CN101488496A - 半导体集成电路 - Google Patents

半导体集成电路 Download PDF

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Publication number
CN101488496A
CN101488496A CNA2009100043862A CN200910004386A CN101488496A CN 101488496 A CN101488496 A CN 101488496A CN A2009100043862 A CNA2009100043862 A CN A2009100043862A CN 200910004386 A CN200910004386 A CN 200910004386A CN 101488496 A CN101488496 A CN 101488496A
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terminal
lead
mos
semiconductor chip
mos fet
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CN101488496B (zh
Inventor
白石正树
岩崎贵之
松浦伸悌
宇野友彰
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NEC Electronics Corp
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Renesas Technology Corp
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Abstract

本发明公开了一种半导体集成电路。功率MOS－FET被用作非绝缘DC/DC变换器中的高端开关晶体管。用作功率MOS－FET源极端子的电极区分别通过连结导线连接到一个外部引线和两个外部引线。所述一个外部引线是连接到用于驱动栅极的通路上的外部端子。所述两个外部引线中的每一个是连接到主电流通路的外部端子。由于以分立的形式连接主电流通路和栅极驱动通路，因此可以减小寄生电感的影响，并提高电压变换效率。

Description

半导体集成电路
本申请是申请号为200410043136.7、申请日为2004年5月13日、发明名称为“半导体器件和电源系统”的发明专利申请的分案申请。
相关申请的交叉引用
本发明申请要求2003年5月14日提交的日本专利申请JP2003-135686的优先权，其内容在此引用作为本申请的参考文献。
技术领域
本发明涉及电源电路或类似电路中使用的开关IC(集成电路)，更具体地，涉及有效地应用于通过DC/DC变换器提高发电效率的技术。
背景技术
最近，增大电源中使用的功率MOSFET(金属氧化物半导体场效应晶体管)的频率，已经用于实现减小电源电路或类似电路的尺寸以及高速负载响应。
特别应用于个人电脑、电脑游戏机或类似装置中的非绝缘DC/DC变换器，表现出趋于电流增大和频率提高，并需要增大流入被驱动的CPU或类似的器件的电流，减小与无源部分对应的扼流圈以及输入/输出电容的尺寸，等等。
非绝缘DC/DC变换器已经广泛应用于，例如，个人电脑、电脑游戏机或类似装置中的电源电路。非绝缘DC/DC变换器，对于装在电子系统中的CPU或类似的器件，需要提高效率和减小尺寸，同时增大电流和降低电压。
非绝缘DC/DC变换器包括高端开关(high side switch)和低端开关(low side switch)。所述开关分别利用功率MOS-FET(金属氧化物半导体-场效应晶体管)。
这些开关通过交替地接通和关断(ON/OFF)执行电压变换，同时高端和低端彼此同步。高端开关是一个控制DC/DC变换器的开关，而低端开关是一个同步的整流开关。
作为一种功率MOS-FET用树脂密封的半导体器件，公知的是，例如，在栅极端子与源极端子之间具有这样一种半导体器件，其中的接地电极端子连接到通过分立半导体芯片形成的接地电极。金线或类似的低阻抗物质，用于连接各个源、栅和接地电极以及它们对应的电极端子，从而当在高频操作下驱动时减小装置的噪音(见，例如，下面的专利文献1)
专利文献1
日本未审查的专利申请，公开号No.2002-009219
发明内容
但是，本发明人已经发现，DC/DC变换器包括如下问题。
图21是本发明人讨论的DC/DC变换器50的示意性电路结构图。DC/DC变换器50包括的一种结构是，每个高端开关51和低端开关52包括功率MOS-FET，并在电源电压Vin和基准电压之间串联。
当高端开关51和低端开关52分别设计成一个封装，例如，出现半导体器件的焊线和外部引线以及安装这些器件的印刷电路板上使用的布线等的寄生电感LdH、LsH、LdL、LgH、LgL和LsL，如图中所示。
特别当高端开关51的寄生电感LsH增大时，出现的问题是，高端开关51的接通和关断损耗变大，从而变换效率大大降低。
图22是表示DC/DC变换器50的损耗部分与LsH的关系的说明图。
在图22中，点染的打点区表示高端开关51的接通损耗，剖面线区表示低端开关52的关断损耗，空白区表示低端开关52的损耗。
如图所示，可以理解的是，当寄生电感LsH增大时，特别是，高端开关51的接通损耗变大，从而变换效率大大降低。
这是因为，当主电流流过寄生电感LsH时，在图21的点A与高端开关51的源极端子之间出现反电动势，从而充分的栅电压不能应用于高端开关51。
由于接通和关断损耗分别与频率或输出电流成比例，损耗部分随着电流增大和效率提高而变大。
本发明的一个目的是提供一种电源系统，甚至当寄生电感大时也能减小对栅电压的影响，并大大提高电压变换效率。
本发明的另一个目的是提供一种半导体器件，它能大大减小寄生电感，从而充分地提高电压变换效率。
从本发明的说明书和附图的描述中，本发明的上述和其它目的及其新颖的特征将变得更加清楚。
本发明申请中描述中的、具有代表性的一个发明内容将简要介绍如下：
(1)本发明提供一种半导体器件，包括用作高端开关的第一功率晶体管，其中所述第一功率晶体管的源极端子分别连接到第一外部连接端子和第二外部连接端子，第一外部连接端子和第二外部连接端子是分别形成的，从而以不同的通路彼此分离。
本发明申请的其它发明内容将简要描述如下：
(2)本发明提供一种半导体器件，包括：用作高端开关的第一功率晶体管，用作低端开关第二功率晶体管，以及驱动第一和第二功率晶体管的驱动器(driver)，其中所述第一功率晶体管的源极端子以不同的通路分别连接到与第二功率晶体管漏极连接的第一外部连接端子，以及连接到所述驱动器中的源极接地端子。
(3)本发明还提供一种半导体器件，包括用作高端开关的第一功率晶体管，用作低端开关的第二功率晶体管，以及驱动控制器，所述驱动控制器包括驱动所述第一功率晶体管和第二功率晶体管的驱动器以及产生用于驱动和控制所述驱动器的控制信号的控制器，其中所述第一功率晶体管的源极端子以不同的通路分别连接到与所述第二功率晶体管漏极连接的第一外部连接端子，以及连接到所述驱动控制器内的源极接地端子。
(4)并且，本发明提供一种电源系统，包括用作高端开关的第一功率晶体管，驱动所述第一功率晶体管的驱动器，平滑线圈(smoothing coil)，以及印刷线路板，所述第一功率晶体管、驱动器和线圈封装在所述印刷线路板上，其中所述第一功率晶体管的源极端子连接到分别形成的、从而以不同的通路彼此分离的第一外部连接端子和第二外部连接端子，其中所述印刷线路板具有第一布线和第二布线，所述第一功率晶体管的第一外部连接端子通过所述第一布线连接到驱动器，所述第一功率晶体管的第二外部连接端子和线圈的连接部分通过所述第二布线连接，并且，第一布线和第二布线分别形成不同的通路。
(5)并且，本发明提供一种电源系统，包括功率模块、驱动器、平滑线圈和印刷线路板，所述功率模块包括用作高端开关的第一功率晶体管和用作低端开关的第二功率模块，所述驱动器用于驱动功率模块，所述功率模块、驱动器和线圈封装在所述印刷线路板上，其中所述第一功率晶体管的源极端子连接到分别形成的、从而以不同的通路彼此分离的第一外部连接端子和第二外部连接端子，其中所述印刷线路板具有第一布线和第二布线，所述第一功率晶体管的第一外部连接端子通过所述第一布线连接到所述驱动器，所述第一功率晶体管的第二外部连接端子和所述线圈的连接部分通过所述第二布线连接，并且，所述第一布线和第二布线分别形成不同的通路。
附图说明
图1是表示根据本发明实施例1、功率MOS-FET结构的一个例子的说明图；
图2是图1所示功率MOS-FET的剖视图；
图3是表示图1所示的功率MOS-FET中芯片布线图的一个例子的说明图；
图4是表示印刷线路板封装的一个例子的说明图，印刷线路板上利用图1所示的功率MOS-FET设计了DC/DC变换器；
图5是封装在图4所示印刷线路板上的DC/DC变换器的等效电路图；
图6是表示图1所示功率MOS-FET的另一个结构例子的说明图；
图7是图6所示功率MOS-FET的剖视图；
图8是表示图7所示功率MOS-FET的另一个结构例子的说明图；
图9是图8所示功率MOS-FET的剖视图；
图10是根据本发明实施例2的、功率IC的结构的一个例子的说明图；
图11是图10所示功率IC的剖视图；
图12是表示印刷线路板封装的一个例子的说明图，印刷线路板上利用图10所示的功率IC设计了DC/DC变换器；
图13是根据本发明实施例3的、功率IC的结构的一个例子的说明图；
图14是图13所示的功率IC的剖视图；
图15是表示绝缘型DC/DC变换器的一个结构例子的电路图，其中使用了图13所示的功率IC；
图16是表示图13所示功率IC的另一个结构例子的说明图；
图17是图16所示功率IC的剖视图；
图18是根据本发明实施例4的、功率IC的结构的一个例子的电路图；
图19是表示图18所示功率IC的结构的说明图；
图20是表示图18所示功率IC的另一个结构例子的说明图；
图21是本发明讨论的DC/DC变换器的示意性电路结构图；
图22是表示图21的DC/DC变换器中形成的损耗部分与寄生电感L的关系的说明图；
图23是表示图5的DC/DC变换器中形成的损耗部分与寄生电感L的关系的说明图。
具体实施方式
下面将按照附图详细地描述本发明的优选实施例。
<实施例1>
图1是表示根据本发明实施例1、功率MOS-FET结构的一个例子的说明图，图2是图1所示功率MOS-FET的剖视图，图3是表示图1所示的功率MOS-FET中芯片布线图的一个例子的说明图，图4是表示印刷线路板封装的一个例子的说明图，该印刷线路板上利用图1所示的功率MOS-FET设计了DC/DC变换器，图5是封装在图4所示印刷线路板上的DC/DC变换器的等效电路图，图6是表示图1所示功率MOS-FET的另一个结构例子的说明图，图7是图6所示功率MOS-FET的剖视图，图8是表示图7所示功率MOS-FET的另一个结构例子的说明图，图9是图8所示功率MOS-FET的剖视图，图23是表示图5的DC/DC变换器中形成的损耗部分与寄生电感L的关系的说明图。
在本发明的这个实施例中，功率MOS-FET(第一功率晶体管和半导体器件)1是用作电源系统的非绝缘DC/DC变换器的高端开关晶体管。这包括封装，例如SOP(小外形封装)。
功率MOS-FET1的封装结构包括引线框架2中心处的芯片焊盘(die pad)2a上安装的半导体芯片3，如图1和2所示。用作功率MOS-FET1的源极端子ST和栅极端子GT的电极区，形成在半导体芯片3的主表面上。用作功率MOS-FET1的漏极端子DT的电极区形成在半导体芯片3的背面。
在图3所示的半导体芯片3中，栅极端子GT在其中心形成在半导体基片HK上，在栅极端子GT与半导体基片HK之间有绝缘膜Z。源极端子ST分别形成在栅极端子GT的两侧，源极端子ST与栅极端子GT之间具有沟道部分。半导体基片HK的背面用作漏极端子DT。
在图1和2中，用作功率MOS-FET1的栅极端子GT的电极区形成在半导体芯片3的主表面的一部分左上部分中。其它的主表面作为源极端子ST的电极区。这些电极区，例如，是通过金属(例如铝Al)的气相沉积形成的。
作为功率MOS-FET1的漏极端子DT的电极区形成在半导体芯片3的背面。电极区是通过金属、例如金(Au)的气相沉积形成的。半导体芯片3的背面压配合在芯片焊盘2a上。
接着，与功率MOS-FET1的漏极端子DT相连接的芯片焊盘2a伸出，因此作为多个(4个)外部引线LD，用作外部的或输出的引线或导线。
用作功率MOS-FET1的栅极端子GT的电极区，通过由诸如金或类似的材料制成的连结导线W，连接到其对应的外部引线LG。用作功率MOS-FET1的源极端子ST的电极区，通过由诸如金或类似的材料制成的连结导线W，分别连接到一根外部引线(第一外部连接端子)LS1和两根外部引线(第二外部连接端子)LS2。
这些芯片焊盘2a、半导体芯片3、外部引线LG、LS1和LS2、部分LG和连结导线W，用密封树脂密封，从而形成封装4。
外部引线LS1是一个外部端子，连接到驱动功率MOS-FET1的栅极的通路，而外部引线LS2是一个外部端子，连接到主电流通路，通过主电流通路输出电压变换的电压。
由于外部引线LG和外部引线LS1在功率MOS-FET1中彼此并排，逆流的电流流入每个它们的寄生电感中，从而可以减小功率MOS-FET1的栅极端子GT的电感。
由于栅极端子GT的电感可以减小，功率MOS-FET1的开关速度可以加快，从而开关损耗可以减小。
所产生的明显效果是，减小功率MOS-FET1的栅极端子GT电感，能防止用作低端开关的MOS-FET的自开启。
自开启是一种现象，当用作低端开关的、内置在功率MOS-FET中的二极管，从回流模式转换到高端开关接通的模式时，低端开关的栅极电压升高，从而导致低端开关故障。
图4表示印刷线路板的封装，在该印刷线路板上使用图1和2所示的功率MOS-FET1设计了DC/DC变换器(电源系统)。虽然图4中没有图示，但实际上输入和输出电容器等等也封装在上面。
DC/DC变换器包括功率MOS-FET1，用作低端开关的功率MOS-FET(第二功率晶体管)5，控制IC(集成电路)6和线圈7。它们封装在印刷线路板上。
如图所示，控制IC6封装在印刷线路板的右侧。控制IC6是驱动器，根据从外部输入的控制信号，分别驱动功率MOS-FET1和5。
功率MOS-FET1封装在控制IC6的左上侧。用作低端开关的功率MOS-FET5封装在功率MOS-FET1下面。线圈7封装在这些功率MOS-FET1和5的左侧。
输入电压Vin通过图案布线H1连接到功率MOS-FET1的四根外部引线LD。控制IC6的一个输出端子通过图案布线H2连接到功率MOS-FET1的外部引线LG。
线圈7的一个连接部分通过图案布线(第二布线)H3连接到功率MOS-FET1的外部引线LS2。控制IC6在源侧的接地端子通过图案布线(第一布线)H4连接到功率MOS-FET1的外部引线LS1。
并且，功率MOS-FET5具有四根外部引线D、三根外部引线S和一根外部引线G，分别作为功率MOS-FET5的漏、源和栅极端子。
功率MOS-FET5的外部引线D连接到图案布线H3。控制IC6的接地端子GND1，通过图案布线H5连接到外部引线S。控制IC6的其它输出端子通过图案布线H6连接到外部引线G。
这样，印刷线路板具有了以下的设计，其中输出引线LS1和控制IC6在源侧的接地端子，通过专用的图案布线H4彼此连接，功率MOS-FET1的栅极驱动通路以及其主电流通路彼此分离。
图5是图4所示的封装在印刷线路板上的DC/DC变换器的等效电路图。
如图5所示，从用作高端开关的功率MOS-FET1的源电极流出的主电流的流动通路，以及用于驱动功率MOS-FET1之栅极的源极接地通路，彼此分离。因此，即使当寄生电感LsH1和LsH2增大时，功率MOS-FET1的栅电压不受其影响。
参看图4，印刷线路板设计成多层线路板，图案布线H2和H4在上面是重叠的，从而可以进一步减小栅极端子的寄生电感。
并且，在图4所示的印刷线路板中，功率MOS-FET5的外部引线S(源极端子)的图案布线H5，以分离的形式提供，或者功率MOS-FET5设计成图1和2所示，图案布线H5以与功率MOS-FET1类似的方式，是分离的并重叠在多层线路板上，从而可以防止功率MOS-FET5的自开启现象。
图23表示图5的DC/DC变换器中形成的损耗与寄生电感LsH1和LsH2的关系。各个区域表示的损耗与图22中的那些相同。
通过对比图22可以清楚，可以理解的是，即使当寄生电感LsH1和LsH2增大时，高端开关的接通损耗与关断损耗变化不大，因此总损耗保持不变。
这是因为，从作为高端开关的功率MOS-FET1的源电极流出主电流的通路，以及驱动MOS-FET1的栅极的源极接地通路是彼此分离的，由于主电流流到寄生电感形成的反电动势在驱动栅极的通路中几乎未生成，对高端开关1可以施加足够的栅电压。
MOS-FET1可以是图1和2所示结构以外的一种结构。例如，不使用连结线(见图1和2)，可以进一步减小电感和电阻。
至于这种情况下的MOS-FET1，MOS-FET1源极端子ST和外部引线LS1和LS2，以及其栅极端子GT和外部引线LG，分别通过金属板8到10彼此互相连接，该金属板是由铝(Al)或铜(Cu)或类似的材料制成的，如图6和7所示。
这些金属板8到10与半导体芯片3的栅极端子GT和源极端子，以及金属板8到10与外部引线LS1、LS2、LG，通过焊料球11彼此互相连接。
而且，形成封装4，以便暴露用作MOS-FET1的背面的引线框架2。因此，减小了引线框架2的热阻，进一步提高了散热性。
并且，MOS-FET1可以按图8和9所示的方式设计，连接外部引线LG和外部引线LS1的金属板12按图6和7所示的结构形成，并且它们可以通过焊料球11连接。
因此，这可以进一步通过流过每个寄生电感的反电流来提高抵消电感的效果，并进一步减小MOS-FET1的栅极端子GT的电感。
这样，根据此实施例，源极端子ST具有分离的外部引线LS1和外部引线LS2。因此，主电流从MOS-FET1的源电极流出的通路，以及用于驱动MOS-FET1之栅极的源极连接通路，可以彼此分离。
这样，可以阻止由于主电流流到每个寄生电感产生的电动势对驱动MOS-FET的栅电压的影响，从而可以提高电压变换效率并且甚至可以处理大电流和高频率。
在印刷线路板中，外部引线LS1和控制IC6的源极接地端子，通过图案布线H4彼此互相连接，驱动功率MOS-FET1的栅极和主电流通路是彼此分离的，从而可以进一步减小功率MOS-FET1的每个寄生电感的影响，并且变换效率可以大大提高。
<实施例2>
图10是根据本发明实施例2的、功率IC的结构的一个例子的说明图，图11是图10所示功率IC的剖视图，图12是表示印刷线路板封装的一个例子的说明图，其中印刷线路板上利用图10所示的功率IC设计了DC/DC变换器。
在本发明实施例2中，功率IC(功率模块)13是一个半导体器件，其中两个用作电源系统的非绝缘DC/DC变换器的高端开关晶体管和低端开关晶体管位于一个封装内。功率IC13的两个晶体管都包括功率MOS-FET。
功率IC13的封装结构包括半导体芯片16和17，分别装在引线框架14和15的中心处的芯片焊盘14a和15a上，如图10和图11所示。这里，半导体芯片16是用于高端开关的功率MOS-FET，半导体芯片17是用于低端开关的功率MOS-FET。
用作源极端子ST和栅极端子GT的电极区分别形成在半导体芯片16和17的主表面上。用作漏极端子DT的电极区形成在半导体芯片16和17的背面。
用作栅极端子GT的电极区，部分形成在半导体芯片16的主表面的右上部，部分形成在半导体芯片17的主表面的左上部。其它的主表面用作源极端子ST的电极区。这些电极区，例如，是通过诸如铝(Al)等的金属的气相沉积形成的。
用作漏极端子DT的电极区形成在半导体芯片16和17的每个背面上。电极区是通过诸如金(Au)的金属的气相沉积形成的。半导体芯片16和17的背面，分别压配合在芯片焊盘14a和15a上。
在半导体芯片16中，有漏极端子DT连接在上面的芯片焊盘14a伸出，从而用作外部引线LD1，作为外部的或向外的连接导线。
并且，通过由金或类似的材料制成的连结导线W，用作栅极端子GT的电极区连接到其相应的外部引线LG1。通过由金或类似的材料制成的连结导线W，用作源极端子ST的电极区分别连接到外部引线(第一外部连接端子)LS3和外部引线(第二外部连接端子)LS4。
在半导体芯片17中，漏极端子DT连接在上面的芯片焊盘15a伸出，从而用作多个外部引线LD2，作为外部的或向外的连接导线。
并且，通过由金或类似的材料制成的连结导线W，用作栅极端子GT的电极区连接到其对应的外部引线LG2。通过由金或类似的材料制成的连结导线W，用作源极端子ST的电极区分别连接到多个外部引线LS5。
这些芯片焊盘14a和15a、半导体芯片16和17、部分外部引线LD1、LD2、LG1、LG2、LS3、LS4和LS5以及连结导线W，用封装树脂密封，从而形成一个封装18。
甚至在此情况下，用作高端开关的功率MOS-FET的半导体芯片16是按如下方式形成的：源极端子ST分离成外部引线LS3和外部引线LS4，外部引线LS3连接到驱动功率MOS-FET的通路上，每根外部引线LS4连接到主电流通路。
这样，从用作高端开关的功率MOS-FET的源电极流出主电流的通路，以及驱动功率MOS-FET的栅极的源极接地通路，可以彼此互相分离。
在一个封装18中形成高端开关和低端开关的两个功率MOS-FET，从而可以基于电源系统的结构获得减小的电源系统尺寸，减小的引线电感和电阻，等等。
图12是表示印刷线路板封装的图，印刷线路板上利用图10和11所示的功率IC13设计了DC/DC变换器。
DC/DC变换器包括功率IC13、控制IC6和线圈7。它们封装在印刷线路板上。
如图所示，控制IC6封装在印刷线路板上部。功率IC13封装在控制IC6下方。线圈7装在功率IC13的右下侧。
输入电压Vin通过图案布线H7连接到其相应的外部引线LD1。控制IC6的一个输出端子通过图案布线H8连接到外部引线LG1。
线圈7的一个连接部分通过图案布线(第二布线)H9连接到三个外部引线LS4。控制IC6在源侧的接地端子通过图案布线(第一布线)H10连接到外部引线LS3。
图案布线H9连接到外部引线LD2。控制IC6的接地端子GND1通过图案布线H11连接到外部引线LS5。控制IC6的其它输出端子通过图案布线H12连接到外部引线LG2。
甚至在这种情况下，印刷线路板具有如下结构：外部引线LS3和控制IC6在源侧的接地端子，通过专门的图案布线H10彼此互相连接，功率IC13的栅极驱动通路及其主电流通路是彼此分离的。
这样，在本发明实施例2中，在高端开关的功率MOS-FET的栅极和源极之间施加的电压没有延迟。因此，可以提高电压变换效率，因为功率MOS-FET的开关时间间隔缩短了。
甚至在功率IC13中，用作低端开关的功率MOS-FET的外部引线LS5，可以以分离的方式形成，这与用作高端开关的功率MOS-FET的方式相似。
并且，图12所示的印刷线路板设计成多层线路板，图案布线H8和H10是以重叠方式布线的，从而可以进一步减小栅极端子的寄生电感。
<实施例3>
图13是根据本发明实施例3的、功率IC的结构的一个例子的说明图，图14是图13所示的功率IC的剖视图，图15是表示绝缘型DC/DC变换器的一个结构例子的电路图，其中使用了图13所示的功率IC，图16是表示图13所示功率IC的另一个结构例子的说明图，图17是图16所示功率IC的剖视图。
在本发明实施例3中，功率IC(功率模块)19是半导体器件，功率MOS-FET和用于驱动功率MOS-FET的驱动器形成在一个封装中。
功率IC19包括半导体芯片22和23，分别装在引线框架20和21的中心处的芯片焊盘20a和21a上，如图13和14所示。这里，半导体芯片22为驱动器，半导体芯片23是功率MOS-FET。
用作电源电压端子VDD、控制信号输入端子IN、输出端子OUT和源极接地端子GND的电极区，分别形成在半导体芯片22的主表面上。
用于施加栅电压的电源电压供应到电源电压端子VDD。控制信号输入到控制信号输入端子IN。输出端子OUT输出用于驱动功率MOS-FET的信号。半导体芯片22是通过诸如银膏的芯片连结材料压配合在芯片焊盘20a上。
用作源极端子ST和栅极端子GT的电极区分别形成在半导体芯片23的主表面上。每个用作漏极端子DT的电极区分别形成在半导体芯片23的背面。
用作栅极端子GT的电极区，部分形成在半导体芯片23的主表面的左上部。其它的主表面用作源极端子ST的电极区。这些电极区是通过诸如铝(Al)的金属的气相沉积形成的。
用作漏极端子DT的电极区形成在半导体芯片23的背面。此电极区是通过诸如金(Au)的金属的气相沉积形成的。半导体芯片23的背面压配合在芯片焊盘21a上。
外部引线V通过诸如金的连结导线W连接到电源电压端子VDD。外部引线SIN通过连结导线W连接到控制信号输入端子IN。
在半导体芯片23中，有漏极端子DT连接在上面的芯片焊盘21a伸出，从而用作外部引线LD3，作为外部的或向外的连接导线。用作栅极端子GT的电极区通过诸如金的连结导线W连接到半导体芯片22的输出端子OUT，用作源极端子ST的电极区通过诸如金的连结导线W连接到半导体芯片22的源极接地端子GND。
用作源极端子ST的电极区通过诸如金的连结导线W连接到引线框架20中的外部引线LS6。半导体芯片22的输出端子OUT通过连结导线W连接到其相应的栅极端子GT。电压确认外部引线G通过连结导线W连接到输出端子OUT。
这样，从用作高端开关的功率MOS-FET的源电极中流出主电流的通路、以及驱动功率MOS-FET的栅极的源极接地通路是彼此分离的。
这些芯片焊盘20a和21a、半导体芯片22和23、部分外部引线V、G、SIN、LD3和LS6以及连结导线W，用封装树脂密封，从而形成一个封装24。
将功率MOS-FET和用于驱动功率MOS-FET的驱动器形成一个封装，可以减小功率MOS-FET的栅极端子的电感及其电阻。
图13和14所示的功率IC19，不但可以应用到非绝缘的DC/DC变换器，而且可以应用到绝缘的DC/DC变换器。
图15是使用四个功率IC19设计的绝缘的DC/DC变换器的电路图，四个功率IC19的每一个表示在图13和14中。
在这种情况下，绝缘的DC/DC变换器包括功率IC(功率模块)19a到19d、控制IC25和25a、电容器26到28、线圈28a以及电源变压器29。
在所采用的一种结构中，电容器26和27以及用于功率IC19a和19b的功率MOS-FET，分别在输入电压Vin上串联连接。电源变压器29的另一初级线圈连接到电容器26和27的连接部分。
电源变压器29的一个初级线圈连接到其相应的功率IC19a和19b的连接部分。控制IC25连接到功率IC19a和19b中的控制信号输入端子IN。
用作开关晶体管的功率IC19c的功率MOS-FET的一个连接部分，连接到电源变压器29的一个次级线圈。用作开关晶体管的功率IC19d的功率MOS-FET的一个连接部分，连接到电源变压器29的另一个次级线圈。
功率IC19d的功率MOS-FET的其它连接部分以及线圈28a的一个连接部分，分别连接到功率IC19c的功率MOS-FET的其它连接部分。
控制IC25a连接到功率IC19c和19d的控制信号输入端子IN。电容器28的一个连接部分连接到线圈28a的其它连接部分。
接着，电源变压器29的次级线圈的中间抽头和电容器28的其它连接部分，用作DC/DC变换器的电压输出区，并将输出电压Vout输出。
控制IC25和25a产生的PWM(脉宽调制)信号应用于功率IC19a到19d的控制信号输入端子IN，从而它们由控制IC25和25a控制。
这样，在本发明实施例3中，由于可以减小用作功率IC19的功率MOS-FET的栅极的电感和电阻，因此可以大在提高电压变换效率。
功率IC19也可以采用图6和7所示的结构，不使用连结导线W，进一步减小电感和电阻。
对于这种情况下的功率IC19，如图16和17所示，半导体芯片22和23上的电极区，以及外部引线V、G、SIN、LD3和LD5，通过由铝(Al)或铜(Cu)或类似的材料制成的金属板30，分别彼此互相连接。
这些金属板30和半导体芯片22和23的电极区，以及金属板30和外部引线V、G、SIN和LD3通过焊料球31分别彼此互相连接。
功率IC19中的封装24的背面形成时，使引线框架20和21分别暴露，从而使散热性进一步提高。并且，封装24设计成薄的形式。
<实施例4>
图18是根据本发明实施例4的、功率IC的结构的一个例子的电路图，图19是表示图18所示功率IC的结构的说明图，图20是表示图18所示功率IC的另一个结构例子的说明图。
在本发明实施例4中，用于非绝缘DC/DC变换器中的功率IC(功率模块)32是一个半导体器件，其中用于高端开关的功率MOS-FET33、低端开关的功率MOS-FET34以及驱动功率MOS-FET33和34的驱动器IC35装在一个封装中，如图18所示。
作为与外部端子对应的外部引线，功率IC32包括：电源电压端子VDD、引导(boot)端子BOOT、电压确认端子GH和GL、控制信号输入端子IN、输入电压端子Vint、接地端子GND1和电压输出端子LX。
电源电压端子VDD是栅电压施加在上面的一个端子，引导端子BOOT是向外提供自举电路的一个端子。电压确认端子GH和GL分别是确认施加在功率MOS-FET33和34的栅极上的电压的端子。
控制信号输入端子IN是输入从控制器IC输出的PWM信号的一个端子。输入电压端子Vint是输入供应到功率MOS-FET33的一个连接部分(漏极)的电压的一个端子。接地端子GND1是一个接地的端子。
驱动器IC35包括用于驱动功率MOS-FET33的驱动器35a，和用于驱动功率MOS-FET34的驱动器35b。
驱动器35a和35b的输入部分连接到控制信号输入端子IN，从而输入PWM波形。驱动器35a的输出部分连接到功率MOS-FET33的栅极，驱动器35b的输出部分连接到功率MOS-FET34的栅极。这些驱动器35a和35b的输出部分分别连接到电压确认端子GH和GL。
一定的电源电压通过输入电压端子Vint供应到功率MOS-FET33的一个连接部分。功率MOS-FET34的一个连接部分连接到功率MOS-FET33的另一个连接部分。功率MOS-FET34的另一个连接部分通过接地端子GND1接地。
引导端子BOOT连接到驱动器35a的电源极端子，功率MOS-FET33的所述另一个连接部分和功率MOS-FET34的所述一个连接部分连接到驱动器35a的基准电位端子。电源电压端子VDD连接到驱动器35b的电源极端子，接地端子GND1连接到驱动器35b的基准电位端子。
电压输出端子LX连接到功率MOS-FET33和功率MOS-FET34的连接部分。电压输出端子LX作为功率IC32的输出部分。
下面描述功率IC32的封装结构。
如图19所示，功率IC32包括QFN(嵌块扁平非引线封装，QuadFlat Non-leaded Package)，例如，对应于一个非引线表面安装的封装。
功率IC32具有如下的结构：半导体芯片39到41分别安装在芯片焊盘36a、37a和38a上，芯片焊盘36a、37a和38a分别位于引线框架36到38的中心处。
半导体芯片39对应于驱动器IC35(见图18)，位于图19的左上部分。半导体芯片40对应于用作高端开关的功率MOS-FET33(见图18)，位于半导体芯片39的右侧。
半导体芯片41对应于用作低端开关的功率MOS-FET34(见图18)，位于半导体芯片38和39的下方。
通过诸如金的连结导线W，对应于外部引线的电源电压端子VDD、引导端子BOOT、电压确认端子GH和GL以及控制信号输入端子IN连接在电极区39a上面，该电极区39a位于半导体芯片39的主表面上。半导体芯片39通过诸如银膏或类似物质的芯片连结材料压配合在芯片焊盘36a上。
用作源和栅极端子的电极区40a和40b，分别形成在半导体芯片40的主表面上。用作漏极端子的电极区形成在半导体芯片40的背面。
用作栅极端子的电极区40b形成在半导体芯片40的主表面的左侧部分上，其它的主表面用作源极端子的电极区40a。这些电极区40a和40b，例如，分别是通过诸如铝(AI)的金属的气相沉积形成的。半导体芯片40的背面的电极区是通过诸如金(Au)的金属的气相沉积形成的。半导体芯片40的背面是压配合在芯片焊盘37a上。
用作栅极端子的电极区41b形成在半导体芯片41的主表面的左侧部分上，用作源极端子的电极区41a形成在半导体芯片41的其它主表面上。用作漏极端子的电极区形成在半导体芯片41的背面。
半导体芯片41的这些电极区41a和41b以及背面的电极区，例如，是通过诸如金(Au)的金属的气相沉积形成的。半导体芯片41的背面压配合在芯片焊盘38a上。
半导体芯片39到41中的电极区39a、40a、40b、41a和41b，以及位于半导体芯片39到41的周围部分上的引线框架36到38的内部引线，通过诸如金的连结导线W而分别连接。
这些内部引线伸出，从而形成外部引线，作为外部连接线。半导体芯片39到41、引线框架36到38的内部引线、芯片焊盘36a、37a和38a以及连结导线W，用封装树脂密封，从而形成矩形封装。
甚至对于功率IC32的封装，安装有半导体芯片39到41的芯片焊盘36a、37a和38a的背面没有封装树脂，从而大大提高了散热性。
这样，本发明实施例4中，功率MOS-FET33、34和驱动器IC35位于一个封装中，从而驱动器IC35与每个功率MOS-FET33和34之间产生的电感和电阻可以大大减小。
由于连接功率MOS-FET33的源极端子ST与驱动器IC35的通路(栅极驱动通路)以及连接功率MOS-FET33的源极端子ST与功率MOS-FET34的漏极端子DT的通路(主电流通路)，在功率MOS-FET33中是彼此分离的，因此可以减小寄生电感的影响，从而大大提高变换效率。
并且，甚至在功率MOS-FET34中，栅极驱动电路和主电流通路是彼此分离的，反向电流流入每个寄生电感，使栅极端子GT的电感减小。因此，可以得到的有益效果是防止自开启。
并且，由于反向电流通路可以从功率MOS-FET33的漏极端子DT到功率MOS-FET34的源极端子ST，因此可以减小主电路的电感。
通过将半导体芯片40与芯片焊盘38a靠近并排列它们，作为第一场效应管的功率MOS-FET33的源40a以及作为第二场效应管的功率MOS-FET34的漏极之间的寄生阻抗可以减小。而且，半导体芯片41排列在芯片焊盘38a的角部附近，从而它可以连接到接地端子GND，而不是输出端子LX。
通过将半导体芯片41与接地端子GND的角部靠近并排列它们，可以将连接第二场效应管34的源极与接地端子GND之间的导线W的布线长度缩短。因此，导线W的布线电阻可以减小，并且可以进一步稳定标准电位GND。
并且，半导体芯片39排列在芯片焊盘36a上，从而半导体芯片39与半导体芯片40之间的距离可以比半导体芯片39与半导体芯片41之间的距离短。
通过排列使半导体芯片39与半导体芯片40之间的距离可以比半导体芯片39与半导体芯片41之间的距离短，第一场效应管33的栅极40b与半导体芯片39之间的寄生阻抗可以减小，并且可以改善第一场效应管33的开关损耗。
通过将这些半导体芯片39、40和41分别排列在芯片焊盘36a、37a和38a的预定位置，可以提高功率IC32的电压变换效率，而不是没有考虑地仅仅将半导体芯片39、40和41排列在芯片焊盘36a、37a和38a上。
在图19中，具有粗线表示的导线W以及比它细的线表示的导线W。粗线表示的导线W，即在第一场效应管33的源极40a与芯片焊盘38a之间连接的导线W，以及在第二场效应管34与接地端子GND之间连接的导线W，其宽度为50微米。并且，在图19中，由细线表示的导线W的宽度为30微米。因此，电压变换效率可以提高，半导体芯片40与输出端子LX之间的寄生阻抗可以减小，并且接地端子GND与半导体芯片之间的寄生阻抗可以减小。在图19中，半导体芯片40和芯片焊盘38a，通过两根或多根平行的粗导线W电气连接。而且，接地端子GND与半导体芯片41之间通过两根或多根平行的粗导线W电气连接。这样，通过连接两根或多根平行的粗导线W，可以减小每个布线通路上的寄生阻抗，并且也可以进一步稳定标准电位GND。
尽管本发明实施例4中描述的是使用连结导线W形成功率IC32的情况，但功率IC32可以采用某种结构，从而不使用连结导线，例如，如图20所示，进一步减小电感和电阻。
在这种情况的功率IC32中，分别位于半导体芯片39到41上的电极区39a、40a、40b、41a和41b，以及引线框架36到38的内部引线，通过由铝或铜或类似材料制成的金属板42分别连接。
这些金属板42和电极区39a、40a、40b、41a和41b，以及金属板42和引线框架36到38的内部引线，分别通过焊料球连接。
下面考虑半导体芯片39的电极区39a与外部端子(电源电压端子VDD、引导端子BOOT、电压确认端子GH和GL以及控制信号输入端子IN)的连接是由连结导线W形成的。
这样，每根连接导线的电感和电阻可以进一步减小，因为使用了这种金属板42的连接，从而电压变换可以高效率地进行。
尽管本发明实施例4描述的情况是，功率IC32包括用于高端开关的功率MOS-FET33、用于低端开关的功率MOS-FET34以及用于驱动功率MOS-FET33和34的驱动器IC35，但功率IC可以具有驱动控制器，其中驱动器和控制器形成在一个半导体芯片中，这里的控制器产生用于驱动和控制所述驱动器的控制信号。
尽管按照图示的实施例具体描述了本发明人做出的本发明，但本发明并不限于此。毫无疑问，在不偏离本发明要旨的范围内可以做出不同变化。
下面将简要解释本发明申请中揭示的、本发明一个代表性实施例得到的好的效果：
(1)DC/DC变换器的电压变换效率可以大大提高；
(2)本发明可以采用大电流和高频率，而不降低效率；
(3)由于上述(1)和(2)，可以提供一种电源系统，其中大大提高了发电效率。

Claims (8)

1.一种组装在一个模塑封装中的半导体集成电路，包括：
第一半导体芯片，包括第一功率MOS FET；
第二半导体芯片，包括第二功率MOS FET；
第三半导体芯片，包括预驱动器，所述预驱动器驱动第一功率MOSFET和第二功率MOS FET。
2.根据权利要求1的半导体集成电路，其中所述封装包括：
控制信号输入端子；
第一输出端子；
第一电压输入端子；
第二电压输入端子，施加给第二电压输入端子的电压低于施加给第一电压输入端子的电压；以及
第三电压输入端子，施加给第三电压输入端子的电压高于施加给第一电压输入端子的电压，
其中，第一功率MOS FET的漏极端子耦接到第一电压输入端子，
第二功率MOS FET的源极端子耦接到第二电压输入端子，
第一功率MOS FET的源极端子和第二功率MOS FET的漏极端子耦接到第一输出端子，并且
第三半导体芯片耦接到第二电压输入端子和第三电压输入端子。
3.根据权利要求2的半导体集成电路，其中所述封装还包括：
第二输出端子；
第三输出端子，并且
其中，第二输出端子耦接到第一功率MOS FET的栅极端子和第三半导体芯片的第一输出端子，
第三输出端子耦接到第二功率MOS FET的栅极端子和第三半导体芯片的第二输出端子。
4.根据权利要求3的半导体集成电路，其中所述封装还包括：
第一电压确认端子，耦接到第一功率MOS FET的栅极端子；以及
第二电压确认端子，耦接到第二功率MOS FET的栅极端子。
5.根据权利要求4的半导体集成电路，其中所述封装还包括：
第四电压输入端子，并且
其中第四电压输入端子耦接到第三半导体芯片。
6.根据权利要求3的半导体集成电路，其中，
使用第一连结导线耦接第一输出端子和第一功率MOS FET的栅极端子，
使用第二连结导线耦接第二输出端子和第二功率MOS FET的栅极端子，
第三半导体芯片包括：
第一输入端子，其接收第一功率MOS FET的源极端子的电压；以及
第二输入端子，其接收第二功率MOS FET的源极端子的电压，
使用第三连结导线耦接第一输入端子和第一功率MOS FET的源极端子，
使用第四连结导线耦接第二输入端子和第二功率MOS FET的源极端子，
第一连结导线邻近第三连结导线，并且
第二连结导线邻近第四连结导线。
7.根据权利要求3的半导体集成电路，其中，
使用第一金属板耦接第一输出端子和第一功率MOS FET的栅极端子；
使用第二金属板耦接第二输出端子和第二功率MOS FET的栅极端子；
第三半导体芯片包括：
第一输入端子，其接收第一功率MOS FET的源极端子的电压；以及
第二输入端子，其接收第二功率MOS FET的源极端子的电压，
使用第三金属板耦接第一输入端子和第一功率MOS FET的源极端子，
使用第四金属板耦接第二输入端子和第二功率MOS FET的源极端子，
第一金属板邻近第三金属板，并且
第二金属板邻近第四金属板。
8.一种半导体集成电路，包括：
控制端子；
第一电压输入端子和第二电压输入端子；以及
输出端子，
该半导体集成电路包括第一MOS FET、第二MOS FET和设置在安装基片上的第三半导体芯片；
形成第一MOS FET的半导体基片的背面耦接到第一电压输入端子，
形成第二MOS FET的半导体基片的表面上形成的第一端子耦接到第二电压输入端子，
控制端子耦接到第三半导体芯片，
第三半导体芯片上形成的第一输出端子耦接到包括第一MOS FET的基片的表面上形成的第一端子，
第三半导体芯片上形成的第二输出端子耦接到包括第二MOS FET的基片的表面上形成的第二端子。
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CN104779815A (zh) * 2015-04-02 2015-07-15 西安交通大学 一种可替换IGBT模块的SiC MOSFET智能功率集成模块
CN107658283A (zh) * 2017-09-30 2018-02-02 杭州士兰微电子股份有限公司 用于电机驱动的集成功率模块和智能功率模块
CN107658283B (zh) * 2017-09-30 2024-05-07 杭州士兰微电子股份有限公司 用于电机驱动的集成功率模块和智能功率模块

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KR20110015043A (ko) 2011-02-14
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KR101086751B1 (ko) 2011-11-25
KR101116197B1 (ko) 2012-03-07
TW201145477A (en) 2011-12-16
US7109577B2 (en) 2006-09-19
US20040227547A1 (en) 2004-11-18
TW200504978A (en) 2005-02-01
TWI467712B (zh) 2015-01-01
KR20110122808A (ko) 2011-11-11
CN100474571C (zh) 2009-04-01
TWI371838B (zh) 2012-09-01
KR20040098562A (ko) 2004-11-20
JP2004342735A (ja) 2004-12-02
CN1551342A (zh) 2004-12-01
CN101488496B (zh) 2012-05-23

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