CN100413065C - 至少具有部分封装的电路器件及其形成方法 - Google Patents

至少具有部分封装的电路器件及其形成方法 Download PDF

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Publication number
CN100413065C
CN100413065C CNB200480010401XA CN200480010401A CN100413065C CN 100413065 C CN100413065 C CN 100413065C CN B200480010401X A CNB200480010401X A CN B200480010401XA CN 200480010401 A CN200480010401 A CN 200480010401A CN 100413065 C CN100413065 C CN 100413065C
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circuit
conductive layer
layer
circuit devcie
devcie
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CN1774802A (zh
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乔治·利尔
赵杰华
艾德华·R·普拉克
罗伯特·J·温策尔
布莱恩·D·索耶
大卫·G·汪托尔
马克·阿兰·曼格拉姆
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NXP USA Inc
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Freescale Semiconductor Inc
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

在一个实施例中，将电路器件(15)设置在导电层(10)的开口内，然后用包封(24)部分包封，使得电路器件(15)的有源面与导电层(10)共面。在该实施例中，可以使用导电层(10)的至少一部分作为参考电压平面(例如接地平面)。在一个实施例中，将电路器件(15)设置导电层(100)上，使得电路器件(115)的有源面处于导电层(100)和电路器件(115)的相反表面之间。在该实施例中，导电层(100)具有至少一个开口(128)，以暴露电路器件(115)的有源面。对于某些实施例来说，包封(24，126，326)可以是导电的，对于其它实施例来说，是非导电的。

Description

至少具有部分封装的电路器件及其形成方法
技术领域
本发明总的来说涉及电路器件，更具体地说，涉及至少具有部分封装的电路器件及其形成方法。
背景技术
所有类型的电路器件、包括(但不限于)电、光、有源和无源器件通常以保护该电路器件、但需要时允许外部耦连到该电路器件的形式封装，并且尽可能低成本，同时仍然允许电路器件的功用。利用能够改善电路器件封装的标准的、已经存在的工具和工艺是电路器件封装进步的低成本方案。
商业传递或者销售仅被部分封装的电路器件变得更普遍。然后可以将这些部分封装的电路器件与其它电路器件结合，并且以最后的形式封装，得到需要的最后的电路。
发明内容
本发明提供一种至少具有部分封装的器件，包括：具有第一表面和与第一表面相反的第二表面的电路器件，其中第一表面包括有源电路；具有第一表面、与第一表面相反的第二表面和至少一个开口的导电层，其中：该至少一个开口至少部分围绕电路器件，电路器件的第一表面与导电层的第一表面共面，导电层包括第一参考电压平面；电耦连到第一参考电压平面的电接点，所述电接点使得能电接触所述第一参考电压平面；和至少部分填充所述至少一个开口内所述电路器件和导电层之间的间隙的包封层。
本发明还提供一种至少具有部分封装的器件，包括：具有第一表面和与第一表面相反的第二表面的电路器件，其中第一表面包括有源电路；具有第一表面、与第一表面相反的第二表面和至少一个开口的导电框，其中：电路器件在所述至少一个开口内，导电框包括参考电压平面；电耦连到第一参考电压平面的电接点，所述电接点使得能电接触所述第一参考电压平面；和覆盖电路器件的第二表面和导电框的第二表面的包封。
本发明又提供一种用于形成至少具有部分封装的器件的方法，包括：提供具有第一表面、与第一表面相反的第二表面和至少一个开口的导电层；在所述至少一个开口内设置电路器件，其中电路器件的有源表面与导电层的第一表面共面，并且其中导电层包括参考电压平面；和形成包封层以至少部分填充所述至少一个开口内所述电路器件和导电层之间的间隙。
本发明再提供一种至少具有部分封装的器件，包括：具有第一表面、与第一表面相反的第二表面并具有侧壁表面的电路器件，其中第一表面包括有源电路；和覆盖电路器件的侧壁表面和第二表面并且露出电路器件的第一表面的至少一部分的导电包封。
本发明还提供一种至少具有部分封装的器件，包括：具有第一表面和与第一表面相反的第二表面的导电层；覆盖导电层的电路器件，该电路器件具有第一表面和与第一表面相反的第二表面，其中第一表面包括有源电路，电路器件的第一表面在电路器件的第二表面和导电层的第一表面之间；和覆盖导电层的第一表面的包封层。
本发明又提供一种至少具有部分封装的器件，包括：具有第一表面和与第一表面相反的第二表面的导电层；覆盖且物理接触导电层的第一表面的粘合层；覆盖粘合层的电路器件，该电路器件具有第一表面和与第一表面相反的第二表面，其中第一表面包括有源电路且与粘合层物理接触；包封层覆盖导电层的第一表面。
本发明再提供一种用于形成至少具有部分封装的器件的方法，包括：提供具有第一表面和与第一表面相反的第二表面的导电层；在导电层上定位电路器件，该电路器件具有第一表面和与第一表面相反的第二表面，其中第一表面包括有源电路，电路器件的第一表面处于电路器件的第二表面和导电层的第一表面之间；和形成覆盖导电层的第一表面的包封层。
附图说明
借助于例子说明本发明，并且不受附图的限制，其中相同的附图标记表示相同的元件，其中：
图1-4示出了根据本发明一个实施例形成的至少具有部分封装的多个电路器件的顺序截面图；
图5示出了根据本发明一个实施例形成的图4的至少具有部分封装的多个电路器件的底视图；
图6示出了根据本发明一个实施例形成的至少具有部分封装的多个电路器件的截面图；
图7示出了根据本发明一个实施例形成的至少具有部分封装的电路器件的顶视图；
图8示出了根据本发明一个实施例形成的图7的至少具有部分封装的电路器件的截面图；
普通技术人员应理解，为了简单和清楚而说明了图中的元件，并且不需要按比例绘制这些元件。例如，相对于其它元件，可以放大图中某些元件的尺寸，以帮助理解本发明的实施例。
具体实施方式
图1示出了覆盖粘合层12设置的导电层10的截面图。在本发明的一个实施例中，使用支撑结构9来支撑粘合层12。导电层10和粘合层12之间的界面形成平面11。导电层10可以由导电的任何材料形成。在本发明的一些实施例中，导电层10可以是导电框，例如引线框。引线框可以由适当性能的任何导电材料形成，例如铜或者42号合金。在本发明的可选择实施例中，导电层10可以是导电基板，例如包含多个互连层的多层基板。粘合层12可以由粘性的任何材料形成。在本发明的一个实施例中，粘合层12是具有沿着平面11与导电层10接触的粘接表面的胶带。在本发明的可以选择的实施例中，粘合层12可以不具有涂覆的粘接剂，直到图2。在本发明的一个实施例中，导电层10具有开口405-407。本发明的可选择实施例可以具有导电层10中的任何形状、任何数量的开口。
图2依序示出了图1的截面图，其中添加了多个电路器件14。多个电路器件14包含放置在开口405中的电路器件15、放置在开口406中的电路器件16和放置在开口407中的电路器件17。注意，开口405-407至少部分围绕它们相应的电路器件15-17。在本发明的某些实施例中，开口405-407完全围绕它们相应的电路器件15-17。注意，在本发明的可以选择的实施例中，多于一个的电路器件(例如15-17)可以位于单个开口(405-407)内。多个电路器件14的一个或者多个可以是执行相同功能的相同的电路器件，或者可以是执行不同功能的不同的电路器件。在本发明的某些实施例中，在电路器件14放置到它们各自的开口405-407中之前，给电路器件14的一个或者多个施加粘接剂。然后施加给一个或者多个电路器件14的粘接剂与层12接触，形成在后续的包封步骤(参见图3)中将电路器件保持到位的粘合层12的粘接部分。
电路器件14至少具有一个表面，该表面是有源的并且基本上与导电层10的表面共面(例如，沿着图2所说明的实施例中的平面11)。在说明的实施例中，认为电路器件15-17的有源表面是电路器件15-17的底部，这些底面粘性耦连于粘合层12。在图2所说明的实施例中，电路器件15的有源表面包含多个接触焊盘18，电路器件16的有源表面包含多个接触焊盘19，电路器件17的有源表面包含多个接触焊盘20。本发明的可选择实施例可以包含每单个电路器件14上的多个或者更少接触焊盘。这些接触焊盘18-20利用本领域已知的各种工艺和材料以任何方式形成在电路器件15-17上。在本发明的一个实施例中，至少一个开口405-407(参见图1)至少部分围绕至少一个电路器件15-17。
图3依序示出了图2的截面图，其中添加了模具21，由此形成空腔22。利用任何适当的包封方法(例如注入模制或者转移模制)通过一个或者多个开口414提供包封。可以选择使用其它的包封方法，例如分配模制(dispense molding)和空腔注入模制。
图4依序示出了图3的截面图，其中在包含电路器件14和导电层10之间的一个或者多个间隙的空腔被包封层24部分或者全部填充之后除去了模具21。对于本发明的某些实施例，例如，如果粘合层12是粘接带，则可以除去粘合层12。在本发明的某些实施例中，包封层24可以是能够模制的任何类型的非导电材料，例如热固性模制化合物或者填充的热塑性树脂，作为绝缘材料。在本发明的可选择实施例中，包封层24可以是能够模制的任何类型的导电材料，例如具有金属填料的热固性环氧树脂或者具有金属填料的热塑性塑料。金属填料可以是任何类型的导电材料，例如银、铜、导电涂覆的聚合物球和导电的纳米粒子。金属填料可以是粒子形式。注意，在本发明的某些实施例中，导电层10或者其一部分作为参考电压面例如地平面或者较高的电压参考面。这种电压参考面的一个好处是能够在互连层328内制造一个或者多个控制的阻抗电路，例如导体461(参见图8)。
图5示出了根据本发明的一个实施例形成的图4的至少具有部分封装的多个电路器件15-17的近似底视图。图5所示的结构还包含图4中未示出的多个附加电路器件28。在本发明的可选择实施例中，电路器件15-17和28可以包含任何数量的电路器件，并且可以以任何合理尺寸的一维或者二维阵列设置。该阵列可以对称，也可以不对称。
在本发明的一个实施例中，导电层10是作为具有开口以容纳电路器件15-17和28的电压参考平面的阵列示出的。注意，在图5所示的本发明的实施例中，通过多个梁(spar)(例如梁416)将电压参考平面保持在一起，这些梁是导电层10的一部分，并且为了清楚在图1-4中未示出。本发明的可选择实施例可以不使用梁416。梁416提供了物理连接具有开口(例如405-406)的多个电压参考平面的方式，使得利用相同的导电层10可以同时进行多于一个电路器件(例如15和16)的部分或者完全封装。在本发明的某些实施例中，可以将梁416固定到外围栏(outer rail)或者框(未示出)上。然后通过切割梁416和位于参考平面405-407之间的其它材料可以得到单体。注意，电路器件15-17和28可以通过切割围绕每单个电路器件15-17、28的适当梁416而分离。
图6示出了根据本发明一个实施例形成的至少具有部分封装多个电路器件115-117的截面图。粘合层112插在导电层100和电路器件115-117之间。包封层126可以按与图4的包封层24相同的方式和材料形成。可以使用导电层100中的一个或者多个开口128，以允许与电路器件115的有源面上的一个或者多个接触焊盘118电连接。可以使用导电层100中的一个或者多个开口129，以允许与电路器件116的有源面上的一个或者多个接触焊盘119电连接。可以使用导电层100中的一个或者多个开口130，以允许与电路器件117的有源面上的一个或者多个接触焊盘120电连接。注意，在放置电路器件(例如115-117)的区域中可以减薄导电层100，以便简化用来通过开口128-130形成互连的工艺。在图6所示的实施例中，导电层100作为电路器件117-119和后来添加的任何互连层(例如图8中的328)之间的应力解耦层，从而提高潜在的可靠性。除了导电层100之外，该应力缓冲功能可以作为参考平面。
注意，在图6所示的实施例中，电路器件115-117的有源面基本上与导电层100的一个表面共面，而相反的表面(有源或者非有源表面)可以总体上通过包封层126包封(对于电路器件116和117)，或者可以基本上与包封层126的相反表面431共面(对于电路器件115)。如果器件115的相反表面430基本上与包封层126的相反表面431共面，则能够直接将热沉(未示出)附着到电路器件115的表面430，以便从电路器件115散热。如果电路器件115是使用大功率的电路器件，散热尤其重要。电路器件(例如电路器件15)的相反表面430基本上与包封层126的表面431共面可以用于本发明的任何适当的实施例，包括例如图4和图8所示和描述的实施例。还应注意，具有有源表面的每个电路器件115-117的底部位于电路器件115-117的顶部和导电层100的顶部之间。
导电层100可以由导电并且具有适当性能的任何材料形成。在本发明的某些实施例中，导电层100可以是导电框，例如引线框。引线框可以由任何导电材料形成，例如铜或者42号合金。在本发明的可选择实施例中，导电层100可以是导电基板，例如包含多个互连层的多层基板。粘合层112可以由粘性的任何材料形成。在本发明的一个实施例中，粘合层112是具有与导电层100接触的粘接表面的胶带。在本发明的可选择实施例中，粘合层112可以不具有涂覆的粘接剂，直到利用夹在粘合层12和电路器件115-117之间的粘接剂将电路器件115-117放置在导电层100上。在某些实施例中，粘合层12可以是带或者液体粘接剂，例如在放置电路器件115-117之前通过浸入、分配或者压印转移而涂覆的环氧树脂。
图6还示出了导电层100可以具有基本上与包封层126的同一相反表面431共面的一个或者多个部分。图6示出了其中电子器件102利用本领域已知的各种方法例如焊接或者导电粘接剂通过接触焊盘/互连101耦连到部分导电层100的例子。电子器件102可以是任何类型的有源或者无源器件，并且可以具有任何数量的端子。注意，在本发明的某些实施例中，电子器件102不埋置到包封126中，因此容易测试和替换。
图7示出了根据本发明的一个实施例形成的至少具有部分封装的电路器件200的顶视图。在本发明的一个实施例中，电路器件200可以是集成电路芯片。注意，在本发明的某些实施例中，电路器件15-17、28(参见图1-5)和电路器件115-117(参见图6)也可以是集成电路芯片。图8示出了图7的至少具有部分封装的电路器件200的截面图。
图7示出了电路器件200，电耦连电路器件200，以从称作输入/输出电源201的电压参考平面接收较高电压、从称作芯电源203的电压参考平面接收较高电压、从称作输入/输出接地204的电压参考平面接收较低或者地电压和从称作芯接地202的电压参考平面接收较低或者地电压。在本发明的某些实施例中，输入/输出电源201、芯电源203、输入/输出接地204和芯接地202是彼此电隔离的导电层的所有部分。在本发明的一个实施例中，输入/输出电源201和输入/输出接地204通过去耦电容器212和213电去耦。同样，芯电源203和芯接地202可以通过去耦电容器214和215电去耦。注意，在所示实施例中，使用接触焊盘216电连接电容器212-215和电压参考平面201-204。去耦电容器212-215可以利用本领域已知的各种方法例如焊接或者导电粘接剂电耦连到接触焊盘216。
参考图7和8，注意，在本发明的某些实施例中，电路器件200可以通过互连层328的部分450电耦连到导电层(201-204，224)的芯电源部分203。在可选择的实施例中，电路器件200可以电耦连到导电层(201-204，224)的任何需要的部分(例如201-204)。注意，导电层(201-204，224)或者其电隔离部分可以作为一个或者多个参考电压平面。
对于本发明的某些实施例，包封层326(参见图8)可以是导电的。如果包封层326导电，则可以形成穿过导电层(202，203，224)到达互连层328的一个或者多个开口(例如开口470)。开口470是导电层(203、202、224)的部分203中的开口。借助于通路332，开口470可以用来电连接包封326和互连层328的一个或者多个部分。例如，借助于开口470、通路332和互连层328，通过将适当的电压(例如电源或者地)耦连到包封层326，可以使用包封层326作为电压参考平面。在本实施例中，即使导电层202、203的覆盖区域小，在包封层326作为参考平面的情况下，受控的阻抗电路、例如导体460(参见图8)也能够在互连层328内。包封层326还可以执行电子器件200的电屏蔽功能。注意，如果包封层326是导电的，那么由于应从电学上缩短其端子的事实，因此电子器件(例如220)将不包封在包封层326内，如图8所示。
本发明的可选择实施例可以不用导电的包封。参考图8，如果包封层326是非导电的，则可以覆盖电路器件200形成导电层415，以便提供电屏蔽和电压参考。注意，可以作为多步骤包封工艺的一部分形成导电层415。那么作为多步骤包封工艺的后续部分，可以覆盖层415形成非导电包封层326。在本发明的可选择实施例中，多于一个的电路器件(例如200)可以位于单个的导电层415内。
互连层328可以包含互连的一级或者多级，并且可以利用本领域已知的各种电路化工艺例如高密度互连内建、层叠或者薄膜工艺形成。在本发明的一些实施例中，穿过柔顺(compliant)聚合物层412的通路331将互连层328的接触焊盘330耦连导电球334。本发明的可选择实施例可以具有多个这种通路，以电连接互连层328和多个球(例如334)。导电球334可以由任何适当的导电材料形成，例如焊料或者围绕聚合物芯338的焊料336。注意，在本发明的某些实施例中，互连层328下面的结构(例如412、331、330、334)可以起到提供互连层328和其它结构(未示出)之间的应力缓冲的作用，所述其它结构是后来附着到导电球上的结构(例如334)。
在本发明的某些实施例中，电子器件220、无论有源还是无源都可以电耦连到导电层224的顶表面上，该顶表面自身是导电层202的隔离部分。注意，电耦连到电子器件220左端子的224的左部分可以与电耦连到电子器件220的右端子的224的右部分电隔离。在一个实施例中，电子器件220借助于在224的顶表面上制造的一个或者多个接触焊盘228电耦连到导电层224。这样，电子器件220可以借助于导电层224电耦连到互连层328。在本发明的一些实施例中，包封层326的一个或者多个部分(例如226)可以起到绝缘导电层的一个或者多个部分(例如224)的作用。可以利用本领域已知的各种方法例如焊接或者导电粘接进行器件220的电耦连。注意，在本发明的一些实施例中，与导电层的其余部分202-203相比，可以降低导电层224的高度，允许电子器件220的较低附着高度和封装的较低潜在轮廓(potential profile)。
导电层(202、203、204)可以由导电的任何适当材料形成。在本发明的某些实施例中，导电层(202、203、204)可以是导电框，例如引线框。引线框可以由任何导电材料形成，例如铜或者42号合金。在本发明的可选择实施例中，导电层(202、203、204)可以是导电基板，例如包含多个互连层的多层基板。
注意，如果利用与包封326相同种类的材料形成互连层328，例如液晶聚合物(LCP)或者聚苯硫醚(PPS)等的热塑性塑料，那么电路器件200及其328内的相应互连可以封入材料的恰当的、无缝单块中，并且表示图8所示包封326和互连层328之间界面的水平线将不再存在。这样的封装结构说明由于较少的潮气入侵和会分层的不同材料之间的界面数量减少而提高了可靠性。在本发明的一个实施例中，对于包封326和互连层328使用相同种类材料的情况下，可以使用用于制造互连层328的叠层技术。而且，注意，在这种情况下，可以使用注入模制来施加包封326。
注意，在苯发明的某些实施例中，其中包封126是非导电的，导电层的一个或者多个部分(例如图6的100；图7的201-204和224；图8的224)与导电层的其它部分可以物理分离或者电隔离，以提供与其它器件(例如图6的102和图8的220)的电连接。
在前面的说明书中，已经参考具体实施例描述了本发明。然而，本领域技术任意应理解，在不离开如下权利要求所提出的本发明范围的情况下，可以进行各种修改和改变。据此，说明书和附图应认为是说明性的，而非限制性的。这样的修改都包含在本发明的范围内。
上面根据具体实施例描述了利益、其它优点和问题的技术方案。然而，会使任何利益、优点或者方案出现或者变得更显著的利益、优点、问题的技术方案和任何部件都不应认为是任何或者所有权利要求的临界的、必须的或者必要的特征或者部件。如这里所使用的，术语“包括”及其任何其它变化都应覆盖非排除的包含，使得包括元件列表的工艺、方法、制品或者装置都不仅包含那些元件，而且可以包含没有列出的其它元件或者对于这种工艺、方法、制品或者装置来说固有的元件。

Claims (84)

1. 一种至少具有部分封装的器件，包括：
具有第一表面和与第一表面相反的第二表面的电路器件，其中第一表面包括有源电路；
具有第一表面、与第一表面相反的第二表面和至少一个开口的导电层，其中：该至少一个开口至少部分围绕电路器件，电路器件的第一表面与导电层的第一表面共面，导电层包括第一参考电压平面；
电耦连到第一参考电压平面的电接点，所述电接点使得能电接触所述第一参考电压平面；和
至少部分填充所述至少一个开口内所述电路器件和导电层之间的间隙的包封层。
2. 权利要求1的器件，其中包封层覆盖导电层的第二表面的至少第一部分。
3. 权利要求2的器件，其中包封层覆盖电路器件的第二表面的至少一部分。
4. 权利要求2的器件，进一步包括与导电层的第二表面的第二部分物理接触的第二电路器件。
5. 权利要求4的器件，其中从无源器件、光学器件、有源器件、半导体器件、天线和微机电系统(MEMS)器件中选择第二电路器件。
6. 权利要求4的器件，其中包封层覆盖第二电路器件的至少一部分。
7. 权利要求1的器件，其中第一参考电压平面电耦连到电路器件。
8. 权利要求1的器件，其中导电层包括多个互连层。
9. 权利要求1的器件，其中包封层覆盖电路器件的第二表面的至少一部分。
10. 权利要求9的器件，其中包封层包括导电材料。
11. 权利要求10的器件，进一步包括覆盖包封层的第二包封层。
12. 权利要求1的器件，其中包封层包括导电材料。
13. 权利要求1的器件，进一步包括第二电路器件，该第二电路器件具有耦连到导电层的第一物理分离部分的第一端子，以及耦连到导电层的第二物理分离部分的第二端子。
14. 权利要求13的器件，进一步包括覆盖电路器件和导电层的第一表面的互连层，其中第二电路器件通过第一和第二物理分离部分电耦连到互连层。
15. 权利要求1的器件，其中导电层包括彼此电隔离的至少两个部分。
16. 权利要求15的器件，其中所述至少两个部分之一包括所述第一电压参考平面。
17. 权利要求16的器件，其中所述至少两个部分中的另一个包括第二电压参考平面。
18. 权利要求17的器件，进一步包括第二电路器件，该第二电路器件具有耦连到第一电压参考平面的第一端子和耦连到第二电压参考平面的第二端子。
19. 权利要求1的器件，进一步包括覆盖电路器件和导电层的第一表面的互连层。
20. 权利要求19的器件，其中互连层包括多个互连级。
21. 权利要求19的器件，进一步包括覆盖互连层的柔顺层。
22. 权利要求21的器件，其中柔顺层包括耦连到互连层的多个导电通路。
23. 权利要求22的器件，进一步包括耦连到导电通路的多个导电球。
24. 权利要求19的器件，其中互连层包括与包封层相同的材料。
25. 权利要求24的器件，其中该相同的材料是选自由液晶聚合物和聚苯硫醚(PPS)构成的组的材料。
26. 权利要求1的器件，进一步包括多个电路器件，其中导电层包括多个开口，其中所述多个开口的每一个都至少部分围绕所述多个电路器件之一。
27. 权利要求26的器件，其中所述多个电路器件中的每一个都具有包括有源电路的第一表面和与第一表面相反的第二表面，其中每个电路器件的第一表面与导电层的第一表面共面。
28. 权利要求27的器件，其中包封层覆盖多个电路器件的第二表面的至少一部分。
29. 权利要求28的器件，其中包封层包括导电材料。
30. 一种至少具有部分封装的器件，包括：
具有第一表面和与第一表面相反的第二表面的电路器件，其中第一表面包括有源电路；
具有第一表面、与第一表面相反的第二表面和至少一个开口的导电框，其中：电路器件在所述至少一个开口内，导电框包括参考电压平面；
电耦连到第一参考电压平面的电接点，所述电接点使得能电接触所述第一参考电压平面；和
覆盖电路器件的第二表面和导电框的第二表面的包封。
31. 权利要求30的器件，进一步包括与导电层的第二表面的第一部分物理接触的第二电路器件。
32. 权利要求31的器件，其中第二电路器件选自由无源器件、光学器件、有源器件、半导体器件、天线以及微机电系统(MEMS)器件构成的组。
33. 权利要求31的器件，其中包封层覆盖第二电路器件。
34. 权利要求30的器件，其中包封层包括导电材料。
35. 权利要求30的器件，其中包封层包括导电部分，所述导电部分覆盖电路器件的第二表面。
36. 权利要求30的器件，其中导电层包括彼此电隔离的至少两个部分，其中该至少两个部分之一包括所述参考电压平面。
37. 权利要求36的器件，进一步包括第二电路器件，该第二电路器件具有耦连到所述至少两个部分之一的第一端子和耦连到所述至少两个部分中的另一个的第二端子。
38. 一种用于形成至少具有部分封装的器件的方法，包括：
提供具有第一表面、与第一表面相反的第二表面和至少一个开口的导电层；
在所述至少一个开口内设置电路器件，其中电路器件的有源表面与导电层的第一表面共面，并且其中导电层包括参考电压平面；和
形成包封层以至少部分填充所述至少一个开口内所述电路器件和导电层之间的间隙。
39. 权利要求38的方法，进一步包括：
将粘合层附着到导电层上，其中在该至少一个开口内设置电路器件的步骤包括在粘合层上设置电路器件。
40. 权利要求39的方法，进一步包括在形成包封层之后去除粘合层。
41. 权利要求38的方法，其中形成包封层的步骤包括形成覆盖电路器件和导电层的第二表面的模制化合物。
42. 一种至少具有部分封装的器件，包括：
具有第一表面、与第一表面相反的第二表面并具有侧壁表面的电路器件，其中第一表面包括有源电路；和
覆盖电路器件的侧壁表面和第二表面并且露出电路器件的第一表面的至少一部分的导电包封。
43. 权利要求42的器件，其中导电包封包括参考电压平面。
44. 权利要求43的器件，其中导电包封电耦合于电路器件。
45. 权利要求42的器件，其中导电包封具有与电路器件的第一表面共面的第一表面。
46. 一种至少具有部分封装的器件，包括：
具有第一表面和与第一表面相反的第二表面的导电层；
覆盖导电层的电路器件，该电路器件具有第一表面和与第一表面相反的第二表面，其中第一表面包括有源电路，电路器件的第一表面在电路器件的第二表面和导电层的第一表面之间；和
覆盖导电层的第一表面的包封层。
47. 权利要求46的器件，进一步包括在电路器件的第一表面和导电层的第一表面之间的粘合层。
48. 权利要求46的器件，其中包封层覆盖电路器件的第二表面。
49. 权利要求46的器件，其中导电层的至少两个部分延伸穿过包封层，其中该器件进一步包括第二电路器件，该第二电路器件具有耦连到导电层的所述至少两个部分之一的第一端子和耦连到导电层的所述至少两个部分中的另一个的第二端子。
50. 权利要求49的器件，其中第二电路器件选自由无源器件、光学器件、有源器件、半导体器件、天线和微机电系统(MEMS)器件组成的组。
51. 权利要求46的器件，其中导电层包括引线框。
52. 权利要求46的器件，其中导电层包括至少一个开口，该开口露出电路器件的第一表面的至少一部分。
53. 权利要求46的器件，其中包封层包括导电材料。
54. 权利要求46的器件，其中包封层包括覆盖电路器件的第二表面的导电部分。
55. 权利要求46的器件，其中进一步包括具有第一端子和第二端子的第二电路器件，其中第一端子耦连到导电层的第一物理分离部分，第二端子耦连到导电层的第二物理分离部分。
56. 权利要求55的器件，其中包封层覆盖第二电路器件。
57. 权利要求46的器件，其中导电层包括彼此电隔离的至少两个部分。
58. 权利要求57的器件，其中该至少两个部分之一包括第一电压参考平面。
59. 权利要求58的器件，其中该至少两个部分中的另一个包括第二电压参考平面。
60. 权利要求59的器件，其中进一步包括第二电路器件，该第二电路器件具有耦连到第一电压参考平面的第一端子和耦连到第二电压参考平面的第二端子。
61. 权利要求46的器件，其中进一步包括覆盖导电层的第二表面的互连层。
62. 权利要求61的器件，其中互连层包括多个互连级。
63. 权利要求61的器件，进一步包括覆盖互连层的柔顺层。
64. 权利要求63的器件，其中柔顺层包括耦连到互连层的多个导电通路。
65. 权利要求64的器件，其中进一步包括耦连到导电通路的多个导电球。
66. 权利要求61的器件，其中互连层包括与包封层相同的材料。
67. 权利要求66的器件，其中该相同的材料是选自由液晶聚合物和PPS构成的组的材料。
68. 权利要求46的器件，其中进一步包括覆盖导电层的第一表面的多个电路器件，每个电路器件都具有包括有源电路的第一表面和与第一表面相反的第二表面，其中每个电路器件的第一表面处在每个电路器件的第二表面和导电层的第一表面之间。
69. 权利要求68的器件，其中包封层覆盖所述多个电路器件的第二表面的至少一部分。
70. 权利要求69的器件，其中包封层包括导电材料。
71. 权利要求46的器件，其中导电层包括多个互连层。
72. 权利要求46的器件，其中导电层包括电压参考平面。
73. 权利要求72的器件，其中参考电压平面包括接地平面。
74. 至少具有部分封装的器件，包括：
具有第一表面和与第一表面相反的第二表面的导电层；
覆盖且物理接触导电层的第一表面的粘合层；
覆盖粘合层的电路器件，该电路器件具有第一表面和与第一表面相反的第二表面，其中第一表面包括有源电路且与粘合层物理接触；包封层覆盖导电层的第一表面。
75. 权利要求74的器件，其中包封层覆盖电路器件的第二表面。
76. 权利要求74的器件，其中导电层包括至少一个开口，该开口暴露电路器件的第一表面的至少一部分。
77. 权利要求74的器件，其中包封层包括导电材料。
78. 权利要求74的器件，其中包封层包括覆盖第二器件的第二表面的导电部分。
79. 权利要求74的器件，其中进一步包括具有第一端子和第二端子的第二电路器件，其中第一端子耦连到导电层的第一物理分离部分，第二端子耦连到导电层的第二物理分离部分。
80. 权利要求79的器件，其中包封层覆盖第二电路器件。
81. 权利要求74的器件，其中导电层包括接地参考平面。
82. 一种用于形成至少具有部分封装的器件的方法，包括：
提供具有第一表面和与第一表面相反的第二表面的导电层；
在导电层上定位电路器件，该电路器件具有第一表面和与第一表面相反的第二表面，其中第一表面包括有源电路，电路器件的第一表面处于电路器件的第二表面和导电层的第一表面之间；和
形成覆盖导电层的第一表面的包封层。
83. 权利要求82的方法，其中定位电路器件的步骤包括将电路器件的第一表面粘接到导电层上。
84. 权利要求82的方法，其中形成包封层的步骤包括形成覆盖电路器件的包封层。
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US8072062B2 (en) 2011-12-06
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