JP4791244B2 - 電子部品内蔵基板及びその製造方法 - Google Patents
電子部品内蔵基板及びその製造方法 Download PDFInfo
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Description
図2〜図4は本発明の第1実施形態の電子部品内蔵基板の製造方法を示す断面図、図5は同じく電子部品内蔵基板を示す断面図である。本発明の第1実施形態の電子部品内蔵基板の製造方法は、まず、図2(a)に示すような配線基板からなる被実装体5を用意する。被実装体5では、ガラスエポキシ樹脂などの絶縁性のコア基板10にそれを貫通するスルーホール10xが設けられており、スルーホール10xの内面にはスルーホールめっき層11が形成されている。スルーホール10xの内部の孔には樹脂9が充填されている。さらに、コア基板10の両面側にはスルーホールめっき層11を介して相互接続された第1配線層12がそれぞれ形成されている。
図9は本発明の第2実施形態の電子部品内蔵基板の製造方法を示す断面図、図10は同じく電子部品内蔵基板を示す断面図である。第2実施形態が第1実施形態と異なる点は、導電性ボールが配置される第1ビアホールの底部の接続部の材料が異なることにあるので、第1実施形態と同一工程については詳しい説明を省略する。
Claims (8)
- 第1配線層を備えた被実装体と、
前記被実装体の上に実装された電子部品と、
前記電子部品を埋設する絶縁層と、
前記絶縁層を貫通して配置され、前記第1配線層に電気的に接続された導電性ボールと、
前記絶縁層の上に形成され、前記導電性ボールに電気的に接続された第2配線層とを有し、
前記導電性ボールの下部は、はんだ層を介して前記第1配線層に電気的に接続され、前記導電性ボールの上部は、前記第2配線層に直接電気的に接続されていることを特徴とする電子部品内蔵基板。 - 前記導電性ボールは、銅ボールとそれを被覆する被覆部とにより構成され、前記導電性ボールの上部の前記被覆部が部分的に除去されており、前記銅ボールに前記第2配線層が接続されていることを特徴とする請求項1に記載の電子部品内蔵基板。
- 前記導電性ボールの中心部に樹脂体が充填されていることを特徴とする請求項1又は2に記載の電子部品内蔵基板。
- 前記絶縁層及び前記第2配線層の上に形成された上側絶縁層と、
前記上側絶縁層に形成され、前記導電性ボールに対応する前記第2配線層の部分に到達する上側ビアホールと、
前記上側絶縁層の上に形成され、前記上側ビアホールを介して前記第2配線層に接続された第3配線層とをさらに有することを特徴とする請求項1乃至3のいずれか一項に記載の電子部品内蔵基板。 - 第1配線層を備えた被実装体の上に電子部品を実装する工程と、
前記電子部品を埋設する絶縁層を形成する工程と、
前記絶縁層に、前記第1配線層に到達するビアホールを形成する工程と、
導電性ボールの上部側が前記絶縁層の上面から突き出る突出部となる状態で、はんだ層を介して前記第1配線層に接続される前記導電性ボールを前記ビアホールに配置する工程と、
前記導電性ボールの前記突出部を埋め込む被覆絶縁層を形成する工程と、
前記導電性ボールの上部が露出するまで前記被覆絶縁層を研磨する工程と、
前記導電性ボールに接続される第2配線層を前記絶縁層の上方に形成する工程とを有することを特徴とする電子部品内蔵基板の製造方法。 - 前記導電性ボールは、銅ボールとそれを被覆する、最外面が金層又ははんだ層からなる被覆部とにより構成されており、
前記被覆絶縁層を研磨する工程において、前記導電性ボールの上部の前記被覆部を同時に研磨して除去することを特徴とする請求項5に記載の電子部品内蔵基板の製造方法。 - 前記ビアホールを形成する工程の後に、前記ビアホール内の前記第1配線層の部分に、最上層が前記はんだ層から形成される接続部を形成する工程をさらに有し、
前記導電性ボールを配置する工程において、前記接続部の前記はんだ層をリフローさせて前記導電性ボールを前記接続部に接合することを特徴とする請求項5又は6に記載の電子部品内蔵基板の製造方法。 - 前記ビアホールを形成する工程の後に、前記ビアホール内の前記第1配線層の部分に最上層が金層から形成される接続部を形成する工程をさらに有し、
前記導電性ボールは、銅ボールとそれを被覆する、最外面が前記はんだ層からなる被覆部とによって構成されており、
前記導電性ボールを配置する工程において、前記導電性ボールの前記はんだ層をリフローさせて前記接続部に接合することを特徴とする請求項5又は6に記載の電子部品内蔵基板の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006132497A JP4791244B2 (ja) | 2006-05-11 | 2006-05-11 | 電子部品内蔵基板及びその製造方法 |
EP07107196.3A EP1868422B1 (en) | 2006-05-11 | 2007-04-30 | Electronic component built-in substrate and method of manufacturing the same |
US11/797,552 US7678681B2 (en) | 2006-05-11 | 2007-05-04 | Electronic component built-in substrate and method of manufacturing the same |
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JP2006132497A JP4791244B2 (ja) | 2006-05-11 | 2006-05-11 | 電子部品内蔵基板及びその製造方法 |
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Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4489411B2 (ja) * | 2003-01-23 | 2010-06-23 | 新光電気工業株式会社 | 電子部品実装構造の製造方法 |
JP5212118B2 (ja) | 2009-01-05 | 2013-06-19 | 日立金属株式会社 | 半導体装置およびその製造方法 |
KR101101550B1 (ko) * | 2009-09-14 | 2012-01-02 | 삼성전기주식회사 | 솔더 볼 및 반도체 패키지 |
JP5026565B2 (ja) * | 2010-06-29 | 2012-09-12 | 京楽産業.株式会社 | 遊技機、主制御基板、周辺基板、遊技機の認証方法及び認証プログラム |
US9159687B2 (en) * | 2012-07-31 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solder bump for ball grid array |
KR20150004005A (ko) * | 2013-07-02 | 2015-01-12 | 에스케이하이닉스 주식회사 | 스택 패키지 및 이의 제조방법 |
US9859200B2 (en) | 2014-12-29 | 2018-01-02 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof |
CN106356355B (zh) * | 2015-07-15 | 2020-06-26 | 恒劲科技股份有限公司 | 基板结构及其制作方法 |
KR102458034B1 (ko) | 2015-10-16 | 2022-10-25 | 삼성전자주식회사 | 반도체 패키지, 반도체 패키지의 제조방법, 및 반도체 모듈 |
US20200161206A1 (en) * | 2018-11-20 | 2020-05-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor manufacturing process |
US11540396B2 (en) * | 2020-08-28 | 2022-12-27 | Unimicron Technology Corp. | Circuit board structure and manufacturing method thereof |
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US5197185A (en) * | 1991-11-18 | 1993-03-30 | Ag Communication Systems Corporation | Process of forming electrical connections between conductive layers using thermosonic wire bonded bump vias and thick film techniques |
JPH0572177U (ja) * | 1992-03-05 | 1993-09-28 | ティーディーケイ株式会社 | 多層基板による回路モジュール |
JPH0946045A (ja) * | 1995-07-26 | 1997-02-14 | Oki Electric Ind Co Ltd | 多層配線基板の製造方法 |
US5956605A (en) * | 1996-09-20 | 1999-09-21 | Micron Technology, Inc. | Use of nitrides for flip-chip encapsulation |
JP2001077497A (ja) * | 1999-09-01 | 2001-03-23 | Denso Corp | プリント基板及びその製造方法 |
JP2001267715A (ja) * | 2000-03-16 | 2001-09-28 | Sony Corp | 電子回路装置および基板接続用弾性体 |
JP3666576B2 (ja) * | 2000-07-12 | 2005-06-29 | 松下電器産業株式会社 | 多層モジュールおよびその製造方法 |
JP2002111180A (ja) * | 2000-09-28 | 2002-04-12 | Kyocera Corp | 配線基板 |
WO2002058108A2 (en) * | 2000-11-14 | 2002-07-25 | Henkel Loctite Corporation | Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith |
JP2002314245A (ja) | 2001-04-11 | 2002-10-25 | Ngk Insulators Ltd | コア基板の製造方法及びその製造方法により製造されたコア基板、そのコア基板を用いた複層コア基板の製造方法及び多層積層基板の製造方法 |
US7309948B2 (en) * | 2001-12-05 | 2007-12-18 | Fujifilm Corporation | Ultrasonic transducer and method of manufacturing the same |
JP2003273317A (ja) * | 2002-03-19 | 2003-09-26 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP3967989B2 (ja) * | 2002-09-24 | 2007-08-29 | 京セラ株式会社 | 半田バンプ付き配線基板の製造方法 |
US6921975B2 (en) * | 2003-04-18 | 2005-07-26 | Freescale Semiconductor, Inc. | Circuit device with at least partial packaging, exposed active surface and a voltage reference plane |
JP2005005332A (ja) * | 2003-06-09 | 2005-01-06 | Yamanashi Matsushita Electric Works Ltd | 多層プリント配線板及びその製造方法 |
JP2005327984A (ja) | 2004-05-17 | 2005-11-24 | Shinko Electric Ind Co Ltd | 電子部品及び電子部品実装構造の製造方法 |
-
2006
- 2006-05-11 JP JP2006132497A patent/JP4791244B2/ja not_active Expired - Fee Related
-
2007
- 2007-04-30 EP EP07107196.3A patent/EP1868422B1/en not_active Expired - Fee Related
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US20070262452A1 (en) | 2007-11-15 |
EP1868422A3 (en) | 2014-01-08 |
EP1868422B1 (en) | 2016-06-15 |
EP1868422A2 (en) | 2007-12-19 |
US7678681B2 (en) | 2010-03-16 |
JP2007305774A (ja) | 2007-11-22 |
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