CN107619020B - 底部封装体暴露的裸片mems压力传感器集成电路封装体设计 - Google Patents
底部封装体暴露的裸片mems压力传感器集成电路封装体设计 Download PDFInfo
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- CN107619020B CN107619020B CN201710289718.0A CN201710289718A CN107619020B CN 107619020 B CN107619020 B CN 107619020B CN 201710289718 A CN201710289718 A CN 201710289718A CN 107619020 B CN107619020 B CN 107619020B
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- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00777—Preserve existing structures from alteration, e.g. temporary protection during manufacturing
- B81C1/00825—Protect against mechanical threats, e.g. against shocks, or residues
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- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0058—Packages or encapsulation for protecting against damages due to external chemical or mechanical influences, e.g. shocks or vibrations
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- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/01—Microstructural systems or auxiliary parts thereof comprising a micromechanical device connected to control or processing electronics, i.e. Smart-MEMS
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Abstract
一种用模制化合物进行封装的MEMS压力传感器。该MEMS压力传感器的特征是引线框、MEMS半导体裸片、第二半导体裸片、多组多条键合接线、以及模制化合物。该MEMS半导体裸片具有内部空腔、感测部件和孔。该MEMS半导体裸片和这些孔被暴露于环境气氛。期望一种减少因模具飞边和裸片破裂而造成的缺陷的用于形成MEMS压力传感器封装体的方法。制造该MEMS压力传感器封装体包括:将引线框放置在引线框胶带上;将MEMS半导体裸片与该引线框相邻地放置在该引线框胶带上,其中,所述孔面对所述胶带并且被其密封;将第二半导体裸片附接至所述MEMS半导体裸片;附接多组多条键合接线,以在该MEMS半导体裸片、该第二半导体裸片和该引线框之间形成电连接;以及形成模制化合物。
Description
技术领域
本公开总体上涉及MEMS(微机电系统)封装体(其是使用引线框胶带进行制造的,以形成具有将感测部件暴露于外部环境的孔的MEMS封装体),并且更具体地,涉及可以可靠地形成使失效较少并且减少了封装错误机会的这种封装体。
相关技术
随着消费者对较小多功能器件的需求增加,为了保持将多个小MEMS器件制作成封装的方法无缺陷,制造商面临着巨大挑战。存在将机械结构与电子器件组合以形成用作小型传感器和致动器的电响应移动部件的MEMS器件。MEMS封装体必须保护MEMS器件中的电连接件和感测部件二者。例如,当电子器件暴露于诸如外部环境的环境气氛时,制造商寻求有效制作MEMS器件并且将其构建为耐受外部应力的方法。图11和图12示出了两个单独的传统MEMS封装体,这两个MEMS封装体被设计成保护MEMS器件的内部部件和电连接件免受将使用它们的环境的影响;但是,这些现有技术的封装体具有各种不足,从而使它们的制作成本高并且常常导致工作部件的成品率低于预期。
发明内容
通过使用引线框胶带作为底部层并且使用有一面带有与引线框胶带接触的孔的MEMS裸片来制造MEMS压力传感器封装体。将一个或多个附加半导体裸片耦合至引线框胶带并且将整个组件包装在模制化合物内。在一个实施例中,一种用来形成封装体的方法导致具有暴露于环境气氛的引线框和MEMS半导体裸片的MEMS压力传感器封装体。在这个实施例中,将引线框放置在引线框胶带的第一面上。在放置引线框之后,接着将MEMS半导体裸片与引线框相邻地放置在引线框胶带的第一面上。引线框胶带密封并保护最终将敞露于终端产品中的周遭环境的MEMS半导体裸片的任何孔。在放置MEMS半导体裸片之后,使用粘合剂膜将第二半导体裸片附接于所述MEMS半导体裸片。一旦MEMS半导体裸片和第二半导体裸片就位,就添加多条键合接线以连接MEMS器件中的引线框、MEMS半导体裸片和第二半导体裸片。最终,施加模制化合物来部分覆盖引线框和MEMS半导体裸片。另外,施加模制化合物,以完全包封多条键合接线和第二半导体裸片。因此,模制化合物保护灵敏且脆弱的电子连接隔绝外部环境,并且有助于保护感测部件和裸片不受外部应力的影响。
在一个实施例中,MEMS半导体裸片包括内部空腔、内部空腔内的感测部件以及将内部空腔暴露于环境空气的孔。孔被暴露于环境大气,以允许内部空腔以及容纳在其中的感测部件接收环境气氛。
在一个实施例中,将引线框放置在MEMS封装体的与MEMS半导体裸片相对的一侧,并且多条键合接线将引线框连接到第二半导体裸片。
在一个实施例中,将引线框放置在MEMS封装体的与MEMS半导体裸片相对的一侧,并且多条键合接线被省去并且被焊料球或金属柱连接件取代。焊料球或金属柱连接件将引线框连接到第二半导体裸片。
附图说明
为了更好地理解本发明,现在将仅通过非限制性示例并且参照附图描述其实施例。
图1至图6是在根据本文所披露的实施例的MEMS封装体制造工艺的连续步骤处封装的MEMS压力传感器的横截面侧视图。
图7是沿着图8的线7-7截取的根据一个实施例的已完成MEMS压力传感器封装体的横截面侧视图。
图8是图7的已完成MEMS压力传感器封装体的简化顶部平面图,示出了一个实施例中的封装内的键合接线的各种连接。
图9是图7中示出的已完成MEMS压力传感器封装体的替代性实施例的横截面侧视图。
图10是图7中示出的已完成MEMS压力传感器封装体的替代性实施例的横截面侧视图。
图11是现有技术的MEMS封装体的横截面侧视图。
图12是不同现有技术的MEMS封装体的横截面侧视图。
具体实施方式
贯穿本说明书所提到的“一个实施例”或“替代性实施例”是指与该实施例相关联地描述的具体特征、结构或特性被包括在至少一个实施例中。因此,贯穿本说明书,短语“在一个实施例中”或“在替代性实施例中”在各种场合中的出现并不一定都是指相同的实施例。
对序数(如,第一、第二和第三)的使用不一定暗示顺序的排名意义,而是可以仅在动作或结构的多个实例之间进行区分。
本文提供的本披露的小标题以及摘要只是为了方便起见,而并非修改这些实施例的范围或含义。
图1是引线胶带20的侧视图。引线框胶带20具有第一面22。引线框胶带20可以由一层或多层非导电粘合剂和聚酰亚胺材料制成。
在这个实施例中,引线框架胶带20在制造过程中被安置在封装体的底部作为基础层。使用引线框胶带20在制造过程中作为基础层使制作MEMS封装体所需的材料量减少,因为引线框胶带20取代了基底底部层54(图11)或模制化合物底部层80(图12),并且可以在制造过程最后容易地去除引线框胶带20。利用引线框胶带作为底部层允许制造商或制作者制造出较薄的MEMS封装体。
图2是放置在引线框胶带20的第一面22上的引线框24的横截面侧视图。引线框24在其中间具有开口区域26。开口区域26可以具有任何形状和大小,并且开口区域26可以是开口空间、开口区域、开口体积或某种其他形式的开口。引线框24可以由诸如铜、铜合金或半导体行业中已知的某种其他导电材料的导电材料构成。以使得开口区域26位于引线框胶带20的第一面22上方的方式来放置引线框24。
图3是横截面侧视图,示出了引线框24的开口区域26中心的引线框胶带20的第一面22上放置的第一MEMS半导体裸片28。将MEMS半导体裸片28与引线框24相邻地放置。MEMS半导体裸片28可以是MEMS裸片、MEMS压力传感器裸片或半导体行业中已知的某种其他裸片。MEMS半导体裸片28具有内部空腔30、感测部件32和多个孔34。内部空腔30容纳感测部件32。感测部件32可以被配置成用于测量压力。以使得孔34面对引线框胶带20的第一面22的方式来放置MEMS半导体裸片28。引线框胶带20密封孔34。
在这个实施例中,将MEMS半导体裸片28直接放置在引线框胶带20的第一面22上。将MEMS半导体裸片28直接放置在引线框胶带20上使制作引线框24所需的材料量减少,因为引线框胶带20支承的是MEMS半导体裸片28,而非引线框24。另外,以使得孔34面对引线框胶带20的方式将MEMS半导体裸片28直接放置在引线框胶带20上允许胶带既密封又保护内部空腔30。这样做,减少了因后续模制工艺过程中的模具飞边而造成的缺陷。当在MEMS压力传感器封装体的形成过程中模制化合物46(图6)被不正确分布并且覆盖孔34时,导致模具飞边。利用引线框胶带作为底部层来保护和覆盖MEMS半导体裸片的孔降低了模具飞边缺陷的机会。
图4是横截面侧视图,示出了通过粘合剂膜38附接于MEMS半导体裸片28的第二半导体裸片36。第二半导体裸片36可以是诸如ASIC(专用集成电路)或半导体行业中已知的某种其他集成电路的集成电路。粘合剂膜38可以是现有技术中已知类型的标准DAF(粘片膜)或半导体行业中已知的某种其他附接材料。
图5是横截面侧视图,示出了多组多条键合接线40、42、44。第一多条键合接线44具有连接至MEMS半导体裸片28的第一端以及连接至第二半导体裸片36的第二端。第二多条键合接线42具有连接至引线框24的第一端以及连接至至少MEMS半导体裸片28或第二半导体裸片36的第二端。第三多条键合接线40具有连接至引线框24连接的第一端以及连接至MEMS半导体裸片28或第二半导体裸片36(无论哪个都没有与引线框24连接)的第二端。第一多条键合接线40、第二多条键合接线42和第三多条键合接线44可以是标准的铜接线或使用半导体行业中合适的已知标准技术来附接的任何接线键合互连件。
在这个实施例中,使用三组多条键合接线40、42和44。使用这些组多条键合接线40、42、44来替代第一多条键合接线72和第二多条键合接线98(图11和图12)允许从引线框78(图12)中去除延长的指状物82。利用第一、第二和第三多条键合接线允许制造商或制作者来制造较薄的MEMS封装体。
图6是横截面侧视图,示出了被形成为完成压力传感器封装体的模制化合物46。模制化合物46被形成为部分覆盖MEMS半导体裸片28和引线框24,并且完全包封第二半导体裸片36和这些组多条键合接线40、42、44。模制化合物46可以是半导体行业中已知的用于形成MEMS封装体的环氧模制化合物、环氧树脂或塑料标准。
在这个实施例中,可以使用模制机器通过颗粒传递模制或压塑模制来形成模制化合物46。颗粒传递模制是半导体封装行业中使用的当前工艺并且是指材料颗粒被加热并且被用力插入孔中以形成MEMS封装体。将引线框24放置在引线框胶带20上允许进行压塑模制,以用作颗粒传递模制的替代手段。压塑模制是指材料的一部分被加热并且被压入就位以形成MEMS封装体。
图7示出了已完成压力传感器封装体的实施例。从压力传感器封装体去除引线框胶带20,将MEMS半导体裸片28的第一面和引线框24暴露于环境气氛48。第一面可以是MEMS半导体裸片的面、MEMS半导体裸片的一部分或MEMS半导体裸片的某个其他部分。在去除了引线框胶带20之后,MEMS半导体裸片28的孔34被暴露于环境气氛48。孔34将内部空腔30和感测部件32暴露于环境气氛48。
在这个实施例中,如果MEMS封装体将被安装在PCB(印刷电路板)上,则在与MEMS裸片28相邻的PCB中将存在一个或多个开口,用于暴露MEMS器件的孔34,以确保环境气氛48能够进入空腔30。将使用引线24将封装体安装在PCB上,使孔34和引线二者在同一面上,面对PCB。在PCB中设置与孔34对准的一个或多个孔将把它们暴露于环境气氛38。
图8示出了这些组多条键合接线40、42、44的连接。第一多条键合接线44将MEMS半导体裸片28连接到第二半导体裸片36。第二多条键合接线42将引线框24连接到第二半导体裸片36。第三多条键合接线40将引线框24连接到MEMS半导体裸片28。图8示出通过键合接线与MEMS和ASIC裸片36二者连接的引线框24的十条引线。因为在本领域中已知引线框的使用和结构,所以未示出整个引线框。在终端产品中,每条引线彼此电隔离,以承载单独电压。
在一个实施例中,键合接线40从各条引线延伸到MEM裸片28和ASIC裸片36二者,如图8中所示。在另一个实施例中,键合接线40从引线只延伸到ASIC裸片36并且只有延伸到MEMS裸片28的接线是源自ASIC 36。
图9示出已完成压力传感器封装体的替代性实施例。该替代性实施例具有引线框24和多条键合接线50,引线框24被放置在与压力传感器封装体中的MEMS半导体裸片28相对的MEMS封装体的一侧。多条键合接线50将引线框连接到第二半导体裸片36。
在这个实施例中,一种方法用于将引线框24放置在MEMS封装体的与MEMS半导体裸片28相对的一侧。将引线框24放置在引线框胶带20上。一旦放置了引线框24,就将支承材料放置在引线框胶带20上的引线框24的开口区域26中,使其与引线框24相邻。支承材料可以是永久性散热器、可移除材料的临时分隔件或半导体行业已知的某种其他支承材料。
一旦放置了支承材料,就接着将第二半导体裸片36附接于支承材料。可以使用粘合剂膜来附接第二半导体裸片36。粘合剂膜可以是DAF或半导体行业中已知的某种其他附接材料。
在将第二半导体裸片36附接于支承材料之后,在引线框24与第二半导体裸片36之间连接多条键合接线50。多条键合接线50可以由铜、铜合金或半导体行业已知的某种导电材料制成。
接下来,使用粘合剂膜38将MEMS半导体裸片24附接于第二半导体裸片36。当将MEMS半导体裸片24附接于第二半导体裸片36时,必须形成电连接。可以使用金属DAF层、裸片之间的金属柱连接件、多条键合接线、接线键合互连件或半导体行业已知的形成裸片之间的电连接的某种其他技术来形成电连接。MEMS半导体裸片24具有内部空腔30、感测部件32和孔34。以使得在随后模制工艺之后将MEMS半导体裸片28其至少一部分暴露于环境气氛48的方式来放置MEMS半导体裸片28。MEMS半导体裸片28的这一个部分具有多个孔34。在后续模制工艺之后,多个孔34将被暴露于环境气氛48。
然后,将第二引线框胶带放置在MEMS半导体裸片28上。第二引线框胶带可以由一层或多层非导电粘合剂和聚酰亚胺材料制成。第二引线框胶带在后续模制工艺过程中密封并保护孔34和内部空腔30。一旦已经放置了第二引线框胶带,就使用注塑模制工艺在引线框胶带20和第二引线框胶带之间注入模制化合物46。注塑模制是指推动加热后的材料通过小孔,以形成MEMS封装体。
一旦已经形成了模制化合物46,就去除第二引线框胶带20和第二引线框胶带。去除第二引线框胶带20使得将引线框24暴露于环境气氛48。去除第二引线框胶带使得MEMS半导体裸片28的多个孔34暴露于环境气氛48。多个孔34将内部空腔30和感测部件32暴露于环境气氛48。当去除了第二引线框胶带20时,支承材料可以固定不动或者随着第二引线框胶带20一起被去除。
在这个实施例和方法中,通过将引线框24与MEMS半导体裸片28相对布置,如果MEMS压力传感器封装体将被安装于PCB,不再需要PCB封装中有与孔34对应的孔。
在与以上方法类似的方法中,替代地,将第二半导体裸片36直接放置在引线框24的开口区域26中的引线框胶带20上,使其与引线框24相邻。也就是说,将第二半导体裸片36放置在封装体的与MEMS半导体裸片28相对的一侧。因此,去除引线框胶带20使得引线框24和第二半导体裸片36暴露于环境气氛。
在这个实施例和类似方法中,通过将引线框24和第二半导体裸片36与封装体中的MEMS半导体裸片28相对放置并且将第二半导体裸片36与引线框20相邻布置,类似地,如果MEMS压力传感器封装体将被安装于PCB,不再需要PCB封装中有与孔34对应的孔。另外,将第二半导体裸片36与引线框20相邻放置进一步减少制作MEMS封装体所需的模制化合物46,进而允许制造商、制作者或制造者制作出更加薄的MEMS封装体。另外,通过将第二半导体裸片36放置在引线框胶带20上,不再需要散热器或临时支承材料。因此,利用将引线框胶带上的第二半导体裸片放置在封装体的与MES半导体裸片相对的一侧的引线框的开口区域内,允许用更少的材料制作更加薄的MEMS封装体。
图10示出了已完成压力传感器封装体的替代性实施例。该替代性实施例具有引线框24和多个电连接件52,引线框24与压力传感器封装体中的MEMS半导体裸片28相对放置。电连接件52可以是焊料球或金属柱连接件,用于将引线框24连接到第二半导体裸片36。
在这个实施例中,通过将引线框与MEMS半导体裸片28相对放置,如果MEMS压力传感器封装体将被安装于PCB,不再需要PCB封装中有与孔34对应的孔。
图11示出了具有容纳引线框56的基底底部层54的现有技术。通过第一DAF层58将基底底部层54附接于第一半导体裸片60。通过第二DAF层62将第一半导体裸片60附接于MEMS半导体裸片64。MEMS半导体裸片64具有内部空腔66、感测部件68和孔70。MEMS半导体裸片64被暴露于环境气氛48。孔70被暴露于环境气氛48。孔70将内部空腔66和感测部件68暴露于环境气氛48。第一和第二多条键合接线72将引线框56连接到第一半导体裸片60并且将第一半导体裸片60连接到MEMS半导体裸片64。形成模制化合物74,模制化合物74部分覆盖引线框56和MEMS半导体裸片64并且包封第一和第二多条键合接线72和第一半导体裸片60。
在该现有技术中,第二半导体裸片64以及孔70存在模具飞边的风险,因为当施加模制化合物74时没有保护或覆盖孔70。当模制化合物46、74、100被不正确分布并且覆盖孔34、70、96时,导致出现模具飞边。该不正确分布导致MEMS压力传感器或MEMS装置不可用。模具飞边的成因包括使得在模制工艺中夹持压力不足的不均匀裸片高度和未优化的压料塞填料压力。另外,在该现有技术中,MEMS半导体裸片64存在裸片破裂的风险,因为是通过模制化合物机器将模制化合物74推入就位的。模制化合物机器对MEMS半导体裸片64施加直接压力,从而使裸片破裂的风险更高。
图12示出具有引线框胶带76的现有技术。将引线框胶带76附接于引线框78和模制化合物底部层80。引线框78具有延长的指状物82。通过第一DAF层84将延长的指状物82附接于第一半导体裸片86。将第一半导体裸片86附接于延长的指状物82在半导体行业中被称为COL(芯片上引线)设计。通过第二DAF层88将第一半导体裸片86附接于MEMS半导体裸片90。MEMS半导体裸片90具有内部空腔92、感测部件94和孔96。MEMS半导体裸片90被暴露于环境气氛48。孔96被暴露于环境气氛48。孔96将内部空腔92和感测部件94暴露于环境气氛48。第一和第二多条键合接线98将引线框78连接到第一半导体裸片86并且将第一半导体裸片86连接到MEMS半导体裸片90。形成部分覆盖引线框78和MEMS半导体裸片90的模制化合物100,并且形成完全包封第一和第二多条键合接线98和第一半导体裸片86的模制化合物100。
在该现有技术中,MEMS半导体裸片90和孔96处于模具飞边的风险,这是由于当应用模制化合物100时没有保护或覆盖孔96。另外,MEMS半导体裸片90存在裸片破裂的风险,因为是通过模制化合物机器将模制化合物100推入就位的。
相比于现有技术,所声明的方法和设备减少了模具飞边的机会。在该现有技术中,例如,如果模制化合物74、100被不正确分布,则模制化合物74、100将有可能覆盖孔70、96。通过以使得孔34面对引线框胶带20的方式来放置MEMS半导体裸片28,即使模制化合物46不正确分布,模制化合物46能够覆盖孔34的可能性也因引线框胶带20覆盖、保护和密封孔隔绝模制化合物46而降低。
所声明的方法和设备减少了裸片破裂的机会。裸片破裂的成因包括高夹持压力和裸片高度与模具帽盖(高裸片高度或浅模具帽盖)之间的不匹配。以使得模制化合物机器向模制化合物46而非MEMS半导体裸片28施加直接压力的方式放置MEMS半导体裸片28减少了裸片破裂的机会。
所声明的方法和设备允许进行颗粒传递模制和压塑模制。颗粒传递模制是用于制造MEMS封装体的半导体行业标准,而压塑模制将是通过在MESM封装体制造过程中将MEMS半导体裸片28放置在引线框胶带20上的半导体行业可利用的另一个工艺。颗粒传递模制是材料的一部分被加热并且被用力压入孔中,以形成MEMS封装体。压塑模制是指材料的一部分被加热并且被压入就位以形成MEMS封装体。另外,在替代性方法中,可以利用第二引线框胶带,从而允许使用注塑模制工艺,以进一步减少模具飞边和裸片破裂的机会。
相比于现有技术,所声明的方法和设备提供了较薄的封装体外形。对于待制造的现有技术,需要基底底部层54(图11)或模制化合物底部层80(图12)。在这种新设计中,可以通过使用引线框胶带20作为底部层来制造较薄封装体。通过使用引线框胶带20作为底部层,从制造例如引线框78的裸片焊盘82(图12)、模制化合物底部层82(图12)和基底底部层54(图11)所需的现有技术封装体中去除材料。另外,在现有技术中,需要两个DAF层58、62、84、88来制作封装体。因此,在这种新技术中,通过利用引线框胶带作为底部层,允许去除DAF层中的一个,从而允许更加薄的MEMS封装体。
上述各实施例可以组合以提供进一步的实施例。在本说明书中所提及的和/或在申请资料表中所列出的所有美国专利、美国专利申请出版物、美国专利申请、国外专利、国外专利申请和非专利出版物,(包括但不限于(插入列表)),都以其全文通过引用并入本文。如果有必要,可以对实施例的各方面进行修改,以采用各专利、申请和公开的构思来提供更进一步的实施例。
鉴于以上详细说明,可以对实施例做出这些和其他改变。总之,在以下权利要求书中,所使用的术语不应当被解释为将权利要求书局限于本说明书和权利要求书中所披露的特定实施例,而是应当被解释为包括所有可能的实施例、连同这些权利要求有权获得的等效物的整个范围。因此,权利要求书并不受本披露的限制。
Claims (28)
1.一种用于形成封装体的方法,包括:
将引线框放置在引线框胶带的第一面上;
将MEMS半导体裸片与所述引线框横向相邻地放置在所述引线框胶带的所述第一面上,所述MEMS半导体裸片具有内部空腔,所述MEMS半导体裸片的暴露的外表面被暴露于环境气氛,所述暴露的外表面具有多个孔以及在所述内部空腔内的感测部件,所述多个孔直接面对所述引线框胶带并且将所述MEMS半导体裸片的所述内部空腔直接暴露于所述环境气氛;
将第二半导体裸片附接至所述MEMS半导体裸片;
附接第一多条键合接线,所述第一多条键合接线具有连接至所述MEMS半导体裸片的第一端以及连接至所述第二半导体裸片的第二端;
附接第二多条键合接线,所述第二多条键合接线具有连接至所述引线框的第一端以及连接至所述第二半导体裸片或所述MEMS半导体裸片中的至少一者的第二端;
形成模制化合物,所述模制化合物部分覆盖所述MEMS半导体裸片和所述引线框并且完全包封所述第二半导体裸片以及所述第一和第二多条键合接线,所述模制化合物的第一表面与所述MEMS半导体裸片的所述暴露的外表面齐平并且还与所述引线框的第一表面齐平;以及
去除所述引线框胶带,以将所述引线框、所述MEMS半导体裸片和所述孔暴露于环境气氛。
2.如权利要求1所述的方法,其中,形成部分覆盖所述MEMS半导体裸片和所述引线框并且完全包封所述第二半导体裸片和所述多条键合接线的模制化合物进一步包括:
在形成所述模制化合物的同时,所述引线框胶带覆盖、保护并密封所述MEMS半导体裸片的所述孔和所述内部空腔。
3.如权利要求1所述的方法,进一步包括:
附接第三多条键合接线,所述第三多条键合接线具有连接至所述引线框的第一端以及连接至所述MEMS半导体裸片或所述第二半导体裸片中的另一者的第二端。
4.如权利要求1所述的方法,其中,所述MEMS半导体裸片的所述孔连接到所述MEMS半导体裸片的所述内部空腔。
5.如权利要求1所述的方法,其中,所述引线框具有在所述引线框中间的开口区域。
6.如权利要求5所述的方法,其中,将所述MEMS半导体裸片放置在所述引线框胶带进一步包括:
在所述引线框胶带上将所述MEMS半导体裸片放置在所述引线框的所述开口区域中。
7.如权利要求1所述的方法,其中,将所述第二半导体裸片附接于所述MEMS半导体裸片进一步包括:
使用粘合剂膜将所述第二半导体裸片附接于所述MEMS半导体裸片。
8.如权利要求1所述的方法,其中,去除所述引线框胶带以暴露所述孔进一步包括:
通过所述孔将所述感测部件和所述内部空腔暴露于所述环境气氛。
9.如权利要求1所述的方法,其中,形成部分覆盖所述MEMS半导体裸片和所述引线框并且完全包封所述第二半导体裸片和所述多条键合接线的模制化合物进一步包括:
使用模制机器以通过颗粒传递模制、压塑模制或注塑模制来形成所述模制化合物。
10.一种包含MEMS传感器电路的封装体,包括:
引线框,所述引线框具有在所述引线框中间的开口区域并且暴露于环境气氛;
MEMS半导体裸片,其与所述引线框横向相邻,所述MEMS半导体裸片具有暴露于所述环境气氛的所述MEMS半导体裸片的暴露的外表面,所述暴露的外表面具有多个孔,所述多个孔将所述MEMS半导体裸片的内部空腔直接暴露于所述环境气氛;
第二半导体裸片,其被附接于所述MEMS半导体裸片;
第一多条键合接线,其连接在所述引线框和所述第二半导体裸片之间;
第二多条键合接线,其至少连接在所述引线框与所述MEMS半导体裸片或所述MEMS半导体裸片与所述第二半导体裸片中的一者之间;以及
模制化合物,其部分覆盖所述MEMS半导体裸片和所述引线框并且包封所述第二半导体裸片和所述多条键合接线,所述模制化合物的第一表面与所述MEMS半导体裸片的所述暴露的外表面齐平并且还与所述引线框的第一表面齐平。
11.如权利要求10所述的封装体,进一步包括:
第三多条键合接线,其连接在所述引线框与所述第二半导体裸片或所述MEMS半导体裸片中的另一者之间。
12.如权利要求10所述的封装体,其中,所述MEMS半导体裸片进一步包括:
感测部件,其在所述内部空腔内。
13.如权利要求12所述的封装体,其中,所述感测部件通过所述多个孔暴露于所述环境气氛。
14.如权利要求10所述的封装体,其中,附接于所述MEMS半导体裸片的所述第二半导体裸片进一步包括:
使用粘合剂膜将所述第二半导体裸片附接于所述MEMS半导体裸片。
15.如权利要求10所述的封装体,其中所述MEMS传感器是压力传感器。
16.如权利要求10所述的封装体,其中所述MEMS半导体裸片被放置在所述引线框的所述开口区域中。
17.一种压力传感器封装体,包括:
MEMS半导体裸片具有暴露于环境气氛的所述MEMS半导体裸片的暴露的外表面,所述MEMS半导体裸片的暴露于所述MEMS半导体裸片的所述环境气氛的所述暴露的外表面具有多个孔,所述多个孔将所述MEMS半导体裸片的内部空腔直接暴露于所述环境气氛;
第二半导体裸片,其附接于所述MEMS半导体裸片;
引线框,所述引线框具有在所述引线框中间的开口区域并且暴露于所述环境气氛,所述引线框被放置在所述压力传感器封装体的与所述MEMS半导体裸片相对的一侧上;
电连接件,其将所述引线框连接到所述第二半导体裸片;以及
模制化合物,其部分覆盖所述MEMS半导体裸片和所述引线框并且包封所述第二半导体裸片和所述电连接件,所述模制化合物具有第一表面,所述模制化合物的所述第一表面与所述MEMS半导体裸片的所述暴露的外表面齐平。
18.如权利要求17所述的压力传感器封装体,其中,所述电连接件选自包括以下的组:
多个键合接线、焊料球连接件或金属柱连接件。
19.如权利要求17所述的压力传感器封装体,其中,所述MEMS半导体裸片进一步包括:
感测部件。
20.如权利要求19所述的压力传感器封装体,其中,所述内部空腔容纳所述感测部件。
21.如权利要求17所述的压力传感器封装体,其中,附接于所述MEMS半导体裸片的所述第二半导体裸片进一步包括:
使用粘合剂膜将所述第二半导体裸片附接于所述MEMS半导体裸片。
22.如权利要求17所述的压力传感器封装体,其中,附接于所述MEMS半导体裸片的所述第二半导体裸片进一步包括:
在所述第二半导体裸片与所述MEMS半导体裸片之间形成电连接。
23.一种包含MEMS传感器电路的封装体,包括:
引线框,所述引线框具有在所述引线框中间的开口区域并且暴露于环境气氛;
MEMS半导体裸片,其具有暴露于所述环境气氛的所述MEMS半导体裸片的暴露的外表面,所述暴露的外表面具有多个孔,所述多个孔将所述MEMS半导体裸片的内部空腔直接暴露于所述环境气氛;
第二半导体裸片,其被附接于所述MEMS半导体裸片;
第一电连接件,其连接在所述引线框和所述第二半导体裸片之间;以及
模制化合物,其部分覆盖所述MEMS半导体裸片和所述引线框并且包封所述第二半导体裸片和所述第一电连接件,所述模制化合物具有第一表面,所述MEMS半导体裸片的所述暴露的外表面暴露于所述模制化合物的所述第一表面上。
24.根据权利要求23所述的封装体,其中所述MEMS半导体裸片与所述引线框相邻。
25.根据权利要求23所述的封装体,所述引线框被定位在所述封装体的与所述MEMS半导体裸片相同的一侧。
26.根据权利要求23所述的封装体,所述引线框被定位在所述封装体的与所述MEMS半导体裸片相对的一侧。
27.根据权利要求23所述的封装体,其中所述第一电连接件选自包括以下的组:
多个键合接线、焊料球连接件或金属柱连接件。
28.根据权利要求23所述的封装体,其中所述MEMS传感器是压力传感器。
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