CN105374763A - 用于封装应力敏感器件的硅保护物 - Google Patents

用于封装应力敏感器件的硅保护物 Download PDF

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Publication number
CN105374763A
CN105374763A CN201510404256.3A CN201510404256A CN105374763A CN 105374763 A CN105374763 A CN 105374763A CN 201510404256 A CN201510404256 A CN 201510404256A CN 105374763 A CN105374763 A CN 105374763A
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China
Prior art keywords
integrated circuit
components
lead frame
surface mount
frame assembly
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CN201510404256.3A
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English (en)
Inventor
M·程
K·王
T·田
M·伊亚施
T·范
B·拉什
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Maxim Integrated Products Inc
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Maxim Integrated Products Inc
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Publication of CN105374763A publication Critical patent/CN105374763A/zh
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Abstract

一种表面安装半导体封装、半导体器件以及用于上述制造表面安装半导体封装和电子器件的方法，所述半导体封装包括引线框架组件；集成电路器件，设置在引线框架组件上；硅保护物，设置在集成电路器件上，其中硅保护物配置为减轻施加到集成电路器件的封装应力；以及模塑层，包封集成电路器件、硅保护物以及至少一部分引线框架组件。

Description

用于封装应力敏感器件的硅保护物
背景技术
这些年来，封装技术进化成开发更小、更便宜、更可靠以及更环境友好封装。例如，开发出芯片尺寸封装技术，使得直接表面可安装的封装具有不大于集成电路芯片面积1.2倍的表面面积。晶片级封装(WPL)是一种芯片尺寸封装技术包括各种技术使得集成电路芯片在分割前以晶片级封装。晶片级封装将晶片制造工艺延伸到包括器件互连和器件保护工艺。因而晶片级封装允许晶片级的晶片制造、封装、测试以及老化工艺(burn-in)集成地制造工艺。
半导体器件制造中使用的一些制造工艺使用显微光刻法在圆形晶片上图案化集成电路，圆形晶片由半导体形成，例如硅、砷化镓等。典型地，将图案化晶片分割成单个集成电路芯片或管芯以将集成电路彼此分离。使用各种封装技术组装或封装单个集成电路芯片以形成半导体器件，半导体器件可以安装在印刷电路板上。
发明内容
描述了一种表面安装半导体封装、电子器件以及用于制造表面安装半导体封装和电子器件的方法，该表面安装半导体封装包括引线框架组件；设置在引线框架组件上的集成电路器件；设置在集成电路器件上的硅保护物(siliconshield)，其中硅保护物配置为减轻施加到集成电路器件的封装应力；以及包封集成电路器件、硅保护物以及至少一部分引线框架组件的模塑层，保护物。在实施例中，使用根据本发明示例技术的电子器件包括印刷电路板和表面安装半导体封装。在实施方式中，使用根据本发明示例技术的用于制造表面安装半导体封装和/或半导体器件的一种工艺包括在引线框架组件上放置集成电路器件；在集成电路器件上放置硅保护物；以及形成包封集成电路器件、硅保护物以及至少一部分引线框架组件的模塑层保护物。
本发明内容以一种简化的形式引入概念的选择，其将在下文的具体实施方式中进一步描述。本发明内容并不旨在确定权利要求所要求保护主题的关键特征或必要特征，也不旨在用于帮助决定权利要求所要求保护主题的范围。
附图说明
详细说明将参照附图描述。说明书和附图中不同示例中的相同的附图标记代表相似或相同的部件。
图1A是横截面侧视图，示出了根据本发明的示例实施例的包括设置在集成电路管芯上的硅保护物的一种表面安装半导体封装的实施例保护物。
图1B是局部俯视图，示出了根据本发明的示例实施例的包括设置在集成电路管芯上的硅保护物的一种表面安装半导体封装的实施例保护物。
图2示出了一种用于制造表面安装半导体封装示例工艺的流程图，表面安装半导体封装包括设置在集成电路管芯上的硅保护物，例如如图1A和1B所示的表面安装半导体封装。
具体实施方式
概述
半导体封装促进比使用许多其他封装技术制造的器件更低成本、具有更小尺寸以及提供更低寄生效应的半导体器件的生产。但是，在应力敏感器件中，封装应力能够影响温度系数(TC)与热滞后(TH)性能。精确测量器件，例如有源管芯，在制造期间对应力更敏感并且在封装组件之后和在可靠性测试之后要求最小的信号漂移，例如参考电压、DAC与ADC测试。
因此，描述了一种表面安装半导体封装、电子器件以及用于制造表面安装半导体封装和电子器件的方法，其包括引线框架组件；设置在引线框架组件上的集成电路器件；设置在集成电路器件上的硅保护物，其中硅保护物配置为减轻施加到集成电路器件的封装应力；以及包封集成电路器件、硅保护物以及至少一部分引线框架组件的模塑层保护物。在实施例中，使用根据本发明示例技术的电子器件包括印刷电路板和表面安装半导体封装。在实施例中，使用根据本发明示例技术的用于制造表面安装半导体封装和/或半导体器件的一种工艺包括在引线框架组件上放置集成电路器件；在该集成电路器件上放置硅保护物；以及形成包封集成电路器件、硅保护物以及至少一部分引线框架组件的模塑层保护物。
这里公开的表面安装半导体封装通过在集成电路器件和/或应力敏感器件上放置硅保护物减轻来自封装组件制造和可靠性测试的应力效应，其中硅保护物提供额外的保护层。
示例实施例
图1A和1B示出了根据本发明的示例实施例的一种表面安装半导体封装100和半导体器件保护物。半导体封装100包括半导体器件，半导体器件被配置为封装和安装到电子器件，例如印刷电路板114，以形成另一个电子器件。半导体封装的一些例子可以包括小外形晶体管、精确测量器件、或者其他敏感集成电路器件。
如图1A和1B所示，表面安装半导体封装100可以包括引线框架组件102。在实施例中，引线框架组件102可以包括引线框架，其进一步包括金属结构，在表面安装半导体封装100内金属结构配置为从集成电路器件104输送电子信号到外部器件(例如，印刷电路板114)。在一些示例中，引线框架可以通过从铜或铜合金平板移除材料制造。一些用于制造引线框架的工艺可以包括蚀刻(适用于少量引线框架制造)和/或冲压(适用于大量引线框架制造)。在实施例中，引线框架组件102可以包括至少一个引线框架接触垫116和/或引脚，其可以包括引线框架上的部分引线，引线框架被配置为提供到外部器件例如印刷电路板114的电接触和/或电信号。在其他实施例中，引线可以电耦合至引线框架接触垫116，并且引线框架接触垫116可以形成为与引线框架组件102分离。在这些实施例中，引线框架接触垫116可以包括设置在表面安装半导体封装100底部的金属和/或导电接触垫。
如图1A和1B所示，表面安装半导体封装100可以包括设置在引线框架组件102上的集成电路器件104。在实施例中，集成电路器件104可以包括至少一个集成电路(例如集成电路管芯)，其已自加工过的半导体晶片的一部分(未显示)形成和/或作为其一部分形成。集成电路器件104可以包括数字集成电路、模拟集成电路、混合信号电路等。在一个或多个实施例中，集成电路器件104可以包括数字逻辑器件、模拟器件(例如放大器等)、以及它们的组合等。
如上所述，集成电路器件104可以使用各种制造技术制造。例如，集成电路器件104可以通过互补金属氧化物半导体(CMOS)工艺、双极半导体工艺等制造。集成电路器件104可以包括形成在其中的电互连(例如集成电路、再布线层(redistributionlayer)、通孔、接触垫等)。在实施例中，集成电路器件104可以包括有源管芯(例如处理器)和/或无源管芯(例如电容、晶体管等)。另外，集成电路器件104可以包括电互连(例如接触垫、金属垫，比如铜和/或铝、凸点下金属化层(UBM，under-ballmetallization)等)，电互连配置为提供集成电路器件104与外部组件(例如印刷电路板)之间的电连接(通过再布线层、通孔、焊料凸块、和/或其他电互连)。集成电路器件104可以配置为使用表面安装技术，例如拾取和放置(pick-and-place)技术，耦合至引线框架组件102。
在实施例中，集成电路器件104可以物理和/或电耦合至引线框架组件102。在一个实施例中，集成电路器件104可以使用管芯连接(dieattach)118耦合至引线框架组件102。管芯连接118可以包括用于将集成电路器件104耦合至引线框架组件102的材料。管芯连接118一些例子可以包括环氧树脂管芯连接、共晶管芯连接、和/或焊料连接。在一个具体的实施例中，集成电路器件104可以使用至少一个引线接合(wirebond)110电连接至引线框架组件102。引线接合可以包括集成电路器件104与引线框架和/或其他封装之间的互连。引线接合材料的一些例子可以包括金、银、铝、和/或铜。在实施例中，引线接合的直径可以介于约15μm到约几百μm之间(例如200μm)。在另一个实施例中，表面安装半导体封装100可以包括具有倒装芯片配置的集成电路器件104。在该实施例中，集成电路器件104可以使用至少一个焊料凸块(未示出)机械连接与电连接到引线框架组件102。焊料凸块可以形成在集成电路器件104的表面。在实施例中，焊料凸块可以包括适于焊接的材料，例如无铅金属，比如锡-银-铜(Sn-Ag-Cu)合金(即SAC)，锡-银(Sn-Ag)合金，锡-铜(Sn-Cu)合金等。在一个具体的实施例中，锡铅(PbSn)材料可以用作焊料凸块。在使用至少一个焊料凸块的实施例中，焊料凸块用作管芯连接118。
如图1A和1B所示，表面安装半导体封装100包括连接至集成电路器件104的硅保护物106。硅保护物106可以连接至集成电路器件104的远离管芯连接118和引线框架组件102的侧面上。在实施例中，硅保护物106可以包括设置在集成电路器件104上的硅层或其他耐用且牺牲性材料，硅保护物106配置为阻止施加到敏感集成电路器件104的应力。硅保护物106可以具有各种尺寸。例如，硅保护物106可以具有比集成电路器件104的相应侧面(例如配置为临近硅保护物106的侧面)上的表面面积小的表面面积。进一步，硅保护物106可以具有各种厚度。在一个具体实施例中，硅保护物106可以具有大约5mm的厚度。这里可以使用其他的硅保护物106尺寸(例如0.5mm×1.0mm，0.5mm×0.5mm等)和厚度(例如0.75mm、0.25mm、0.1mm等)。当制造表面安装半导体封装100时，表面安装半导体封装100和集成电路器件104经受应力。增加硅保护物106可以保护集成电路器件104免受制造步骤损伤。在一个实施例中，可以使用管芯粘接工艺利用粘接层108将硅保护物106放置在集成电路器件104上。粘接层108的一些例子可以包括胶、薄膜、环氧树脂、共晶连接或适合于将硅保护物106粘结到集成电路器件104的其他粘结剂。例如，硅保护物106可以使用环氧基粘结层108连接至集成电路器件104。
表面安装半导体封装100可以包括模塑层112，其包封集成电路器件104、引线接合110、至少一部分引线框架组件102、以及硅保护物106。如图1A和1B所示，模塑层112为集成电路器件104、引线框架组件102、引线接合110以及硅保护物106提供支撑和/或电绝缘。模塑层112可以使用各种工艺形成，例如注射成型和/或传递成型。模塑层112可以包括一种材料，该材料配置为兼具高物理强度与低应力及吸湿性，例如硅树脂和/或环氧树脂。在一个实施例中，模塑层112包括聚合物材料；例如环氧树脂，设置在表面安装半导体封装100上。在其他实施例中，模塑层112可以包括其他聚合物和支撑材料。
图1A示出了一种典型的与印刷电路版114连接的表面安装半导体封装100。该视图示出了表面安装半导体封装100的概略截面图。在该视图中，表面安装半导体封装100可以连接至印刷电路版114以形成半导体器件。图1B示出了表面安装半导体封装100的俯视图，显示了硅保护物106放置在集成电路器件104的远离引线框架组件102的一个侧面上。在该实施例中，集成电路器件104显示为使用多个引线接合110耦合至引线框架组件102。
示例工艺流程
图2示出了一种示例工艺流程200，其采用多种技术制造半导体器件，例如图1A和1B所示的表面安装半导体封装100和半导体器件。
在所示的工艺流程200中，放置集成电路器件到引线框架组件(块202)上。在实施例中，放置集成电路器件104到引线框架组件102上可以包括使用自动表面安装技术系统(例如拾取和放置技术)用于放置步骤。在一些实施例中，放置集成电路器件104到引线框架组件102上可以包括使用管芯连接118，其配置为将聚合物粘接到金属上。在一些实施例中，放置集成电路器件104到引线框架组件102上可以进一步包括管芯连接技术，例如环氧树脂连接和/或共晶管芯连接技术。在一个具体实施例中，适合的管芯连接118包括环氧树脂。在其他实施例中，放置集成电路器件104到引线框架组件102上可以包括使用焊料连接放置倒装型集成电路器件104。在实施例中，放置集成电路器件104到引线框架组件102上可以包括放置集成电路器件104到引线框架组件102的中心部分上。在其他实施例中，放置集成电路器件104可以包括放置集成电路器件104到引线框架组件102的非中心部分上。
接下来，放置硅保护物到集成电路器件上(块204)。在一些实施例中，放置硅保护物106包括放置预形成的硅保护物106，其配置为降低集成电路器件104上的制造应力。在这些实施例中，硅保护物通过单一化硅晶片为适合覆盖集成电路器件104的尺寸而形成。每个硅保护物106可以使用各种技术放置在集成电路器件104上，例如拾取和放置技术和粘接层118。在实施例中，硅保护物106可以相对于集成电路器件104的表面具有相同或者不同的尺寸并且可以放置在集成电路器件104上的不同位置(例如中心、偏离中心等)。在一个具体示例中，放置硅保护物106包括放置具有比集成电路器件104更小表面积的硅保护物106到集成电路器件104的远离管芯连接118与引线框架组件102的侧面的中心上。
模塑层形成为包封表面安装半导体封装的至少一部分(块206)。在实施例中，形成模塑层112包括在形成器件互连以后在集成电路器件104、硅保护物106以及引线框架组件102的表面上形成模塑层112，以提供对表面安装半导体封装100内的集成电路器件104的支撑和隔离。例如，形成模塑层112可以包括在集成电路器件104和至少一部分引线框架组件102上及周围形成环氧树脂包封结构，其中硅保护物连接至集成电路器件104。在一些实施例中，形成模塑层112可以包括使用模塑工艺形成聚合物和/或环氧树脂材料，例如注射成型、传递成型、和/或压模。注射成型可以包括将模塑材料注入模具，其包括表面安装半导体封装100。传递成型可以包括工艺，其中测量模塑材料的数量以及将模塑材料嵌入模具空腔，其包括表面安装半导体封装100。在一些实施例中，沉积多个聚合物层(例如环氧树脂等)以形成模塑层112。在一个具体实施例中，形成模塑层112包括使用传递成型形成环氧模塑层112。在这个具体实施例中，引线框架组件102和集成电路器件104放置在模具上并且关闭模具。环氧树脂(例如模塑层112)缓慢地转移进模具中使得引线接合110不弯曲、避免空洞、以及缓和表面安装半导体封装100上的应力。
在模塑工艺与形成模塑层112以后，表面安装半导体封装100可以进一步被加工和/或连接至其他电子器件，例如印刷电路版114，以形成其他电子器件。
结论
尽管使用具体的结构特征和/或工艺操作的语言描述主题，但是可以理解权利要求书所限定的主题不必限定于以上所描述的具体特征或行为。相反，以上描述的具体特征和行为用于作为权利要求书实施的示例形式而公开。

Claims (20)

1.一种表面安装半导体封装，包含：
引线框架组件；
集成电路器件，设置在所述引线框架组件上；
硅保护物，设置在所述集成电路器件上，其中所述硅保护物配置为减轻施加到所述集成电路器件的封装应力；以及
模塑层，包封所述集成电路器件、所述硅保护物以及至少一部分所述引线框架组件。
2.如权利要求1所述的表面安装半导体封装，其中所述引线框架组件包括铜。
3.如权利要求1所述的表面安装半导体封装，其中所述集成电路器件包括小外形晶体管。
4.如权利要求1所述的表面安装半导体封装，其中所述集成电路器件包括倒装管芯。
5.如权利要求1所述的表面安装半导体封装，其中所述集成电路器件包括有源管芯。
6.如权利要求1所述的表面安装半导体封装，其中所述集成电路器件包括无源器件。
7.如权利要求1所述的表面安装半导体封装，其中所述硅保护物包括厚度为约5mm的硅。
8.如权利要求1所述的表面安装半导体封装，其中所述模塑层包括环氧树脂。
9.如权利要求1所述的表面安装半导体封装，进一步包括：
至少一个引线接合，其提供所述引线框架组件与所述集成电路器件之间的电通信。
10.如权利要求9所述的表面安装半导体封装，其中所述至少一个引线接合包括金、铝、银或铜中的至少一种。
11.一种电子器件，包含：
印刷电路板；以及
表面安装半导体封装，其连接至所述印刷电路板，其中所述表面安装半导体封装包括
引线框架组件；
集成电路器件，设置在所述引线框架组件上；
硅保护物，设置在所述集成电路器件上，其中所述硅保护物配置为减轻施加到所述集成电路器件的封装应力；以及
模塑层，包封所述集成电路器件、所述硅保护物以及至少一部分所述引线框架组件。
12.如权利要求11所述的电子器件，其中所述引线框架组件包括铜。
13.如权利要求11所述的电子器件，其中所述集成电路器件包括小外形晶体管。
14.如权利要求11所述的电子器件，其中所述集成电路器件包括倒装管芯。
15.如权利要求11所述的电子器件，其中所述集成电路器件包括有源管芯。
16.如权利要求11所述的电子器件，其中所述集成电路器件包括无源器件。
17.如权利要求11所述的电子器件，其中所述硅保护物包括厚度为约5mm的硅。
18.如权利要求11所述的电子器件，其中所述模塑层包括环氧树脂。
19.如权利要求11所述的电子器件，进一步包括：
至少一个引线接合，其提供所述引线框架组件与所述集成电路器件之间的电通信。
20.一种工艺，包括：
将集成电路器件放置在引线框架组件上；
将硅保护物放置在所述集成电路器件上；以及
形成模塑层，包封所述集成电路器件、所述硅保护物以及至少一部分所述引线框架组件。
CN201510404256.3A 2014-06-13 2015-06-12 用于封装应力敏感器件的硅保护物 Pending CN105374763A (zh)

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