CN109698177B - 半导体装置封装及其制造方法 - Google Patents
半导体装置封装及其制造方法 Download PDFInfo
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- CN109698177B CN109698177B CN201811201403.7A CN201811201403A CN109698177B CN 109698177 B CN109698177 B CN 109698177B CN 201811201403 A CN201811201403 A CN 201811201403A CN 109698177 B CN109698177 B CN 109698177B
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Abstract
一种半导体装置封装包含金属载体、无源装置、导电粘合材料、电介质层和导电通孔。所述金属载体具有第一导电垫和与所述第一导电垫隔开的第二导电垫。所述第一导电垫和所述第二导电垫在其间限定空间。所述无源装置安置于第一导电垫和所述第二导电垫的顶部表面上。所述导电粘合材料将所述无源装置的第一导电触点和第二导电触点分别电连接到所述第一导电垫和所述第二导电垫。所述电介质层覆盖所述金属载体和所述无源装置,并暴露所述第一导电垫和所述第二导电垫的底部表面。所述导电通孔在所述电介质层内延伸,且电连接到所述第一导电垫和/或所述第二导电垫。
Description
技术领域
本发明涉及一种半导体装置封装及其制造方法,且涉及一种包含功率裸片的半导体封装装置及其制造方法。
背景技术
在半导体装置封装(例如封装系统,SIP)中,使用模制化合物来保护有源或无源装置,但模制化合物会妨碍所述有源或无源装置的散热。为了增强有源或无源装置的散热,可将所述有源或无源装置嵌入于具有更高效散热设计的载体(引线框或衬底)中。
为了形成嵌入式有源或无源装置的电连接,可去除(例如通过激光钻孔技术)覆盖有源或无源装置的绝缘材料(例如预浸渍体)的一部分,以形成通孔。可例如通过镀敷技术将导电材料(例如铜(Cu)、银(Ag)或类似者)填充到通孔中。用于外部连接的无源元件的导电触点/端子通常包含锡(Sn)或焊接材料。然而,为了促进通过镀敷技术为嵌入式无源装置制造导电通孔,导电触点/端子可从焊料/Sn改变为具有相对较大导电性(例如Cu、Ag或其它合适材料)的材料,且此类定制结构可必然增加半导体装置封装的制造成本。
发明内容
在一些实施例中,一种半导体装置封装包含金属载体、无源装置、导电粘合材料、电介质层和导电通孔。所述金属载体具有第一导电垫和与第一导电垫隔开的第二导电垫。所述第一导电垫和所述第二导电垫中的每一者具有顶部表面和底部表面。第一导电垫和第二导电垫在其间限定空间。无源装置安置于第一导电垫和第二导电垫的顶部表面上。无源装置具有第一导电触点和第二导电触点。导电粘合材料将无源装置的第一导电触点和第二导电触点分别电连接到第一导电垫和第二导电垫。电介质层覆盖金属载体和无源装置,并暴露第一导电垫和第二导电垫的底部表面。导电通孔在电介质层内延伸,且电连接到第一导电垫和第二导电垫中的至少一者。
在一些实施例中,根据另一方面,一种半导体装置封装包含金属载体、无源装置、导电粘合材料和电介质层。所述金属载体具有第一导电垫和与第一导电垫隔开的第二导电垫。所述第一导电垫和所述第二导电垫中的每一者具有顶部表面和底部表面。第一导电垫和第二导电垫在其间限定空间。无源装置安置于第一导电垫和第二导电垫的顶部表面上。无源装置具有第一导电触点和第二导电触点。第一导电触点和第二导电触点包含锡。导电粘合材料将无源装置的第一导电触点和第二导电触点分别电连接到第一导电垫和第二导电垫。电介质层覆盖金属载体和无源装置,并暴露第一导电垫和第二导电垫的底部表面。
在一些实施例中,一种用于制造半导体装置封装的方法包含:(a)证明金属载体具有第一导电垫和通过连接部分连接到第一导电垫的第二导电垫;(b)通过导电粘合材料将无源装置连接到第一导电垫和第二导电垫;(c)形成覆盖金属载体和无源装置的电介质层;以及(d)去除所述连接部分来使第一导电垫与第二导电垫分离,以在其间形成空间。所述空间从所述电介质层暴露。
附图说明
图1A说明根据本公开的一些实施例的半导体装置封装的横截面图。
图1B说明根据本公开的一些实施例的图1A中的裸片垫的一部分的放大视图。
图1C说明根据本公开的一些实施例的图1A中的裸片垫的一部分的放大视图。
图1D说明根据本公开的一些实施例的图1A中的裸片垫的一部分的放大视图。
图2说明根据本公开的一些实施例的半导体装置封装的横截面图。
图3说明根据本公开的一些实施例的半导体装置封装的横截面图。
图4说明根据本公开的一些实施例的半导体装置封装的横截面图。
图5A、图5B、图5C、图5D和图5E说明根据本公开的一些实施例的制造工艺。
图6A、图6B、图6C和图6D说明根据本公开的一些实施例的制造工艺。
图7A、图7B、图7C、图7D和图7E说明根据本公开的一些实施例的制造工艺。
图8A、图8B和图8C说明根据本公开的一些实施例的制造工艺。
图9A、图9B和图9C说明根据本公开的一些实施例的制造工艺。
图10A、图10B和图10C说明根据本公开的一些实施例的制造工艺。
贯穿图式和详细描述使用共同参考标号来指示相同或类似组件。根据以下结合附图作出的详细描述将容易理解本公开。
具体实施方式
图1A说明根据本公开的一些实施例的半导体装置封装1的横截面图。半导体装置封装1包含金属载体10;电子组件11a、11b、11c;电介质层12、导电通孔13和导电层14。
金属载体10可为引线框或引线框的一部分。举例来说,金属载体10是包含一或多个裸片垫(或裸片桨)10a、10b和10c的引线框。裸片垫10a、10b和10c彼此分开。举例来说,任何两个邻近裸片垫之间均存在间隙。在一些实施例中,金属载体10是或包含铜或铜合金。在一些实施例中,可将锡镀敷在金属载体10上。在其它实施例中,金属载体10包含铁、铁合金、镍、镍合金或另一金属或金属合金中的一者或组合。在一些实施例中,金属载体10涂覆有银或铜层。
在一些实施例中,裸片垫10a包含腔10ar,用于容纳电子组件11a。裸片垫10a包含物理上彼此隔开的两个部分10a1和10a2。裸片垫10a的部分10a1与裸片垫10a的部分10a2之间存在间隙10s。在一些实施例中,裸片垫10a包含腔10cr,用于容纳电子组件11c。在一些实施例中,裸片垫10a、10b和10c的顶部表面10a3、10b1和10c1大体上共面。或者,裸片垫10a、10b和10c的顶部表面10a3、10b1和10c1可具有不同高度。在一些实施例中,裸片垫10a、10b和10c的底部表面10a4、10b2和10c2大体上共面。
图1B说明根据本公开的一些实施例的由点线矩形A圈起的图1A中的裸片垫10a的一部分的放大视图。出于清楚的目的,图1B中省略导电通孔13。金属载体10的裸片垫10a的部分10a1包含导电垫10p1,且金属载体10的裸片垫10a的部分10a2包含导电垫10p2。导电垫10p1包含第一侧表面10L11和第二侧表面10L12。导电垫10p2包含第一侧表面10L21和第二侧表面10L22,其分别面朝导电垫10p1的第一侧表面10L11和第二侧表面10L12。在一些实施例中,第一侧表面10L11和第二侧表面10L12是弯曲表面且彼此连接。第一侧表面10L21和第二侧表面10L22是弯曲表面且彼此连接。导电垫10p1的第一侧表面10L11和第二侧表面10L12与导电垫10p2的第一侧表面10L21和第二侧表面10L22隔开,以在其间限定间隙10s。
图1C说明根据本公开的其它实施例的由点线矩形A圈起的图1A中的裸片垫10a的一部分的放大视图。出于清楚的目的,图1C中省略导电通孔13。图1C中说明的结构类似于图1B中的结构,不同之处在于在图1C中,导电垫10p1仅具有一个弯曲表面10L13,且导电垫10p2仅具有一个弯曲表面10L23。弯曲表面10L13与弯曲表面10L23隔开,以在其间限定间隙10s。
返回参看图1A,电子组件11a安置在裸片垫10a的腔10ar内。在一些实施例中,电子组件11a可包含两个导电触点,其中一个导电触点(其可被称为“第一导电触点”)电连接到裸片垫10a的部分10a1((例如如图1B或图1C所示的导电垫10p1上),且另一导电触点(其可被称为“第二导电触点”)电连接到裸片垫10a的部分10a2(例如如图1B或图1C所示的导电垫10p2上)。举例来说,电子组件11a跨间隙10s安置。在一些实施例中,电子组件11a的导电触点包含锡或其合金。在一些实施例中,电子组件11a通过导电粘合剂层11h(例如焊料、镀敷膜或金属膜)附接到裸片垫10a。在一些实施例中,电子组件11a是无源装置,例如电阻器、电容器、电感器或其组合。电子组件11a通过金属载体10的裸片垫10a电连接到导电通孔13。在一些实施例中,导电通孔13包含锡或其合金。
电子组件11b安置于金属载体10的裸片垫10b的顶部表面10b1上。在一些实施例中,电子组件11b的背侧表面通过粘合剂层(例如胶水或胶带)附接到金属载体10的裸片垫10b。电子组件11b的作用表面电连接到导电通孔13。电子组件11b可包含芯片或裸片,其中包含半导体衬底、一或多个集成电路装置以及一或多个上覆互连结构。所述集成电路装置可包含有源装置,例如晶体管和/或无源装置,例如电阻器、电容器、电感器或其组合。在一些实施例中,电子组件11b的厚度不同于电子组件11a的厚度。举例来说,电子组件11a的厚度大于电子组件11b的厚度。
电子组件11c安置在裸片垫10c的腔10cr内。在一些实施例中,电子组件11c的背侧表面通过粘合剂层(例如胶水或胶带)附接到金属载体10的裸片垫10c。电子组件11c的作用表面电连接到导电通孔13。电子组件11c可包含芯片或裸片,其中包含半导体衬底、一或多个集成电路装置以及的一或多个上覆互连结构。所述集成电路装置可包含有源装置,例如晶体管和/或无源装置,例如电阻器、电容器、电感器或其组合。在一些实施例中,电子组件11c的厚度不同于电子组件11b的厚度。举例来说,电子组件11c的厚度大于电子组件11b的厚度。在一些实施例中,导电粘合材料11h、电子组件11b与裸片垫10b之间的粘合剂层或电子组件11c与裸片垫10c之间的粘合剂层的俯视图可为任何形状,取决于不同设计要求。
电介质层12安置于裸片垫10a、10b和10c上,以覆盖或包封电子组件11a、11b和11c。电介质层12安置在任何两个邻近裸片垫之间的间隙处。举例来说,电介质层12安置于裸片垫10a与裸片垫10b之间以及裸片垫10b与裸片垫10c之间的间隙中。电介质层12暴露裸片垫10a、10b和10c的底部表面10a4、10b2和10c2在一些实施例中,电介质层12的底部表面122与裸片垫10a、10b和10c的底部表面10a4、10b2和10c2大体上共面。在一些实施例中,电介质层12可包含模制化合物、预浸复合纤维(例如,预浸体)、硼磷硅玻璃(BPSG)、氧化硅、氮化硅、氮氧化硅、未掺杂的硅酸盐玻璃(USG)、其任何组合或类似者。模制化合物的实例可包含但不限于环氧树脂,包含分散在其中的填充剂。预浸体的实例可包括(但不限于)通过堆叠或层压许多预浸材料/片材而形成的多层结构。
在一些实施例中,电介质层12暴露裸片垫10a的部分10a1与裸片垫10a的部分10a2之间的间隙10s的至少一部分。举例来说,如图1B中所示,电介质层12安置于导电垫10p1的第一侧表面10L11与导电垫10p2的第一侧表面10L21之间,且电介质层12暴露导电垫10p1的第二侧表面10L12与导电垫10p2的第二侧表面10L22之间的空间。举例来说,如图1C所示,电介质层12暴露导电垫10p1的弯曲表面10L13与导电垫10p2的弯曲表面10L23之间的空间。在一些实施例中,电介质层12安置于电子组件11a的两个导电触点与之间,如图1B和图1C所示。或者,电介质层12可暴露电子组件11a的导电触点的一部分,如图1D所示,其说明根据本公开的一些实施例的图1A中的裸片垫10a的由点线矩形A圈起的部分的放大视图。
导电层14安置于电介质层12的顶部表面121上。导电层14通过导电通孔13电连接到电子组件11a、11b和11c。在一些实施例中,导电层14和导电通孔13由相同材料形成。或者,导电层14和导电通孔13可包含不同材料。
根据如图1A所示的实施例,将有源装置(例如电子组件11b和11c)和无源装置(例如电子组件11a)两者嵌入电介质层12内可改进半导体装置封装1的散热。此外,在一些实施例中,由于无源装置(例如电子组件11a)的导电触点和导电通孔13由相同材料(例如锡或其合金)形成,不必要使用定制的无源装置,这又将降低半导体装置封装1的制造成本。此外,将具有相对较大厚度的电子组件(例如电子组件11a和11c)放置到腔(例如10ar和10cr)中可减小半导体装置封装1的总厚度。
图2说明根据本公开的一些实施例的半导体装置封装2的横截面图。半导体装置封装2类似于图1A中所示的半导体装置封装1,且下文描述其间的差异。如图2中所示,裸片垫20a不具有间隙。另外,所有电子组件11a、11b和11c直接连接到导电通孔13。
图3说明根据本公开的一些实施例的半导体装置封装3的横截面图。半导体装置封装3类似于图2中示出的半导体装置封装2,不同之处在于金属载体30的所有裸片垫均具有腔30c,以容纳电子组件11a、11b和11c。
图4说明根据本公开的一些实施例的半导体装置封装4的横截面图。半导体装置封装4类似于图3中示出的半导体装置封装3,不同之处在于金属载体40的一些裸片垫(例如裸片垫40a)的腔的侧壁被去除。换句话说,不同于图3中的包含基座部分30a1和延伸部分30a2的裸片垫30a,图4中的裸片垫40a仅具有基座部分40a1,而无延伸部分。
图5A、图5B、图5C、图5D和图5E说明根据本公开的一些实施例的制造工艺。在一些实施例中,图5A、图5B、图5C、图5D和图5E中说明的制造工艺可用以形成如图1B所示的结构。
参看图5A,提供金属载体50(例如引线框或引线框的一部分)。金属载体50具有基座部分50a和延伸部分50b。基座部分50a和延伸部分50b限定腔50c。基座部分50a具有顶部表面50a1和与顶部表面50a1相对的底部表面50a2。
参看图5B,凹进部分50r1形成于金属载体50的基座部分50a的顶部表面50a1上。在一些实施例中,可通过蚀刻或其它合适的操作来形成凹进部分50r1。
参看图5C,电子组件51安置于金属载体50的腔50c内。电子组件51安置于金属载体50的基座部分50a上。电子组件51安置在凹进部分50r1之上。在一些实施例中,电子组件51可为无源装置(例如电阻器、电容器、电感器或其组合)。电子组件51包含两个导电触点51a和51b,其中导电触点51a安置在凹进部分50r1的一侧,且导电触点51b安置在凹进部分50r1的相对侧。
参看图5D,形成电介质层52以覆盖金属载体50和电子组件51的一部分。电介质层52暴露金属载体50的底部表面50a2。
参看图5E,去除电介质层52的一部分,以在金属载体50的底部表面50a2上形成凹进部分50r2。形成对应于凹进部分50r1的凹进部分50r2。凹进部分50r2连接到凹进部分50r1,以形成间隙来将金属载体50的基座部分50a分成两个分离的部分。
图6A、图6B、图6C和图6D说明根据本公开的一些实施例的制造工艺。在一些实施例中,图6A、图6B、图6C和图6D中说明的制造工艺可用以形成如图1C所示的结构。图6A中的操作在图5A中的操作之后进行。图6A、图6B、图6C和图6D中说明的制造工艺类似于图5B、图5C、图5D和图5E中的制造工艺,不同之处在于在图6A中,凹进部分60r1形成于金属载体50的基座部分50a的底部表面50a2上。因此,如图6D所示,间隙的侧壁仅具有一个弯曲表面,而在图5E中,间隙的侧壁具有彼此连接的两个弯曲表面。
图7A、图7B、图7C、图7D和图7E说明根据本公开的一些实施例的制造工艺。
参看图7A,提供金属载体70(例如引线框或引线框的一部分)。金属载体70包含多个裸片垫70a、70b和70c。在一些实施例中,裸片垫70a类似于图6A中说明的裸片垫。或者,裸片垫70a类似于图5B中说明的裸片垫。裸片垫70b和70c分别类似于图1A中说明的裸片垫10b和10c。因此,针对图1A和6A中说明的裸片垫的描述在此处适用。
参看图7B,电子组件71a安置于裸片垫70a的腔70c内,电子组件71b安置于裸片垫70b上,且电子组件71c安置于裸片垫70c的腔70r内。在一些实施例中,电子组件71a、71b和71c类似于图1A中的电子组件11a、11b和11c,且因此电子组件11a、11b和11c的描述和特性可适用于电子组件71a、71b和71c。在一些实施例中,在安置电子组件71b和71c之前,安置电子组件71a。
参看图7C,形成电介质层72,以覆盖或包封金属载体70以及电子组件71a、71b和71c。在一些实施例中,电介质层72类似于图1A中的电介质层12,且因此电介质层12的描述和特性可适用于电介质层12。在一些实施例中,可通过层压或其它合适的操作来形成电介质层72。导电层74形成于电介质层72上。
参看图7D,通孔73形成为穿透电介质层72,以将裸片垫70a、70b和70c与导电层72电连接。在一些实施例中,可通过以下操作来形成通孔73:(i)通过例如激光钻孔来形成通孔以穿透导电层74和电介质层72,以暴露裸片垫70a、70b和70c的一部分(例如裸片垫70a、70b和70c的导电垫);以及(ii)通过例如镀敷或其它合适的操作来锉削通孔内的导电材料(例如锡或其合金)。
在导电层74上进行图案化操作,以形成经图案化的导电层。去除电介质层72的在电子组件71a下方的部分,以形成凹进部分70s(或间隙)来将裸片垫70a分成两个分离的部分。在一些实施例中,图7D中说明的结构类似于图1A中的半导体装置封装1,且因此半导体装置封装1的描述和特性可适用于图7D中说明的结构。
参看图7E,焊接掩模(或防焊剂)75形成于经图案化的导电层74上。焊接掩模75具有一或多个凹进部分,以暴露经图案化的导电层74的一部分。电触点(例如焊料球)76形成于所述凹进部分内,以电连接到经图案化的导电层74的暴露部分。在一些实施例中,可通过例如锯割或其它合适的操作来进行单分操作。
图8A、图8B和图8C说明根据本公开的一些实施例的制造工艺。
参看图8A,提供金属载体20(例如引线框或引线框的一部分)。金属载体20类似于图2中所说明的金属载体20。接着,进行如图7B、7C和7D所示的操作以形成如图8B所示的结构,不同之处在于用于去除如图7D所示的电介质层72的一部分的操作可省略,且通孔13电连接到电子组件11a的导电触点而不是裸片垫20a。在一些实施例中,图8B中说明的结构类似于图2中的半导体装置封装2,且因此半导体装置封装2的描述和特性可适用于图8B中说明的结构。
参看图8C,焊接掩模(或防焊剂)85形成于经图案化的导电层14上。焊接掩模85具有一或多个凹进部分,以暴露经图案化的导电层14的一部分。电触点(例如焊料球)86形成于凹进部分内,以电连接到图案化导电层14的暴露部分。在一些实施例中,可通过例如锯割或其它合适的操作来进行单分操作。
图9A、图9B和图9C说明根据本公开的一些实施例的制造工艺。
参看图9A,提供金属载体30(例如引线框或引线框的一部分)。金属载体30类似于图3中所说明的金属载体30。接着,进行如图7B、7C和7D所示的操作以形成如图9B所示的结构,不同之处在于用于去除如图7D所示的电介质层72的一部分的操作可省略,且通孔13电连接到电子组件11a的导电触点而不是裸片垫30a。在一些实施例中,图9B中说明的结构类似于图3中的半导体装置封装3,且因此半导体装置封装3的描述和特性可适用于图9B中说明的结构。
参看图9C,焊接掩模(或防焊剂)95形成于经图案化的导电层14上。焊接掩模95具有一或多个凹进部分,以暴露经图案化的导电层14的一部分。电触点(例如焊料球)96形成于凹进部分内,以电连接到经图案化的导电层14的暴露部分。在一些实施例中,可通过例如锯割或其它合适的操作来进行单分操作。
图10A、图10B和图10C说明根据本公开的一些实施例的制造工艺。
参看图10A,提供金属载体40(例如引线框或引线框的一部分)。金属载体40类似于图4中说明的金属载体40。在一些实施例中,可通过例如蚀刻或其它合适的操作来去除裸片垫40a的延伸部分。接着,进行如图7B、7C和7D所示的操作以形成如图10B所示的结构,不同之处在于用于去除如图7D所示的电介质层72的一部分的操作可省略,且通孔13电连接到电子组件11a的导电触点而不是裸片垫40a。在一些实施例中,图10B中说明的结构类似于图4中的半导体装置封装4,且因此半导体装置封装4的描述和特性可适用于图10B中说明的结构。
参看图10C,焊接掩模(或防焊剂)105形成于经图案化的导电层14上。焊接掩模105具有一或多个凹进部分,以暴露经图案化的导电层14的一部分。电触点(例如焊料球)106形成于凹进部分内,以电连接到经图案化的导电层14的暴露部分。在一些实施例中,可通过例如锯割或其它合适的操作来进行单分操作。
如本文中所使用,术语“大体上”、“大体”、“近似地”和“约”用于表示少量变化。举例来说,当结合数值使用时,所述术语可指代小于或等于所述数值的±10%的变化范围,例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%。术语“大体上共面”或“大体上对准”可指两个表面在数微米(μm)内处于沿同一平面,例如在100μm内、80μm内、60μm内、40μm内、30μm内、20μm内、10μm内或1μm内处于沿同一平面。如果两个表面或组件之间的角为例如90°±10°,例如,±5°、±4°、±3°、±2°、±1°、±0.5°、±0.1°或±0.05°,那么两个表面或组件可被认为“大体上垂直”。当结合事件或情况使用时,术语“大体上”、“大体”、“近似地”和“约”可指其中事件或情况精确出现的例子,以及其中事件或情况非常近似出现的例子。术语“大体上平坦”可指约3μm到约20μm的表面粗糙度(Ra),其中表面的最高点与最低点之间的差为约5μm到约10μm。如本文中所使用,除非上下文另外明确规定,否则单数术语“一(a/an)”和“所述”可包含多个指示物。在一些实施例的描述中,提供于另一组件“上”或“之上”的组件可涵盖前者组件直接在后者组件上(例如,与后者组件物理接触)的情况,以及一或多个介入组件位于前者组件与后者组件之间的情况。
另外,有时在本文中按范围格式呈现量、比率和其它数值。应理解,此类范围格式是为了便利和简洁而使用,且应灵活地理解,不仅包含明确地指定为范围极限的数值,而且包含涵盖于所述范围内的所有个别数值或子范围,如同明确地指定每一数值和子范围一般。
尽管已参考本公开的特定实施例描述并说明本公开,但这些描述和说明并不限制本公开。所属领域的技术人员可清楚地理解,可进行各种改变,且可在实施例内替代等效元件而不脱离如由所附权利要求书定义的本公开的真实精神和范围。图解可能未必按比例绘制。归因于制造过程中的变量等等,本发明中的艺术再现与实际设备之间可能存在区别。可存在并未特定说明的本公开的其它实施例。应将说明书和图式视为说明性的,而不是限制性的。可做出修改,以使特定情形、材料、物质组成、方法或过程适应本公开的目标、精神以及范围。所有此类修改既定在所附权利要求书的范围内。虽然已参考按特定次序执行的特定操作描述了本文中所公开的方法,但可理解,可在不脱离本公开的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此,除非本文中特别指示,否则操作的次序和分组并非本发明的限制。
Claims (29)
1.一种半导体装置封装,其包括:
金属载体,其具有第一导电垫和与所述第一导电垫隔开的第二导电垫,所述第一导电垫和所述第二导电垫中的每一者具有顶部表面和底部表面,其中所述第一导电垫和所述第二导电垫之间限定空间;
无源装置,其安置于所述第一导电垫和所述第二导电垫的所述顶部表面上,所述无源装置具有第一导电触点和第二导电触点;
导电粘合材料,其将所述无源装置的所述第一导电触点和所述第二导电触点分别电连接到所述第一导电垫和所述第二导电垫;
电介质层,其覆盖所述金属载体和所述无源装置,且暴露所述第一导电垫和所述第二导电垫的所述底部表面;以及
导电通孔,其在所述电介质层内延伸,且电连接到所述第一导电垫和所述第二导电垫中的至少一者,
其中所述第一导电垫具有在所述顶部表面与所述底部表面之间的第一侧表面,所述第二导电垫具有在所述顶部表面与所述底部表面之间的第二侧表面,以及所述第一侧表面和所述第二侧表面中的每一者包含弯曲表面;
所述第一侧表面和所述第二侧表面中的每一者包含彼此连接的第一弯曲表面和第二弯曲表面;以及
所述第一侧表面的所述第一弯曲表面和所述第二侧表面的所述第一弯曲表面限定第一空间,其中安置所述电介质层,以及所述第一侧表面的所述第二弯曲表面和所述第二侧表面的所述第二弯曲表面限定从所述电介质层暴露的第二空间。
2.根据权利要求1所述的半导体装置封装,其中所述第一导电垫与所述第二导电垫限定的所述空间从所述电介质层暴露。
3.根据权利要求1所述的半导体装置封装,其中所述电介质层安置于所述无源装置的所述第一导电触点与所述第二导电触点之间。
4.根据权利要求1所述的半导体装置封装,其中所述无源装置的所述第一导电触点和所述第二导电触点包含锡或其合金。
5.根据权利要求1所述的半导体装置封装,其中所述金属载体包含腔以暴露所述第一导电垫和所述第二导电垫,且所述无源装置安置于所述腔内。
6.根据权利要求1所述的半导体装置封装,其中所述空间在所述第一侧表面与所述第二侧表面之间。
7.根据权利要求1所述的半导体装置封装,其进一步包括安置为邻近于所述无源装置且由所述电介质层包封的半导体芯片。
8.根据权利要求1所述的半导体装置封装,其中所述第一导电垫和所述第二导电垫的所述底部表面与所述电介质层的底部表面实质上共面。
9.一种半导体装置封装,其包括:
金属载体,其具有第一导电垫和与所述第一导电垫隔开的第二导电垫,所述第一导电垫和所述第二导电垫中的每一者具有顶部表面和底部表面,其中所述第一导电垫和所述第二导电垫之间限定空间;
无源装置,其安置于所述第一导电垫和所述第二导电垫的所述顶部表面上,所述无源装置第一导电触点和第二导电触点,其中所述第一导电触点和所述第二导电触点包含锡;
导电粘合材料,其将所述无源装置的所述第一导电触点和所述第二导电触点分别电连接到所述第一导电垫和所述第二导电垫;以及
电介质层,其覆盖所述金属载体和所述无源装置,且暴露所述第一导电垫和所述第二导电垫的所述底部表面,
其中所述第一导电垫具有在所述顶部表面与所述底部表面之间的第一侧表面,所述第二导电垫具有在所述顶部表面与所述底部表面之间的第二侧表面,以及所述第一侧表面和所述第二侧表面中的每一者包含弯曲表面,
所述第一侧表面和所述第二侧表面中的每一者包含彼此连接的第一弯曲表面和第二弯曲表面,以及
所述第一侧表面的所述第一弯曲表面和所述第二侧表面的所述第一弯曲表面限定第一空间,其中安置所述电介质层,以及所述第一侧表面的所述第二弯曲表面和所述第二侧表面的所述第二弯曲表面限定从所述电介质层暴露的第二空间。
10.根据权利要求9所述的半导体装置封装,其进一步包括导电通孔,所述导电通孔在所述电介质层内延伸,且电连接到所述第一导电垫和所述第二导电垫。
11.根据权利要求9所述的半导体装置封装,其中所述金属载体包含腔以暴露所述第一导电垫和所述第二导电垫,且所述无源装置安置于所述腔内。
12.根据权利要求9所述的半导体装置封装,其中所述空间在所述第一侧表面与所述第二侧表面之间。
13.根据权利要求9所述的半导体装置封装,其中所述第一导电垫和所述第二导电垫的所述底部表面与所述电介质层的底部表面实质上共面。
14.根据权利要求9所述的半导体装置封装,其中所述第一导电垫和所述第二导电垫限定的所述空间从所述电介质层暴露。
15.一种用于制造半导体装置封装的方法,所述方法包括:
(a)证明金属载体具有第一导电垫和通过连接部分连接到所述第一导电垫的第二导电垫;
(b)通过导电粘合材料将无源装置连接到所述第一导电垫和所述第二导电垫;
(c)形成覆盖所述金属载体和所述无源装置的电介质层;
(d)去除所述连接部分来使所述第一导电垫从所述第二导电垫分离以在其间形成空间,
其中所述空间从所述电介质层暴露;以及
在操作(a)之后,在所述连接部分上形成凹进部分。
16.根据权利要求15所述的方法,在操作(c)之后,其进一步包括
在所述电介质层上形成孔以暴露所述金属载体;以及
在所述电介质层上以及所述孔内形成导电层以电连接到所述金属载体。
17.根据权利要求15所述的方法,在操作(c)之前,其进一步包括:
将半导体裸片安置在所述金属载体上;以及
形成所述电介质层以覆盖所述半导体裸片。
18.根据权利要求15所述的方法,其中操作(b)进一步包括:
将所述导电粘合材料安置在所述第一导电垫和所述第二导电垫上;以及
将所述无源装置放置在所述导电粘合材料上。
19.根据权利要求15所述的方法,其中所述电介质层安置于所述凹进部分内。
20.一种半导体装置封装,其包括:
金属载体,其具有第一导电垫及第二导电垫,所述第一导电垫和所述第二导电垫中的每一者具有顶部表面和底部表面;
无源装置,其安置于所述第一导电垫和所述第二导电垫的所述顶部表面上,所述无源装置具有第一导电触点和第二导电触点;
导电粘合材料,其将所述无源装置的所述第一导电触点和所述第二导电触点分别电连接到所述第一导电垫和所述第二导电垫;
电介质层,其覆盖所述金属载体和所述无源装置;及
导电通孔,其在所述电介质层内延伸,且电连接到所述第一导电垫和所述第二导电垫的至少一者,
其中所述电介质层完全覆盖所述无源装置的顶部表面,
所述第一导电垫具有在所述顶部表面与所述底部表面之间的第一侧表面,所述第二导电垫具有在所述顶部表面与所述底部表面之间的第二侧表面,以及所述第一侧表面和所述第二侧表面中的每一者包含弯曲表面,
所述第一侧表面和所述第二侧表面中的每一者包含彼此连接的第一弯曲表面和第二弯曲表面,及
所述第一侧表面的所述第一弯曲表面和所述第二侧表面的所述第一弯曲表面限定第一空间,其中安置所述电介质层,及所述第一侧表面的所述第二弯曲表面和所述第二侧表面的所述第二弯曲表面限定从所述电介质层暴露的第二空间。
21.根据权利要求20所述的半导体装置封装,其中所述无源装置的所述第一导电触点和所述第二导电触点包含锡或其合金。
22.根据权利要求20所述的半导体装置封装,其中所述金属载体包含腔以暴露所述第一导电垫和所述第二导电垫,且所述无源装置安置于所述腔内。
23.根据权利要求20所述的半导体装置封装,其中所述第一导电垫和所述第二导电垫限定在其间之空间。
24.根据权利要求23所述的半导体装置封装,其中所述空间在所述第一侧表面与所述第二侧表面之间。
25.一种半导体装置封装,其包括:
金属载体,其具有第一导电垫和第二导电垫,所述第一导电垫和所述第二导电垫中的每一者具有顶部表面和底部表面;
无源装置,其安置于所述第一导电垫和所述第二导电垫的所述顶部表面上,所述无源装置第一导电触点和第二导电触点;
导电粘合材料,其将所述无源装置的所述第一导电触点和所述第二导电触点分别电连接到所述第一导电垫和所述第二导电垫;
电介质层,其覆盖所述金属载体和所述无源装置;及
一或多个导电通孔,其在所述电介质层内延伸,
其中所述第一导电触点和所述第二导电触点从所述导电通孔的任意者物理性地间隔开,
所述第一导电垫具有在所述顶部表面与所述底部表面之间的第一侧表面,所述第二导电垫具有在所述顶部表面与所述底部表面之间的第二侧表面,及所述第一侧表面和所述第二侧表面中的每一者包含弯曲表面,
所述第一侧表面和所述第二侧表面中的每一者包含彼此连接的第一弯曲表面和第二弯曲表面,及
所述第一侧表面的所述第一弯曲表面和所述第二侧表面的所述第一弯曲表面限定第一空间,其中安置所述电介质层,及所述第一侧表面的所述第二弯曲表面和所述第二侧表面的所述第二弯曲表面限定从所述电介质层暴露的第二空间。
26.根据权利要求25所述的半导体装置封装,其中所述无源装置的所述第一导电触点和所述第二导电触点包含锡或其合金。
27.根据权利要求25所述的半导体装置封装,其中所述金属载体包含腔以暴露所述第一导电垫和所述第二导电垫,且所述无源装置安置于所述腔内。
28.根据权利要求25所述的半导体装置封装,其中所述第一导电垫和所述第二导电垫限定在其间之空间。
29.根据权利要求28所述的半导体装置封装,其中所述空间在所述第一侧表面与所述第二侧表面之间。
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