CN109390293B - 半导体封装装置及其制造方法 - Google Patents
半导体封装装置及其制造方法 Download PDFInfo
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- CN109390293B CN109390293B CN201810066753.0A CN201810066753A CN109390293B CN 109390293 B CN109390293 B CN 109390293B CN 201810066753 A CN201810066753 A CN 201810066753A CN 109390293 B CN109390293 B CN 109390293B
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Abstract
一种半导体封装装置包括衬底、电组件及封装主体。所述电组件设置在所述衬底上。所述电组件具有面朝所述衬底的有源表面及与所述有源表面相反的背表面。所述背表面具有第一部分及围绕所述第一部分的第二部分。所述电组件的所述背表面的所述第一部分包括多个柱。所述封装主体设置在所述衬底上。所述封装主体包封所述电组件并且暴露所述电组件的所述背表面。
Description
技术领域
本发明大体上涉及一种半导体封装装置及其制造方法。更具体地说,本发明涉及一种包括散热结构的半导体封装装置及其制造方法。
背景技术
随着电子集成电路的电能消耗增加,将半导体装置的操作温度保持在可接受范围内是很有挑战性的。一般来说,将散热片或散热器接合到芯片或裸片的背侧进行散热。然而,使用散热片或散热器会增加裸片或芯片的制造成本及厚度。
发明内容
在一或多个实施例中,一种半导体封装装置包括衬底、电组件及封装主体。电组件设置在衬底上。电组件具有面朝衬底的有源表面及与所述有源表面相反的背表面。背表面具有第一部分及围绕所述第一部分的第二部分。电组件的背表面的第一部分包括多个柱。封装主体设置在衬底上。封装主体包封电组件并且暴露电组件的背表面。
在一或多个实施例中,一种半导体封装装置包括衬底、电组件及封装主体。电组件设置在衬底上。电组件具有面朝衬底的有源表面及与所述有源表面相反的背表面。背表面具有第一部分及围绕所述第一部分的第二部分。电组件的背表面的第一部分界定多个孔。封装主体设置在衬底上。封装主体包封电组件并且暴露电组件的背表面。
在一或多个实施例中,一种半导体封装装置包括衬底、电组件及封装主体。电组件设置在衬底上。电组件具有面朝衬底的有源表面、与所述有源表面相反的背表面以及在所述有源表面与所述背表面之间延伸的侧表面。电组件的侧表面界定多个孔。封装主体设置在衬底上。封装主体包封电组件并且暴露电组件的背表面及电组件的侧表面的多个孔。
附图说明
当结合附图阅读时,从以下详细描述能最佳地理解本发明的各方面。应注意,各种特征可不按比例绘制,且各种特征的尺寸可出于论述的清晰起见任意地增大或减小。
图1A示出根据本发明的一些实施例的半导体封装装置的横截面视图;
图1B示出根据本发明的一些实施例的图1A所示的半导体封装装置的一部分的放大视图;
图1C示出根据本发明的一些实施例的图1A所示的半导体封装装置的一部分的放大视图;
图1D示出根据本发明的一些实施例的图1A所示的半导体封装装置的一部分的放大视图;
图1E示出根据本发明的一些实施例的图1A所示的半导体封装装置的一部分的放大视图;
图2A示出根据本发明的一些实施例制造半导体封装装置的方法的一或多个阶段;
图2B示出根据本发明的一些实施例制造半导体封装装置的方法的一或多个阶段;
图2C示出根据本发明的一些实施例制造半导体封装装置的方法的一或多个阶段;
图2C'示出根据本发明的一些实施例制造半导体封装装置的方法的一或多个阶段;
图2D示出根据本发明的一些实施例制造半导体封装装置的方法的一或多个阶段;
图2D'示出根据本发明的一些实施例制造半导体封装装置的方法的一或多个阶段;
图3A示出根据本发明的一些实施例制造半导体封装装置的方法的一或多个阶段;
图3B示出根据本发明的一些实施例制造半导体封装装置的方法的一或多个阶段;
图3C示出根据本发明的一些实施例制造半导体封装装置的方法的一或多个阶段;
图4A示出根据本发明的一些实施例的电组件的一部分的透视图;以及
图4B示出根据本发明的一些实施例的电组件的一部分的透视图。
贯穿图式及具体实施方式使用共同参考数字以指示相同或类似元件。从以下结合附图作出的详细描述,本发明将会更显而易见。
具体实施方式
根据本发明的至少一些实施例,一种半导体封装装置包括电组件(例如,裸片或芯片)。在电组件的表面上设置呈纳米尺度的多个特征(例如,纳米尺度的柱或孔)以改进半导体封装装置的散热性。所述纳米尺度特征用作散热器并且取代相当的散热片,从而减小半导体封装装置的制造成本及总体厚度。
图1A示出根据本发明的一些实施例的半导体封装装置1A的横截面视图。半导体封装装置1A包括衬底10、电组件(例如,裸片或芯片)11及封装主体12。
衬底10可以是例如印刷电路板(PCB)、例如纸质铜箔层合物、复合铜箔层合物、聚合物浸渍的玻璃纤维类铜箔层合物,或其两者或多者的组合。衬底10可以包含互连结构10r,例如再分布层(RDL)。衬底10具有顶表面101(也称为“第一表面”)及与所述顶表面101相反的底表面102(也称为“第二表面”)。一或多个电接点10b设置在衬底10的底表面102上并且穿过互连结构10r电连接到衬底10的顶表面101。在一些实施例中,电接点10b是可控塌陷芯片连接(C4)凸点、焊料球、焊盘网格阵列(LGA),或其两者或多者的组合。
电组件11设置在衬底10的顶表面101上。电组件11具有面朝衬底10的顶表面101的有源表面111、与所述有源表面111相反的背表面112(也称为背侧),以及在有源表面111与背表面112之间延伸的侧表面113。电组件11可以在其中包含半导体衬底、一或多个集成电路装置及一或多个上覆的互连结构。集成电路装置可以包含晶体管等有源装置和/或电阻器、电容器、电感器等无源装置,或其两者或多者的组合。
封装主体12设置在衬底10的顶表面101上,并且覆盖衬底10的顶表面101及电组件11的一部分。电组件11的背表面112从封装主体12暴露。在一些实施例中,电组件11的侧表面113的一部分从封装主体12暴露。替代地,电组件11的侧表面113可以被封装主体12完全覆盖。在一些实施例中,封装主体12包含具有填充物的环氧树脂、模塑料(例如,环氧模塑料或其它模塑料)、聚酰亚胺、酚化合物或材料、具有分散在其中的硅酮的材料,或其两者或多者的组合。
图1B示出根据本发明的一些实施例的图1A所示的半导体封装装置1以圆圈A标记的一部分的放大视图。
电组件11的背表面112具有第一部分11A及围绕第一部分11A的第二部分11B。在一些实施例中,第一部分11A可以是电组件11的背表面112的中心部分,并且第二部分11B可以是电组件11的背表面112的边缘。
如图1B所示,电组件11的背表面112的第一部分11A包含多个柱11p。在一些实施例中,柱11p是纳米柱。例如,柱11p中的每一个的高度及宽度中的任一者或两者呈纳米尺度。在一些实施例中,柱11p及电组件11的背表面112由相同材料形成。例如,柱11p是电组件11的背表面112的部分,并且与电组件11的其余部分一体地形成为整体式或均质结构。在一些实施例中,柱11p的高度彼此不同。在一些实施例中,至少柱11p的最高部分高于电组件11与封装主体12之间的分界面。本发明还涵盖并非以纳米尺度设定大小的柱,例如具有大于100纳米(nm)以及高达500nm或更大的高度和/或宽度。
在一些实施例中,电组件11与封装主体12之间的分界面与电组件11的背表面112的第二部分11B大体上共面或低于所述第二部分,以避免电组件11的顶表面112的边缘处的开裂。在一些实施例中,电组件11的背表面112的第一部分11A不与电组件11的背表面112的第二部分11B共面。例如,取决于不同实施例的各种布置,电组件11的背表面112的第一部分11A可以高于电组件11与封装主体12之间的分界面、与所述分界面大体上共面或低于所述分界面。
如图1B所示,封装主体12的顶表面121为大体上平坦的。在其它实施例中,例如,如图1E所示,封装主体12的顶表面121'可以是弧形的。
通过在电组件11的背表面112上形成从封装主体12暴露的纳米柱11p,可以改进电组件11的散热性能。另外,由于在半导体封装装置1中不包含散热片,因此可减小半导体封装装置1的制造成本及厚度。
图1C示出根据本发明的一些实施例的图1A所示的半导体封装装置1以圆圈A标记的一部分的放大视图。
如图1C所示,封装主体12的顶表面121低于电组件11的背表面112的第二部分11B以暴露电组件11的侧表面113的一部分。电组件11的侧表面113的暴露部分界定多个孔(或凹口)11h1。在一些实施例中,孔11h1是纳米孔。例如,孔11h1中的每一个的深度及宽度中的任一者或两者呈纳米尺度。本发明还涵盖并非以纳米尺度设定大小的孔,例如具有大于100nm以及高达500nm或更大的深度和/或宽度。
图1D示出根据本发明的一些实施例的图1A所示的半导体封装装置1以圆圈A标记的一部分的放大视图。图1D所示的结构类似于图1B所示的结构,不同之处在于在图1D所示的结构中,电组件11的背表面112的第一部分11A界定多个孔(或凹口)11h2。在一些实施例中,孔11h2是纳米孔。例如,孔11h2中的每一个的深度及宽度中的任一者或两者呈纳米尺度。在一些实施例中,孔11h2的深度或宽度彼此不同。
通过在电组件11的背表面112上形成从封装主体12暴露的纳米孔11h2,可以改进电组件11的散热性能。另外,由于在半导体封装装置1中不包含散热片,因此可减小半导体封装装置1的制造成本及厚度。
图2A、2B、2C、2C'、2D及2D'是根据本发明的一些实施例的在各个阶段制造的半导体结构的横截面图。为了更好地理解本发明的各方面,已简化各图。
参考图2A,提供在其上具有胶粘剂29a(例如,胶带)的载体29。通过胶粘剂29a将多个电组件21附接到载体29以便于后续处理。电组件21具有有源表面211及面朝载体29的背表面212(也称为背侧)。例如,电组件21的背表面212附接到载体29。
接着在载体29上形成封装主体22以覆盖电组件21。在一些实施例中,封装主体22包含具有填充物的环氧树脂、模塑料(例如,环氧模塑料或其它模塑料)、聚酰亚胺、酚化合物或材料、具有分散在其中的硅酮的材料,或其两者或多者的组合。
参考图2B,移除封装主体22的一部分以暴露电组件21的有源表面211上的导电衬垫。在一些实施例中,可以通过例如磨削、蚀刻或其它合适的工艺移除封装主体22。
参考图2C,在封装主体22上形成电路层20或再分布层(RDL),并且所述电路层20或再分布层(RDL)与电组件21的有源表面211上的导电衬垫电连接。电路层20包含介电层或绝缘层20d及由介电层20d包封或覆盖的导电层20r(例如,金属层)。在一些实施例中,可以通过以下操作形成电路层20:(i)在封装主体22上形成光刻胶或掩模;(ii)通过例如光刻技术在光刻胶或掩模上界定预定图案;(iii)镀覆导电材料以形成图案化导电层20r;以及(iv)移除光刻胶或掩模。
接着在导电层20r上形成电接点20b。在一些实施例中,电接点20b是C4凸点、BGA、LGA或其两者或多者的组合。在一些实施例中,可以通过例如电镀、无电镀敷、溅镀、锡膏印刷、凸点成形或粘结工艺形成电接点20b。
如图2C所示,电组件21的背表面212与封装主体22的表面大体上共面。在一些实施例中,如图2C'所示,电组件21'可以沉降到胶粘剂29a中,并且因此电组件21'的背表面212不与封装主体22'的表面共面。
参考图2D,从封装主体22移除载体29连同胶粘剂29a以暴露电组件21的背表面212。可以执行分离工艺以将图2D所示的结构分离成个别的半导体封装装置。在一些实施例中,可以通过锯切、激光或其它合适的工艺来执行分离工艺。
图2D'所示的操作类似于图2D所示的操作,不同之处在于图2D'所示的操作是在图2C'所示的操作(电组件21'沉降到胶粘剂29a中)之后执行的,而图2D所示的操作是在图2C所示的操作之后执行的。
图3A、3B及3C是根据本发明的一些实施例在图2D所示的操作之后在各个阶段制造的半导体结构的放大部分(以图2D中的正方形方形B为标记)的横截面视图。为了更好地理解本发明的各方面,已简化各图。
参考图3A,在电组件21的背表面212上涂覆含银离子(例如,AgNO3的银离子Ag+)的多个颗粒28。在一些实施例中,可以将含银离子(Ag+)的颗粒28涂覆在电组件21的从封装主体22暴露的侧表面213的一部分上。
参考图3B,接着在电组件21的由例如硅(Si)组成的背表面212上执行氧化还原反应(Redox)。例如,氧化电组件21的背表面212以在背表面212和/或侧表面213上的一些位置处形成二氧化硅(SiO2)。接着,在电组件21的背表面212上涂覆氢氟酸(HF)以移除SiO2,从而在电组件21的背表面212及侧表面213上形成多个孔21h1、21h2。
如果在涂覆氢氟酸过程期间终止蚀刻工艺,或Ag+的浓度不够,那么电组件21的背表面212可以处于如图4A所示的状态,其示出电组件21的一部分的透视图。如图4A所示,电组件21的背表面212及侧表面213限定多个孔21h1、21h2。在一些实施例中,图4A所示的结构类似于图1D所示的结构,不同之处在于图1D所示的电组件11的侧表面113不界定孔。
参考图3C,如果蚀刻工艺继续进行或Ag+的浓度增加(例如,通过涂覆Fe(NO3)3或H2O2作为氧化剂),那么电组件21的背表面212可以处于如图4B所示的状态,其示出电组件21的一部分的透视图。如图4B所示,电组件21的背表面212包含多个柱21p。在一些实施例中,图4B所示的结构类似于图1B所示的结构。在一些实施例中,由于在电组件21的侧表面213上执行的蚀刻工艺,可能移除邻近电组件21的背表面212的第二部分(例如,边缘部分)21B的一些柱21p。因此,大部分柱21p位于电组件21的背表面212的第一部分(例如,中心部分)21A处。
在一些实施例中,可以通过将电组件21的背表面212在介于从约60度到约800度的温度下浸入与AgNO3及HF混合的溶液中约1到5分钟来执行图3A到3C所示的操作。操作温度和/或操作时间周期的选择可以取决于需要或指定哪种最终结构(图4A或图4B中的结构)。
如本文中所使用,物体的尺寸呈“纳米尺度”或“纳米级尺度”意味着物体的尺寸是从1纳米(nm)到100nm,例如从1nm到50nm,或从1nm到10nm。
如本文中所使用,术语“大致”、“大体上”、“大体”及“约”用于描述及解释小的变化。当与事件或情形结合使用时,所述术语可以指其中事件或情形明确发生的情况以及其中事件或情形极接近于发生的情况。例如,当结合数值使用时,所述术语可以指小于或等于所述数值的±10%的变化范围,例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%。例如,如果两个数值之间的差值小于或等于所述值的平均值的±10%(例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%),那么可认为所述两个数值“大体上”相同或“约为”相同。例如,“大体上”平行可以指小于或等于±10°的相对于0°的角度变化范围,例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°。例如,“大体上”垂直可以指小于或等于±10°的相对于90°的角度变化范围,例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°。
如果两个表面之间的移位不超过5μm、不超过2μm、不超过1μm或不超过0.5μm,那么这两个表面可以被视为共面或大体上共面。
如本文中所使用,术语“传导性”、“导电性”和“电导率”是指输送电流的能力。导电材料通常指示那些对电流流动呈现极少反作用或不呈现反作用的材料。电导率的一个量度为西门子每米(S/m)。通常,导电材料是电导率大于大致104S/m(例如至少105S/m或至少106S/m)的一种材料。材料的电导率有时可以随温度而变化。除非另外规定,否则在室温下测量材料的电导率。
如本文中所使用,除非上下文另外明确规定,否则单数术语“一”及“所述”可以包含多个参考物。在一些实施例的描述中,一个组件提供于另一组件“上”或“上方”可涵盖前一组件直接在后一组件上(例如,与后一组件物理接触)的情况,以及一或多个中间组件位于前一组件与后一组件之间的情况。
虽然已参考本发明的特定实施例描述及说明本发明,但这些描述及说明并不限制本发明。所属领域的技术人员可清楚地理解,可进行各种改变,且可在实施例内替代等效组件而不脱离如由所附权利要求书定义的本发明的真实精神及范围。所述说明可能未必按比例绘制。归因于制造过程及公差,本发明中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书及图式视为说明性的而非限制性的。可做出修改,以使具体情况、材料、物质组成、方法或工艺适应于本发明的目标、精神及范围。所有所述修改都既定在所附权利要求书的范围内。虽然本文揭示的方法已参考按特定次序执行的特定操作加以描述,但应理解,可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此,除非本文中特别指示,否则操作的次序及分组并非对本发明的限制。
Claims (8)
1.一种半导体封装装置,其包括:
衬底;
所述衬底上的电组件,所述电组件具有面向所述衬底的有源表面及与所述有源表面相反的背表面,所述背表面具有第一部分及围绕所述第一部分的第二部分,其中所述电组件包括多个柱,所述多个柱从所述第一部分突出;以及
所述衬底上的封装主体,所述封装主体封装所述电组件并且暴露所述电组件的所述背表面;
其中所述多个柱的底部之间的表面与所述封装主体的顶表面大体上共面或高于所述顶表面。
2.根据权利要求1所述的半导体封装装置,其中所述电组件与所述封装主体之间的分界面与所述电组件的所述背表面的所述第二部分大体上共面或低于所述第二部分。
3.根据权利要求1所述的半导体封装装置,其中所述电组件的所述背表面的所述第一部分的最高部分高于所述电组件与所述封装主体之间的分界面。
4.根据权利要求1所述的半导体封装装置,其中所述多个柱是纳米柱。
5.根据权利要求1所述的半导体封装装置,其中所述柱的最高部分高于所述电组件与所述封装主体之间的分界面,且其中所述封装主体具有连接所述分界面的侧表面的弧面。
6.根据权利要求1所述的半导体封装装置,其中所述柱是所述电组件的部分。
7.根据权利要求1所述的半导体封装装置,其中所述电组件进一步包括在所述有源表面与所述背表面之间延伸的侧表面,并且所述侧表面界定多个孔,其中所述多个孔中的其中一者从所述第二部分向所述第一部分延伸。
8.根据权利要求7所述的半导体封装装置,其中所述孔的深度或宽度呈纳米尺度。
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