CN112018064A - 半导体装置封装及其制造方法 - Google Patents

半导体装置封装及其制造方法 Download PDF

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Publication number
CN112018064A
CN112018064A CN201910659592.0A CN201910659592A CN112018064A CN 112018064 A CN112018064 A CN 112018064A CN 201910659592 A CN201910659592 A CN 201910659592A CN 112018064 A CN112018064 A CN 112018064A
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conductive
semiconductor device
conductive post
carrier
device package
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CN201910659592.0A
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English (en)
Inventor
张勇舜
李德章
赖威宏
施孟铠
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN112018064A publication Critical patent/CN112018064A/zh
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Abstract

一种半导体装置封装包含载体、导电柱和第一封装主体。所述载体具有第一表面和与所述第一表面相对的第二表面。所述导电柱安置在所述载体的所述第二表面上。所述第一封装安置在所述载体的所述第二表面上并且覆盖所述导电柱的至少一部分。所述导电柱具有不均匀的宽度。

Description

半导体装置封装及其制造方法
技术领域
本发明大体上涉及半导体装置封装及其制造方法。更确切地说，本发明涉及包含导电柱的半导体装置封装及其制造方法。
背景技术
导电柱(例如，铜柱)广泛地在用于电连接的半导体装置封装中使用。为了保护导电柱，可以形成模制化合物以覆盖导电柱。然而，在制造半导体装置封装的各种过程期间，应力将被应用于半导体装置封装的组件或结构以在各种方向上弯曲那些组件或结构(例如，弯曲)。因此，分层问题可能出现在模制化合物与导电柱之间，并且在制造过程期间导电柱可能剥离或掉落。
发明内容
在一或多个实施例中，半导体装置封装包含载体、导电柱和第一封装主体。载体具有第一表面和与第一表面相对的第二表面。导电柱安置在载体的第二表面上。第一封装安置在载体的第二表面上并且覆盖导电柱的至少一部分。导电柱具有不均匀的宽度。
在一或多个实施例中，半导体装置封装包含载体、导电柱和第一封装主体。载体具有第一表面和与第一表面相对的第二表面。导电柱安置在载体的第二表面上。导电柱具有面向载体的第一表面、与第一表面相对的第二表面，以及在导电柱的第一表面与第二表面之间延伸的第一横向表面。第一封装安置在载体的第二表面上并且覆盖导电柱的至少一部分。第一封装主体具有面向载体的第一表面和与第一表面相对的第二表面。导电柱的第一横向表面并不垂直于第一封装主体的第一表面。
在一或多个实施例中，制造半导体装置封装的方法包含：(a)提供具有安置在其上的晶种层的载体；(b)在晶种层上形成导电柱，导电柱具有不均匀的宽度；以及(c)在晶种层上形成第一封装主体以覆盖导电柱。
附图说明
当结合附图阅读时，从以下详细描述最好地理解本发明的各方面。应注意各种特征可能未按比例绘制，且各种特征的尺寸可出于论述的清楚起见而任意增大或减小。
图1说明根据本发明的一些实施例的半导体装置封装的截面图。
图2A说明根据本发明的一些实施例的导电柱的截面图；
图2B说明根据本发明的一些实施例的导电柱的截面图；
图2C说明根据本发明的一些实施例的导电柱的截面图；
图2C'说明根据本发明的一些实施例的导电柱的截面图；
图2D说明根据本发明的一些实施例的导电柱的截面图；
图2E说明根据本发明的一些实施例的导电柱的截面图；
图3A、图3B、图3C、图3D、图3E、图3F、图3G和图3H说明根据本发明的一些实施例的制造电子组件的方法的各个阶段。
贯穿图式和详细描述使用共同参考标号来指示相同或类似元件。根据以下结合附图作出的详细描述，本发明将将更显而易见。
具体实施方式
在下文详细论述本发明的实施例的结构、制造和使用。然而，应了解，实施例阐述了可在多种多样的特定情境中实施的许多适用的概念。应理解，以下公开内容提供了实施各种实施例的不同特征的许多不同实施例或实例。下文出于论述的目的描述组件和布置的特定实例。当然，这些仅是实例且并不意图是限制性的。
下文使用特定语言公开图中所说明的实施例或实例。然而，将理解，所述实施例或实例并不意图是限制性的。如相关领域的普通技术人员通常所理解地，所公开的实施例的任何变更以及修改以及本文档中所公开的原理的任何进一步应用处于本发明的范围内。
另外，本发明可能在各个实例中重复参考数字和/或字母。此重复是出于简单和清晰的目的，且本身并不规定所论述的各种实施例和/或配置之间的关系。
图1说明根据本发明的一些实施例的半导体装置封装1的截面图。半导体装置封装1包含电路层10、封装主体11、14、一或多个导电柱12、电子组件13、15a、15b和电触点。
电路层10(也可以是载体或衬底)包含互连层(例如，再分布层，RDL)10r和介电层10d。互连层10r的一部分由介电层10d覆盖或囊封，而互连层10r的另一部分从介电层10d暴露以提供用于电子组件13、15a和15b的电连接。在一些实施例中，介电层10d可包含模制化合物、预浸复合纤维(例如，预浸体)、掺杂硼磷的硅玻璃(BPSG)、氧化硅、氮化硅、氮氧化硅、未掺杂的硅玻璃(USG)、其中两者或多于两者的任何组合，或类似者。模制化合物的实例可包含但不限于包含分散在其中的填充物的环氧树脂。预浸体的实例可包含但不限于通过堆叠或层压多个预浸材料/片材而形成的多层结构。在一些实施例中，取决于设计规范可存在任何数量的互连层10r。电路层10包含表面101和与表面101相对的表面102。
电子组件13安置在电路层10的表面102上。电子组件13具有面向电路层10的有源表面和与有源表面相对的后表面(也被称作后侧)。一或多个电触点13c安置在电子组件13的有源表面上。电触点13c电连接到电路层10(例如，到互连层10r)。电子组件13可以是在其中包含半导体衬底、一或多个集成电路装置和一或多个上覆互连结构的芯片或裸片。集成电路装置可包含例如晶体管的有源装置和/或例如电阻器、电容器、电感器的无源装置，或其组合。
导电柱12安置在电路层10的表面102上并且电连接到电路层10(例如，到互连层10r)。在一些实施例中，导电柱12可包含铜。然而，例如镍和/或铝或各种金属的组合的其它导电材料或其它导电材料也可以在导电柱12中使用。
封装主体11安置在电路层10的表面102上以覆盖或囊封电子组件13和导电柱12。举例来说，封装主体11可覆盖导电柱12的横向表面并且暴露导电柱12的上部部分和下部部分以用于电连接。在一些实施例中，封装主体11包含具有填充物的环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料，具有分散在其中的硅酮的材料，或其组合。封装主体11具有面向电路层10的表面111和与表面111相对的表面112。在一些实施例中，晶种层12s可以安置在封装主体12的表面112上并且电连接到从封装主体11暴露的导电柱12的下部部分。
电触点16安置在封装主体11的表面112上并且电连接到导电柱12以在半导体装置封装1与其它电路或电路板之间提供电连接。在一些实施例中，电触点16可以是或包含可控塌陷芯片连接(C4)凸块。
电子组件15a和15b安置在电路层10的表面101上。电子组件15a和15b中的每一个具有面向电路层10的有源表面和与有源表面相对的后表面(也被称作后侧)。电子组件15a和15b可以通过倒装芯片或导线接合技术电连接到电路层10(例如，到互连层10r)。电子组件15a和15b中的每一个可以是在其中包含半导体衬底、一或多个集成电路装置和一或多个上覆互连结构的芯片或裸片。集成电路装置可包含例如晶体管的有源装置和/或例如电阻器、电容器、电感器的无源装置，或其组合。
封装主体14安置在电路层10的表面101上以覆盖或囊封电子组件15a和15b。在一些实施例中，封装主体14包含具有填充物的环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料，具有分散在其中的硅酮的材料，或其组合。在一些实施例中，封装主体14和封装主体11可包含相同材料。替代地，封装主体14和封装主体11可包含不同材料。
图2A说明根据本发明的一些实施例的图1中所说明的导电柱12的截面图。如图2A中所示，导电柱12的截面图是矩形的形状。举例来说，图2A中所说明的导电柱12可以是圆柱形。导电柱12具有表面121和与表面101相对的表面122。在一些实施例中，导电柱12的表面121的宽度WA1与导电柱12的表面122的宽度WA2基本上相同。
在制造半导体装置封装1的各种过程期间，应力将被应用于半导体装置封装1的组件或结构(例如，电路层10、封装主体11、14、导电柱12及类似者)以在各种方向上弯曲那些组件或结构(例如，弯曲)。因此，分层问题可能出现在封装主体11与导电柱12之间。根据图2A中的实施例，因为导电柱12是圆柱形的形状，所以导电柱12的横向表面是直的。因此，当分层问题发生时，在制造过程期间导电柱12可能剥离或掉落。
图2B说明根据本发明的一些实施例的图1中所说明的导电柱12的截面图。如图2B中所示，导电柱12的截面图是梯形的形状的。举例来说，导电柱12的表面121的宽度WB1小于导电柱12的表面122的宽度WB2。导电柱12具有连接在表面121与表面122之间的横向表面123。横向表面123的斜率(或梯度)小于90度。在一些实施例中，在图1中导电柱12的表面121面向半导体装置封装1的电路层10，并且在图1中导电柱12的表面122背对半导体装置封装1的电路层10。替代地，在图1中导电柱12的表面121背对半导体装置封装1的电路层10，并且取决于不同设计要求在图1中导电柱12的表面122面向半导体装置封装1的电路层10。
根据图2B中的实施例，因为导电柱12的横向表面123是倾斜的(即，斜率小于90度)，所以图1中的半导体装置封装1的横向表面123与封装主体11之间的接触区域是相对大的(与图2A中的导电柱12进行比较)，这可以增大其间的连接能力(类似于锁模的效果)。另外，在去载体过程(将在下文中描述去载体过程)期间应用到导电柱12的应力可以减少。举例来说，在去载体操作期间应用到图2B中的导电柱12的应力小于应用到图2A中的导电柱12的应力18％。
图2C说明根据本发明的一些实施例的图1中所说明的导电柱12的截面图。如图2C中所示，导电柱12的截面图是沙漏的形状的。举例来说，导电柱12的上部部分是从表面121朝向表面122锐化的，并且导电柱12的下部部分是从表面122朝向表面121锐化的。上部部分和下部部分在导电柱12的中间部分处或邻近于导电柱12的中间部分连接到彼此。举例来说，横向表面123从表面121朝向表面122朝内倾斜，并且横向表面124从表面122朝向表面121朝内倾斜。横向表面123和横向表面124在导电柱12的中间部分处或邻近于导电柱12的中间部分连接到彼此。举例来说，导电柱12的表面121的宽度WC1与导电柱12的表面122的宽度WC2基本上相同，并且宽度WC1或WC2大于横向表面123和横向表面124的接头部分(或上部部分和下部部分)的宽度WC3。在一些实施例中，导电柱12可限定凹部12r。
根据图2C中的实施例，因为导电柱12的横向表面123和横向表面124是朝内倾斜的(即，斜率小于90度)以限定沙漏状导电柱，所以图1中的半导体装置封装1的横向表面123、124与封装主体11之间的接触区域是相对大的(与图2A中的导电柱12进行比较)，这可以增大其间的连接能力(类似于锁模的效果)。
在一些实施例中，如图2C'中所示，横向表面123和横向表面124的连接部分(或接头部分)接近于表面122。在其它实施例中，横向表面123和横向表面124的连接部分(或接头部分)可以接近于表面121。举例来说，横向表面123和横向表面124的连接部分并不位于导电柱12的中间部分处。举例来说，横向表面123和横向表面124的连接部分可以接近于如图1中所示的封装主体11的表面111或表面112。在横向表面123和横向表面124的连接部分接近于封装主体11的表面112的情况下，导电柱12与封装主体11之间的锁模的效果增强，这可以增大其间的连接能力。
图2D说明根据本发明的一些实施例的图1中所说明的导电柱12的截面图。图2D中的导电柱12的结构类似于图2C中的导电柱12的结构，不同之处在于图2D中的导电柱12具有弯曲的横向表面123。举例来说，图2D中的导电柱12的横向表面123限定弯曲的凹部12r。
图2E说明根据本发明的一些实施例的图1中所说明的导电柱12的截面图。如图2E中所示，导电柱12的截面图是六边形的形状的。举例来说，横向表面123从表面121朝向表面122朝内倾斜，并且横向表面124从表面122朝向表面121朝外倾斜。横向表面123和横向表面124在导电柱12的中间部分处或邻近于导电柱12的中间部分连接到彼此。举例来说，导电柱12的表面121的宽度WE1与导电柱12的表面122的宽度WE2基本上相同，并且宽度WE1或WE2大于横向表面123和横向表面124的接头部分的宽度WE3。在一些实施例中，宽度WE3大于宽度WE1或WE2 20％到50％。
根据图2E中的实施例，因为导电柱12的横向表面123和横向表面124是朝外倾斜的，所以图1中的半导体装置封装1的横向表面123、124与封装主体11之间的接触区域是相对大的(与图2A中的导电柱12进行比较)，这可以增大其间的连接能力(类似于锁模的效果)。另外，在去载体过程(将在下文中描述去载体过程)和用于形成封装主体11的过程期间应用到导电柱12的应力可以减少。举例来说，在去载体操作期间应用到图2E中的导电柱12的应力小于应用到图2A中的导电柱12的应力1.5％，并且在用于形成封装主体11的过程期间应用到图2E中的导电柱12的应力小于应用到图2A中的导电柱12的应力8％。
图3A、图3B、图3C、图3D、图3E、图3F和图3G是根据本发明的一些实施例的在各个阶段制造的半导体结构的截面图。为了更好的理解本发明的各方面，已经简化各图。在一些实施例中，图3A、图3B、图3C、图3D、图3E、图3F和图3G中说明的操作可用于制造图1中的半导体装置封装。
参考图3A，提供载体39。晶种层12s安置在载体39上。光阻剂38安置在晶种层39上。光阻剂38具有多个开口38h以暴露晶种层39。在一些实施例中，光阻剂38是正性抗蚀剂。替代地，取决于不同设计要求光阻剂38可以是负性抗蚀剂。在一些实施例中，光阻剂38经图案化，因此光阻剂38的开口38h可以呈导电柱12的形状，如图2A到2E中的任一个中所示。在一些实施例中，可以通过调节光刻过程的参数来控制或确定光阻剂38的图案。
参考图3B，导电材料安置或形成在开口38h内以形成导电柱12。在一些实施例中，导电材料可以通过例如镀覆或任何其它合适的过程形成。随后通过例如蚀刻或任何其它合适的过程移除光阻剂38。
参考图3C，电子组件13安置在晶种层12s上。在一些实施例中，电子组件13的后表面例如通过粘合层13d(例如，裸片附接膜，DAF)附接到晶种层12s。
参考图3D，封装主体11形成在晶种层12s上以完全地覆盖电子组件13和导电柱12。在一些实施例中，封装主体11可以通过模制过程(例如，压缩模制、传递模制或类似者)或任何其它合适的过程形成。
参考图3E，移除封装主体11的一部分以暴露导电柱12的上部部分和电子组件13的电触点13c。在一些实施例中，通过例如研磨或任何其它合适的过程移除封装主体11的部分。
参考图3F，电路层10(包含互连层10r和覆盖互连层10r的一部分的介电层10d)形成在封装主体11上并且电连接到导电柱12和电子组件13的电触点13c。在一些实施例中，一或多个微衬垫(μ衬垫)可以构建在电路层10上。
参考图3G，电子组件15a和15b安置在电路层10上并且电连接到电路层10(例如，到互连层10r和/或到μ衬垫)。在一些实施例中，电子组件15a和15b可以通过例如倒装芯片或任何其它合适的技术电连接到电路层10。在一些实施例中，底部填充物可以形成在电子组件15a、15b与电路层10之间以覆盖电子组件15a和15b的电触点。
参考图3H，封装主体14形成在电路层10上以覆盖电子组件15a和15b。在一些实施例中，封装主体14可以通过模制过程(例如，压缩模制、传递模制或类似者)或任何其它合适的过程形成。载体39被从晶种层12s移除(即，去载体过程)，并且随后安置电触点16以用于形成在晶种层12s上。
如本文中所使用，术语“近似地”、“基本上”、“实质”和“约”用于描述和解释小的变化。当与事件或情况结合使用时，所述术语可指事件或情况精确地发生的例子以及事件或情况极近似地发生的例子。举例来说，当与数值结合使用时，术语可指小于或等于所述数值的±10％的变化范围，例如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％)，那么可认为所述两个数值“基本上”相同或相等。举例来说，“基本上”平行可以指相对于0°的小于或等于±10°的角度变化范围，例如，小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。举例来说，“基本上”垂直可以指相对于90°的小于或等于±10°的角度变化范围，例如，小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。
如果两个表面之间的位移不大于5μm、不大于2μm、不大于1μm或不大于0.5μm，那么可认为所述两个表面是共面的或基本上共面的。
如本文中所使用，术语“导电(conductive)”、“导电(electrically conductive)”和“电导率”是指传送电流的能力。导电材料通常指对电流流动呈现极少或零对抗的那些材料。电导率的一个量度是西门子(Siemens)每米(S/m)。通常，导电材料是电导率大于近似地104S/m(例如，至少105S/m或至少106S/m)的一种材料。材料的电导率有时可可随温度而变化。除非另外规定，否则材料的电导率是在室温下测量的。
如本文中所使用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述”可包含复数指示物。在一些实施例的描述中，组件提供于另一组件“上”或“之上”可涵盖前一组件直接在后一组件上(例如，与后一组件物理接触)的情况，以及一或多个中间组件位于前一组件与后一组件之间的情况。
虽然已参考本发明的特定实施例描述并说明本发明，但是这些描述和说明并不限制本发明。所属领域的技术人员可清晰地理解，在不脱离如由所附权利要求书定义的本发明的真实精神和范围的情况下，可进行各种改变，且可在实施例内取代等效组件。图示可能未必按比例绘制。归因于制造过程中的变量等等，本发明中的艺术再现与实际设备之间可能存在区别。可能存在未特别说明的本发明的其它实施例。应将本说明书和图式视为说明性而非限制性的。可进行修改，以使特定情形、材料、物质组成、方法或过程适宜于本发明的目标、精神和范围。所有此类修改都意图在此所附权利要求书的范围内。虽然已参考按特定次序执行的特定操作描述本文中所公开的方法，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中具体指示，否则操作的次序和分组并非本发明的限制。

Claims (20)

1.一种半导体装置封装，其包括：
载体，其具有第一表面和与所述第一表面相对的第二表面；
导电柱，其安置在所述载体的所述第二表面上；以及
第一封装，其安置在所述载体的所述第二表面上并且覆盖所述导电柱的至少一部分，
其中所述导电柱具有不均匀的宽度。
2.根据权利要求1所述的半导体装置封装，其中
所述导电柱具有面向所述载体的第一表面和与所述第一表面相对的第二表面；以及
所述第一表面的宽度小于所述第二表面的宽度。
3.根据权利要求1所述的半导体装置封装，其中
所述导电柱具有面向所述载体的第一表面和与所述第一表面相对的第二表面；以及
所述第一表面的宽度大于所述第二表面的宽度。
4.根据权利要求1所述的半导体装置封装，其中
所述导电柱具有面向所述载体的第一表面和与所述第一表面相对的第二表面；
所述导电柱具有在从所述导电柱的所述第一表面朝向所述导电柱的所述第二表面的方向上锐化的第一部分以及在从所述导电柱的所述第二表面朝向所述导电柱的所述第一表面的方向上锐化的第二部分。
5.根据权利要求4所述的半导体装置封装，其中
所述导电柱的所述第一部分在所述导电柱的中间部分处或邻近于所述导电柱的中间部分连接到所述导电柱的所述第二部分；
所述导电柱的所述第一表面的宽度与所述导电柱的所述第二表面的宽度基本上相同；以及
所述导电柱的所述第一表面或所述第二表面的宽度大于所述导电柱的所述第一部分和所述第二部分的接头部分的宽度。
6.根据权利要求4所述的半导体装置封装，其中所述导电柱的所述第一部分连接到所述导电柱的所述第二部分，并且所述第一部分与所述第二部分之间的交接面更接近于所述导电柱的所述第一表面。
7.根据权利要求1所述的半导体装置封装，其中
所述导电柱具有面向所述载体的第一表面和与所述第一表面相对的第二表面；
所述导电柱具有从所述导电柱的所述第一表面朝向所述导电柱的所述第二表面朝内倾斜的第一横向表面以及从所述导电柱的所述第二表面朝向所述导电柱的所述第一表面朝内倾斜的第二横向表面；以及
所述第一横向表面在所述导电柱的中间部分处或邻近于所述导电柱的中间部分连接到所述第二表面。
8.根据权利要求7所述的半导体装置封装，其中所述第一横向表面和所述第二横向表面具有弯曲表面。
9.根据权利要求1所述的半导体装置封装，其中
所述导电柱具有面向所述载体的第一表面和与所述第一表面相对的第二表面；
所述导电柱具有从所述导电柱的所述第一表面朝向所述导电柱的所述第二表面朝外倾斜的第一横向表面以及从所述导电柱的所述第二表面朝向所述导电柱的所述第一表面朝外倾斜的第二横向表面；以及
所述第一横向表面在所述导电柱的中间部分处或邻近于所述导电柱的中间部分连接到所述第二横向表面。
10.根据权利要求9所述的半导体装置封装，其中所述导电柱的所述第一横向表面和所述第二横向表面的接头部分的宽度大于所述导电柱的所述第一表面或所述第二表面的宽度20％到50％。
11.根据权利要求1所述的半导体装置封装，其进一步包括安置在所述载体的所述第二表面上并且由所述第一封装主体覆盖的第一电子组件。
12.根据权利要求1所述的半导体装置封装，其进一步包括：
第二电子组件，其安置在所述载体的所述第一表面上；以及
第二封装主体，其安置在所述载体的所述第一表面上并且覆盖所述第二电子组件。
13.一种半导体装置封装，其包括：
载体，其具有第一表面和与所述第一表面相对的第二表面；
导电柱，其安置在所述载体的所述第二表面上，所述导电柱具有面向所述载体的第一表面、与所述第一表面相对的第二表面以及在所述导电柱的所述第一表面与所述第二表面之间延伸的第一横向表面；以及
第一封装，其安置在所述载体的所述第二表面上并且覆盖所述导电柱的至少一部分，所述第一封装主体具有面向所述载体的第一表面和与所述第一表面相对的第二表面，
其中所述导电柱的所述第一横向表面并不垂直于所述第一封装主体的所述第一表面。
14.根据权利要求13所述的半导体装置封装，其中所述第一横向表面从所述导电柱的所述第一表面朝向所述导电柱的所述第二表面朝内倾斜。
15.根据权利要求13所述的半导体装置封装，其中所述第一横向表面从所述导电柱的所述第一表面朝向所述导电柱的所述第二表面朝外倾斜。
16.根据权利要求3所述的半导体装置封装，其中所述导电柱进一步包含在所述导电柱的所述第一横向表面与所述第二表面之间延伸的第二横向表面，并且所述第二横向表面并不垂直于所述第一封装主体的所述第二表面。
17.根据权利要求16所述的半导体装置封装，其中
所述第一横向表面从所述导电柱的所述第一表面朝向所述导电柱的所述第二表面朝内倾斜；
所述第二横向表面从所述导电柱的所述第二表面朝向所述导电柱的所述第一表面朝内倾斜；以及
所述第一横向表面和所述第二横向表面在所述导电柱的中间部分处或邻近于所述导电柱的中间部分连接。
18.根据权利要求17所述的半导体装置封装，其中所述第一横向表面和所述第二横向表面具有弯曲表面。
19.根据权利要求16所述的半导体装置封装，其中
所述第一横向表面从所述导电柱的所述第一表面朝向所述导电柱的所述第二表面朝外倾斜；
所述第二横向表面从所述导电柱的所述第二表面朝向所述导电柱的所述第一表面朝外倾斜；以及
所述第一横向表面和所述第二横向表面在所述导电柱的中间部分处或邻近于所述导电柱的中间部分连接。
20.根据权利要求13所述的半导体装置封装，其进一步包括安置在所述载体的所述第二表面上并且由所述第一封装主体覆盖的第一电子组件。
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