CN111463180A - 一种芯片引线连接方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 claims abstract description 22
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- 238000004528 spin coating Methods 0.000 claims description 3
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 14
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- 238000005259 measurement Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
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Abstract
本发明提供了一种芯片引线连接方法，包括：步骤S1、在芯片的电极面制作整面绝缘层；步骤S2、在所述绝缘层上位于芯片的外接点和引线框架的连接点处，分别制作过孔；步骤S3、在所述绝缘层上制作导电线路，通过所述过孔将芯片的外接点和引线框架的连接点对应连接导通。本发明的导电线路沿着绝缘层的表面进行制作，相比传统的将金线的两端分别焊接到芯片的外接点和引线框架的连接点上，没有金线孤高、金球厚度等工艺参数控制要求，制作过程更加简单。
Description
技术领域
本发明属于芯片加工技术领域，尤其涉及一种芯片引线连接方法。
背景技术
芯片(chip),或称集成电路(integrated circuit，缩写IC)，是指内含集成电路的硅片，体积很小，是手机，计算机或其他电子设备的重要功能组件。芯片前段工艺(FOL，Front of Line)中，引线焊接(W/B，Wire Bonding)是封装工艺中最为关键的一道工序，具体如图1和图2所示，是采用高纯金线1A通过焊接的方式将芯片的外接点2A(Pad)与引线框架的连接点3A(Lead)进行连接导通。
但是该工艺过程中的质量控制因子众多且复杂，需要管控好金线的颈部和尾部拉力(Wire Pull、Stitch Pull)、金线孤高(Wire Loop)，金球厚度(Ball Thickness)等等。因此，现有技术还有待发展。
发明内容
本发明所要解决的技术问题在于提供一种芯片引线连接方法，旨在现有的芯片引线焊接连接方法质量控制因子众多且复杂的问题。
为解决上述技术问题，本发明是这样实现的，一种芯片引线连接方法，包括：
步骤S1、在芯片的电极面制作整面绝缘层；
步骤S2、在所述绝缘层上位于芯片的外接点和引线框架的连接点处，分别制作过孔；
步骤S3、在所述绝缘层上制作导电线路，通过所述过孔将芯片的外接点和引线框架的连接点对应连接导通。
进一步地，所述步骤S3中，所述导电线路为银浆线路或金属线路。
进一步地，所述步骤S3中，所述银浆线路的制作过程包括：
步骤S311、在所述绝缘层上制作整面银浆；
步骤S312、采用激光切割工艺将所述整面银浆切割为银浆线路。
进一步地，所述步骤S311包括：在所述绝缘层上丝网印刷或旋涂银浆，然后固化。
进一步地，所述步骤S312中，所述激光切割工艺中采用的设备为紫外纳秒激光器。
进一步地，所述步骤S312包括：
将切割线路图导入到紫外纳秒激光器设备；
调试光路、激光光斑和加工参数；
将所述步骤S311制作的半成品按照所述切割线路图进行激光切割，芯片引线连接完成。
进一步地，所述激光光斑的尺寸为8-12μm。
进一步地，所述加工参数设置为：两次发射激光的时间间隔为10-200KHz，切割速度为50-2000mm/s。
进一步地，所述步骤S3中，所述金属线路的制作过程包括：
步骤S321、在所述绝缘层上制作整面金属层；
步骤S322、采用湿法蚀刻工艺将所述整面金属层蚀刻为金属线路。
本发明与现有技术相比，有益效果在于：本发明的导电线路沿着绝缘层的表面进行制作，相比传统的将金线的两端分别焊接到芯片的外接点和引线框架的连接点上，没有金线孤高、金球厚度等工艺参数控制要求，制作过程更加简单。
附图说明
图1是现有技术芯片引线连接后的俯视图。
图2是现有技术芯片引线连接后的侧视图。
图3是本发明中芯片表面制作绝缘层后的侧视图。
图4是本发明中绝缘层打过孔后的侧视图。
图5是本发明中绝缘层表面制作导电线路层后的侧视图。
图6是本发明中银浆层被激光切割后的效果图。
图7是本发明中银浆层被激光切割后的银浆线缝的尺寸测量图。
图8是本发明中银浆线与Pad的位置关系图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明提供了一种如下的芯片引线连接方法的实施例，包括：
步骤S1、在芯片的电极面制作整面绝缘层。
具体地，可以通过丝网印刷、旋涂或者蒸镀的方式，在芯片的电极面制作绝缘层4，如图3所示，绝缘层4将芯片的外接点2(Pad)与引线框架的连接点3(Lead)全部覆盖。
步骤S2、在所述绝缘层上位于芯片的外接点和引线框架的连接点处，分别制作过孔。
具体地，如图4所示，可以通过激光进行加工，在绝缘层4上打过孔，过孔5A使芯片的外接点2裸露出部分，过孔5B使引线框架的连接点3裸露出部分，以便对相应的连接点进行连接。
步骤S3、在所述绝缘层上制作导电线路，通过所述过孔将芯片的外接点和引线框架的连接点对应连接导通。
由于芯片的外接点2和引线框架的连接点3均有裸露出来，可以直接在绝缘层4上制作导电线路对对应的连接点进行连接。导电线路可以是银浆线路或铜、金等金属线路。本发明的导电线路沿着绝缘层4的表面进行制作，相比传统的将金线的两端分别焊接到芯片的外接点2和引线框架的连接点3上，没有金线孤高、金球厚度等工艺参数控制要求，制作过程更加简单。
当采用金属线路进行连接时，可以通过蒸镀(例如磁控溅射)工艺在绝缘层4上制作整面金属层6，如图5所示，然后采用湿法蚀刻工艺进行蚀刻，具体的，可以按照设计的导电线路在金属层6上印刷耐蚀刻层，然后采用蚀刻液对进行蚀刻，受耐蚀刻层保护的线路得以保留，其余部分被蚀刻掉，最后再去除耐蚀刻层，得到金属线路。
当采用银浆线路进行连接时，可以通过丝网印刷或旋涂的方式，在绝缘层4上制作整面银浆，然后进行光固化或热固化。再采用激光切割工艺将整面银浆切割为银浆线路。本发明优选采用紫外纳秒激光器进行加工，可以控制加工精度至±10μm。具体的，首先将切割线路图导入到紫外纳秒激光器设备中，调试好光路、激光光斑、加工参数和精密加工平台精度，将准备好的芯片产品水平放置于精密加工平台上。开启激光设备，装好镜头，出光并调整镜头到芯片的距离，将激光焦点的位置调至底材上表面，利用激光设备的短脉宽、小能量、高频率对固化银浆表面持续作用。在激光作用的过程中，底材在瞬间高温下融化，形成线路，达到连接导通Pad和Lead的目的，激光切割形成的银浆线路效果图如图6所示。随后可以进行芯片封装的后续工艺。其中，激光光斑和加工参数可按照如下表格进行设置。
表1激光加工参数
| 光斑尺寸 | Q频(KHz) | 切割速度(mm/s) | 加工精度 |
| 10um | 10-200 | 50-2000 | +/-10um |
相较于采用传统引线焊接工艺，本发明实施例采用激光加工芯片银浆层的方式可以达到更高的精度，效果如图7所示，加工的银浆线路之间的线缝宽为10um，整体加工精度+/-10um，而传统工艺一般只能达到50um，从图8可以看出，若偏移超过10um会有露出银浆下面的金属Pad的风险。此外，本发明还可以使芯片的厚度做到更薄，加工效率更高，加工过程更环保。
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型，这些均应包含在本发明的保护范围之内。
Claims (9)
1.一种芯片引线连接方法，其特征在于，包括：
步骤S1、在芯片的电极面制作整面绝缘层；
步骤S2、在所述绝缘层上位于芯片的外接点和引线框架的连接点处，分别制作过孔；
步骤S3、在所述绝缘层上制作导电线路，通过所述过孔将芯片的外接点和引线框架的连接点对应连接导通。
2.如权利要求1所述的芯片引线连接方法，其特征在于，所述步骤S3中，所述导电线路为银浆线路或金属线路。
3.如权利要求2所述的芯片引线连接方法，其特征在于，所述步骤S3中，所述银浆线路的制作过程包括：
步骤S311、在所述绝缘层上制作整面银浆；
步骤S312、采用激光切割工艺将所述整面银浆切割为银浆线路。
4.如权利要求3所述的芯片引线连接方法，其特征在于，所述步骤S311包括：在所述绝缘层上丝网印刷或旋涂银浆，然后固化。
5.如权利要求3所述的芯片引线连接方法，其特征在于，所述步骤S312中，所述激光切割工艺中采用的设备为紫外纳秒激光器。
6.如权利要求5所述的芯片引线连接方法，其特征在于，所述步骤S312包括：
将切割线路图导入到紫外纳秒激光器设备；
调试光路、激光光斑和加工参数；
将所述步骤S311制作的半成品按照所述切割线路图进行激光切割，芯片引线连接完成。
7.如权利要求6所述的芯片引线连接方法，其特征在于，所述激光光斑的尺寸为8-12μm。
8.如权利要求6所述的芯片引线连接方法，其特征在于，所述加工参数设置为：两次发射激光的时间间隔为10-200KHz，切割速度为50-2000mm/s。
9.如权利要求2所述的芯片引线连接方法，其特征在于，所述步骤S3中，所述金属线路的制作过程包括：
步骤S321、在所述绝缘层上制作整面金属层；
步骤S322、采用湿法蚀刻工艺将所述整面金属层蚀刻为金属线路。
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| CN (1) | CN111463180A (zh) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6426241B1 (en) * | 1999-11-12 | 2002-07-30 | International Business Machines Corporation | Method for forming three-dimensional circuitization and circuits formed |
| CN107759106A (zh) * | 2017-09-27 | 2018-03-06 | 广东星弛光电科技有限公司 | 一种手机电容式触摸屏盖板玻璃的制造方法 |
| CN109698177A (zh) * | 2017-10-20 | 2019-04-30 | 日月光半导体制造股份有限公司 | 半导体装置封装及其制造方法 |
-
2020
- 2020-03-27 CN CN202010227536.2A patent/CN111463180A/zh active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6426241B1 (en) * | 1999-11-12 | 2002-07-30 | International Business Machines Corporation | Method for forming three-dimensional circuitization and circuits formed |
| CN107759106A (zh) * | 2017-09-27 | 2018-03-06 | 广东星弛光电科技有限公司 | 一种手机电容式触摸屏盖板玻璃的制造方法 |
| CN109698177A (zh) * | 2017-10-20 | 2019-04-30 | 日月光半导体制造股份有限公司 | 半导体装置封装及其制造方法 |
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