CN101256966A - 半导体器件及制备方法 - Google Patents

半导体器件及制备方法 Download PDF

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Publication number
CN101256966A
CN101256966A CNA2007101967962A CN200710196796A CN101256966A CN 101256966 A CN101256966 A CN 101256966A CN A2007101967962 A CNA2007101967962 A CN A2007101967962A CN 200710196796 A CN200710196796 A CN 200710196796A CN 101256966 A CN101256966 A CN 101256966A
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lead frame
semiconductor device
semiconductor chip
lead
chip
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CN101256966B (zh
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杰·A·尤德
乔斯弗·K·弗蒂
詹姆斯·P·莱特曼
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Abstract

一种包括两个堆叠的半导体芯片的半导体器件及制备方法。具有包括引线框导线和腔的有效区域的引线框装配至诸如胶带的载体材料。包括装配至载体结构并封装在模压复合物中的第一半导体芯片的封装的半导体芯片装配在胶带上。第二半导体芯片装配至封装的半导体芯片。第二半导体芯片上的接合焊盘电连接至引线框、装配有第一半导体芯片的载体结构，或两者。模压复合物在第二半导体芯片、引线框的一部分以及封装的半导体芯片周围形成。胶带被除去且引线框被分割以形成多芯片封装。

Description

半导体器件及制备方法
技术领域
本发明大体涉及半导体器件封装，以及更具体地，涉及包括多于一个半导体芯片或封装的半导体器件。
背景技术
一般，在设计和制备半导体器件产品时，半导体器件制造商考虑诸如尺寸、重量、功率消耗以及功能性的标准。增加半导体器件的功能性一般增加了它们的尺寸、重量及功率消耗。增加功能性同时限制其他设计标准的降低的一种方法使基于不同的技术的器件集成在单个封装中。该混合芯片方法包括在诸如多层印制电路板或引线框的基底上布置两个或更多裸露的半导体芯片。接着利用盖或密封材料覆盖基底和半导体芯片以形成多芯片模块(Multi-chip Module，“MCM”)。例如，一个半导体芯片可以为驱动晶体管，而另一个半导体芯片可以为模拟电压调节器开关。该方法的一个缺陷是，驱动晶体管可以使用能够承载大电流的引线接合(wire bond)，例如铝或铝合金，而模拟电压调节器可以使用更适于快速信号传输和低衰减的引线接合，例如金或金合金。这两种引线接合很难利用混合芯片来制备。
制备MCM的另一种方法是在印制电路板基底上设置模制的或封装的半导体芯片以及在印制电路板基底的另一部分上设置裸露芯片。这项技术的缺点是，在印制电路板基底上制造适于引线接合至裸露半导体芯片的信号径迹(signal trace)以及将封装的半导体芯片的引线框导线焊接至印制电路板的复杂性和成本。
因此，有一种MCM和用于制备包括至少一个裸露半导体芯片的MCM的方法是有利的。制备有成本效益的MCM是进一步有利的。
附图说明
结合附图，从以下详细说明的阅读中可以更好地理解本发明，其中相似的参考符号表示相似的元件，且其中：
图1为根据本发明的实施例的在制备期间的半导体器件的俯视图；
图2为图1的半导体器件的一部分的仰视图；
图3为沿图1的截线3-3截取的半导体器件的横截面视图；
图4为在制备的后期阶段期间图1的半导体器件的俯视图；
图5为分割(singulation)之后图4的半导体器件的仰视图；
图6为根据本发明的另一实施例的在制备期间的半导体器件的俯视图；
图7为沿图6的截线7-7截取的半导体器件的横截面视图；
图8为分割之后图7的半导体器件的横截面视图；
图9为根据本发明的另一实施例的在制备期间的半导体器件的俯视图；
图10为沿图9的截线10-10截取的半导体器件的横截面视图；
图11为在制备的后期阶段期间图9的半导体器件的俯视图；
图12为分割之后图11的半导体器件的仰视图；
图13为根据本发明的另一实施例的在制备期间的半导体器件的俯视图；
图14为沿图13的截线14-14截取的半导体器件的横截面视图；
图15为在制备的后期阶段期间图14的半导体器件的俯视图；
图16为分割之后图15的半导体器件的仰视图；
图17为根据本发明的另一实施例的在制备期间的半导体器件的俯视图；
图18为沿图17的截线18-18截取的半导体器件的横截面视图；
图19为分割之后图18的半导体器件的仰视图；
图20为根据本发明的另一实施例的在制备期间的半导体器件的俯视图；
图21为沿图20的截线21-21截取的半导体器件的横截面视图；
图22为封装和分割之后图21的半导体器件的横截面视图；
图23为根据本发明的另一实施例的在制备期间的半导体器件的俯视图；
图24为在制备的后期阶段期间图22的半导体器件的俯视图；
图25为封装之后沿图24的截线25-25截取的半导体器件的横截面视图；
图26为封装之后图25的半导体器件的横截面视图；
图27为根据本发明的另一实施例的在制备期间的半导体器件的俯视图；以及
图28为沿图27的截线28-28截取的半导体器件的横截面视图。
具体实施方式
一般，本发明提供包括多个半导体芯片的半导体器件以及用于制备半导体器件的方法。根据本发明的实施例，具有至少一个开口的引线框装配至诸如模制带(mold tape)的粘接材料(adhesive material)。开口使一部分粘接材料暴露。封装的半导体器件装配至被开口暴露的那部分粘接材料。封装的半导体器件还被称为封装的半导体芯片。裸露半导体芯片接着连接至封装的半导体器件。引线接合在裸露半导体芯片上的接合焊盘(bond pad)和引线框导线之间形成。单个引线接合可以在接合焊盘和引线框导线之间形成，或者多个接合焊盘可以利用多个引线接合连接至单个引线框导线。换句话说，引线接合从一个接合焊盘延伸至引线框导线，以及引线接合从不同的接合焊盘延伸至引线框导线。
根据另一实施例，两个裸露半导体芯片连接至半导体器件。裸露半导体芯片上的接合焊盘被引线接合至相应的引线框导线。
根据另一实施例，裸露半导体芯片上的一个或更多接合焊盘被引线接合至从封装的半导体器件延伸的导线。使裸露半导体芯片装配至封装的半导体芯片降低了传统的裸露芯片堆叠平台通常有的机械堆叠应力。此外，对引线接合的损害被减少，因为半导体芯片中的一个已经封装在模压复合物(mold compound)中。将一个或更多半导体芯片装配至封装的半导体器件还排除了使用先进的“低弯曲度(lowloop)”引线接合设计的需要。
图1为根据本发明的实施例的在制备期间的半导体器件10的俯视图。在图1中所示的是装配在胶带14上的引线框12。引线框12具有上表面16、具有相对侧20和22以及相对侧24和26的腔18。多个引线框导线28侧26延伸，而多个引线框导线30自侧24延伸。应该理解，构成多个引线框导线28的引线框导线的数量和构成多个引线框导线30的引线框导线的数量不是本发明的限制。还应该理解，引线框12包括形成半导体器件的多个有效区域，并且图1示出了两个有效区域15。用于胶带14的适当材料为包括聚酰亚胺、聚酯等的模制带。作为样例，胶带14为Bron Tape CT908模制带，而引线框12为具有范围自大约5密耳(大约127微米)至大约25密耳(大约635微米)的厚度的铜。用于形成引线框导线的技术对于本领域技术人员而言是众所周知的。
模制半导体器件装配在被腔18暴露的胶带14的部分上。更具体地，半导体器件34装配在每个有效区域15中的引线框导线28和30之间。根据一个实施例，半导体器件34主要由装配在引线框上的半导体芯片组成，其中半导体芯片和一部分引线框封装在模压复合物中。半导体器件34还被称为封装的半导体芯片，以及其上装配有半导体芯片的引线框还被称为载体(support)。封装半导体芯片的模压复合物还被称为保护性材料。简要参照图1和2，半导体器件34具有上表面36、下表面38、源极导体40、栅极导体42以及漏极导体44和46。应该注意，图1示出了半导体器件34的俯视图，而图2示出了半导体器件34的仰视图。
参照图1和3，半导体芯片50通过芯片连接材料56连接至每个模制半导体器件34。每个半导体芯片50具有上表面或有效表面52以及下表面或配合表面54。应该注意，图3为沿图1的截线3-3截取的横截面视图。多个接合焊盘58设置在有效表面52上。配合表面54设置在芯片连接材料56中，芯片连接材料56设置在模制半导体器件34的表面36上。用于芯片连接材料56的适当材料包括环氧树脂、聚酰亚胺、热塑性涂胶(thermoplastic paste)、热塑性薄膜等。芯片连接材料56可以配制在模制半导体器件34的表面上或者以薄片覆盖至半导体芯片50的后部并进行B阶段硬化。
接合引线60和61分别将引线框导线28和30连接至相应的接合焊盘58。优选地，单个接合引线将引线框导线连接至相应的接合焊盘。然而，这不是本发明的限制。例如，一个或更多接合焊盘可以连接至单个引线框导线。接合引线还被称为引线接合。对于本领域的技术人员而言，用于形成接合引线的技术是众所周知的。
如参照图1所描述的，引线框12一般包括自其形成半导体器件的多个有效区域。在形成接合引线之后，每个有效区域封装在保护半导体器件免受物理和环境应力的模压复合物中。接着从引线框中分割单独的半导体器件。图4为模制半导体器件34、半导体芯片50、接合焊盘58、接合引线60和61以及引线框导线28和30的部分由模压复合物64封装之后半导体器件10的俯视图。这些元件可以利用传递模塑(transfer molding)技术封装在模压复合物64中。在被模压复合物64封装之后，除去胶带14。因为胶带14在被模压复合物64封装之后被除去，它还被称为临时载体。应该注意，封装在模压复合物64内的半导体器件34、引线接合60和61、引线框导线28和30的部分被示为虚线，因为在视图中它们被模压复合物64隐藏。
图5为分割之后半导体器件10的俯视图。图5中所示为模压复合物64的下表面66、引线框导线28和30以及包括源极导体40、栅极导体42以及漏极导体44和46的模制半导体器件34的下表面38。因此，半导体器件10包括在单个半导体封装中的两个半导体芯片。半导体器件10还被称为单个堆叠结构，因为单个半导体芯片装配在模制半导体器件34上。
图6为根据本发明的另一实施例的在制备期间的半导体器件100的俯视图。图6中所示为装配在胶带14上的引线框12。参照图1描述了引线框12和胶带14。模制半导体器件102装配在被腔18暴露的一部分胶带14上。更具体地，模制半导体器件102装配在引线框导线28和30之间。模制半导体器件102可以包括装配在引线框上的半导体芯片，其中半导体芯片和引线框的一部分封装在模压复合物中。与模制半导体器件34类似，模制半导体器件102包括上表面104、下表面106(图7中示出)以及通过下表面106暴露的导体。
参照图6和7，具有上表面或有效表面112和下表面或配合表面114的半导体芯片110通过芯片连接材料56连接至模制半导体器件102。应该注意，图7为沿图6的截线7-7截取的横截面视图。多个接合焊盘118设置在有效表面112上。配合表面114设置在芯片连接材料56中，芯片连接材料56设置在模制半导体器件102的表面104上。此外，具有上表面或有效表面122和下表面或配合表面124的半导体芯片120通过芯片连接材料56连接至模制半导体器件102。多个接合焊盘128设置在有效表面122上。配合表面124设置在芯片连接材料56中，芯片连接材料56设置在模制半导体器件102的表面104上。接着将芯片连接材料56硬化。半导体器件100被称为双堆叠结构，因为两个半导体芯片装配在封装的半导体器件102上。
接合引线130和132将引线框导线28和30分别连接至半导体芯片110上的相应的接合焊盘118，并且接合引线134和136将引线框导线28和30分别连接至半导体芯片120上的相应的接合焊盘128。优选地，单个接合引线将引线框导线连接至相应的接合焊盘。然而，这不是本发明的限制。例如，一个或更多接合焊盘可以连接至单个引线框导线。接合引线还被称为引线接合。对于本领域的技术人员而言，形成接合线的技术是众所周知的。
如8为封装在模压复合物140中及分割之后的半导体器件100的横截面视图。
图9为根据本发明的另一实施例的在制备期间的半导体器件150的俯视图。图9中所示为装配在胶带14上的引线框152。引线框152具有上表面154和具有相对侧158和180以及相对侧162和164的腔156。多个引线框导线166自侧158延伸，而多个引线框导线168自侧160延伸。应该理解，包括多个引线框导线166的引线框导线的数量和包括多个引线框导线168的引线框导线的数量不是本发明的限制。象引线框12一样，引线框152包括形成半导体器件的多个有效区域。图9示出了两个有效区域。作为样例，引线框152为具有范围从大约5密耳(大约127微米)至大约25密耳(大约635微米)的厚度的铜。对于本领域的技术人员而言，形成引线框导线的技术是众所周知的。
模制半导体器件170装配在被腔156暴露的胶带14的一部分上。更具体地，半导体器件170装配在引线框导线166和168之间。根据一个实施例，模制半导体器件170包括装配在引线框上的半导体芯片，其中半导体芯片和一部分引线框封装在模压复合物174中。引线框导线176、177和178自模压复合物174的一侧延伸，而引线框导线179自模压复合物174的相对侧延伸。引线框导线179具有孔或开口181。
具有上表面或有效表面182和下表面或配合表面184的半导体芯片180通过芯片连接材料56连接至模制半导体器件170。应该注意，图10为沿图9的截线10-10截取的横截面视图。多个接合焊盘186设置在有效表面182上。配合表面184设置在芯片连接材料56中，芯片连接材料56设置在模制半导体器件170的上表面上。接着硬化芯片连接材料56。
接合引线188将引线框导线166连接至相应的接合焊盘186，并且接合引线189将引线框导线168连接至相应的接合焊盘186。接合引线189A和189B将两个接合焊盘连接至单个引线框导线168，以及接合引线189C和189D将两个接合焊盘连接至单个引线框导线168。
象引线框12一样，引线框152一般包括形成半导体器件的多个有效区域。在形成接合引线之后，将每个有效区域封装在保护半导体器件免受物理和环境应力的模压复合物中。接着从引线框中分割单独的半导体器件。图11为模制半导体器件170、半导体芯片180、接合焊盘58、接合引线188、189和189A-D以及一部分引线框导线166和168由模压复合物190封装之后半导体器件150的俯视图。这些器件可以利用注塑成型技术封装在模压复合物190中。应该注意，封装在模压复合物190中的半导体器件170的一部分、引线框导线186和188的一部分以及引线接合189、189A和189B以虚线示出，因为它们被模压复合物190自视图中隐藏。
图12为分割之后半导体器件150的仰视图。图12中所示为模压复合物190的下表面192、引线框导线176、177、178和179以及半导体器件170的下表面194。下表面192配合下表面194形成半导体器件150的下表面。引线框导线176起源极导体的作用，引线框导线177起栅极导体的作用，而引线框导线178和179起漏极导体的作用。图12进一步示出了引线框导线166和168。
图13为根据本发明的另一实施例的在制备期间的半导体器件200的俯视图。图13中所示为装配在胶带14上的引线框202。引线框202具有上表面204、具有相对侧208和210以及相对侧212和214的腔206。多个引线框导线216自侧208延伸，而多个引线框导线218自侧210延伸。应该理解，由多个引线框导线216组成的引线框导线的数量和由多个引线框导线218组成的引线框导线的数量不是本发明的限制。还应该理解，引线框202包括形成半导体器件的多个有效区域205。作为样例，引线框202为具有范围自大约5密耳(大约127微米)至大约25密耳(大约635微米)的厚度的铜。对于本领域的技术人员而言，形成引线框导线的技术是众所周知的。
模制半导体器件220装配在被腔206暴露的胶带14的一部分上。更具体地，半导体器件202装配在引线框导线216和218之间。根据一个实施例，模制半导体器件220包括装配在引线框上的半导体芯片，其中半导体芯片和引线框的一部分封装在模压复合物222中。引线框导线224、226和228自模压复合物222的一侧延伸。
具有上表面或有效表面232和下表面或配合表面234的半导体芯片230通过芯片连接材料56连接至模制半导体器件220。应该注意，图14为沿图13的截线14-14截取的横截面视图。多个接合焊盘236设置在有效表面232上。配合表面234设置在芯片连接材料56中，芯片连接材料56设置在模制半导体器件230的上表面231上。接着硬化芯片连接材料56。
接合引线240将引线框导线216连接至相应的接合焊盘236，而接合引线242将引线框导线218连接至相应的接合焊盘236。优选地，单个接合引线将引线框导线连接至相应的接合焊盘。然而，这不是本发明的限制。例如，多个接合引线可以将两个或更多接合焊盘连接至单个引线框导线。此外，接合引线243将接合焊盘236连接至引线框导线224。
象引线框12一样，引线框202一般包括形成半导体器件的多个有效区域。在形成接合引线之后，每个有效区域封装在保护半导体器件免受物理和环境应力的模压复合物中。图15为模制半导体器件220、半导体芯片230、接合焊盘236、以及接合引线240、242和243、以及一部分引线框导线224、226和228由模压复合物244封装之后半导体器件200的俯视图。这些器件可以利用注塑成型技术封装在模压复合物244中。应该注意，封装在模压复合物244中的半导体器件230的一部分、一部分引线导线216、218、224、226和228以及引线接合240和242以虚线示出，因为它们被模压复合物244自视图中隐藏。
图16为分割之后半导体器件200的仰视图。图16中所示的为模制半导体器件220的下表面、引线框导线216、224、226和228以及模压复合物244的下表面。引线框导线224起源极导体的作用，引线框导线226起栅极导体的作用，而引线框导线228起漏极导体的作用。
图17为根据本发明的另一实施例的在制备期间的半导体器件250的俯视图。图17中所示的为装配在胶带14上的引线框252。引线框252具有包括相对侧254和256的开口以及具有相对侧258和260的开口。引线框252具有分别自侧254和256延伸的引线框导线262和264以及自侧254延伸至侧256的引线框导线结构266、268和270。此外，引线框252包括通过接头(tab)276连接至侧254以及通过接头278连接至侧256的半导体器件连接结构或挡板(flag)274。参照图1描述了诸如引线框252的引线框及其制备。模制半导体器件280利用芯片连接材料例如芯片连接材料56或焊剂连接(couple)至每个挡板274。每个模制半导体器件280还连接至引线框导线结构266、268以及270。模制半导体器件280可以主要由装配在引线框上的半导体芯片组成，其中半导体芯片和一部分引线框封装在模压复合物中。象模制半导体器件34一样，模制半导体器件280包括上表面282、下表面284和通过下表面284暴露的导体。
参照图17、18和19，具有上表面或有效表面290和下表面或配合表面292的半导体芯片288通过芯片连接材料56连接至模制半导体器件280。应该注意，图18为沿图17的截线18-18截取的横截面视图。多个接合焊盘294设置在有效表面290上。配合表面292设置在芯片连接材料56中，芯片连接材料56设置在模制半导体器件280的表面282上。接着硬化芯片连接材料56。
接合引线296和298将引线框262和264分别连接至相应的接合焊盘294。接合引线300将相应的接合焊盘294连接至引线框导线结构268。优选地，单个接合引线将引线框导线连接至相应的接合焊盘。然而，这不是本发明的限制。例如，一个或更多接合焊盘可以连接至单个引线框导线。接合引线还被称为引线接合。对本领域的技术人员而言，形成接合引线的技术是众所周知的。
装配有模制半导体器件280和半导体芯片288的引线框252设置在传递模塑装置中，并由模压复合物302封装以形成具有上表面304和下表面306的封装的半导体器件。
将胶带14除去，并将具有模制半导体器件280、半导体芯片288以及模压复合物302的引线框252分割成模制半导体器件250。图19为分割的模制半导体器件250的仰视图，并示出了在去除胶带14并分割之后剩余的挡板274、下表面306、一部分引线框导线262和264以及一部分引线框导线结构266、268和270。
图20和21分别示出了根据本发明的另一实施例的在制备期间的半导体器件320的俯视图和横截面视图。图20所示的为装配在胶带14上的引线框322。引线框322具有上表面324、具有相对侧328和330以及相对侧332和334的腔326。多个引线框导线336自侧328延伸，而多个引线框导线338自侧330延伸。腔326暴露一部分胶带14。应该理解，由多个引线框导线336组成的引线框导线的数量和由引线框导线338组成的引线框导线的数量不是本发明的限制。还应该理解，引线框322包括形成半导体器件的多个有效区域。优选地，有效区域是完全相同的并且可以由单个参考符号标注。为了清楚起见，有效区域通过参考符号340A和340B来识别。作为样例，引线框320为具有范围从大约5密耳(大约127微米)至大约25密耳(大约635微米)的厚度的铜。对于本领域的技术人员而言，形成引线框导线的技术是众所周知的。
半导体器件342装配在被腔326暴露的胶带14的每个部分上。为了进一步示出引线框322的结构，半导体器件未在有效区域340A中示出。半导体器件342包括通过芯片连接材料348连接至源极导线346以及通过芯片连接材料348连接至栅极导线350的半导体芯片。电传导芯片352通过热传导环氧树脂354连接至半导体芯片并连接至漏极导线356。可选地，传导芯片352可以通过焊剂连接至半导体芯片。具有设置在上表面上的接合焊盘362的半导体芯片360通过芯片连接材料364、焊剂或环氧树脂连接至芯片352。
接合引线365将引线框导线335连接至相应的接合焊盘362，而接合引线366将引线框导线338连接至相应的接合焊盘362。优选地，单个接合引线将引线框导线连接至相应的接合焊盘。然而，这不是本发明的限制。例如，多个接合引线可以将两个或更多接合焊盘连接至单个引线框导线。此外，接合引线368将接合焊盘362连接至栅极导线350。
象引线框12一样，引线框322一般包括形成半导体器件的多个有效区域。在形成接合引线之后，每个有效区域封装在保护半导体器件免受物理和环境应力的模压复合物中。接着将单独的半导体器件从引线框中分割。图22为半导体器件342和引线框322的一部分由模压复合物370封装并被分割之后的半导体器件320的横截面视图。此外，胶带14被去除。这些元件可以利用传递模塑技术封装在模压复合物370中。
图23为根据本发明的另一实施例的在制备期间的半导体器件400的俯视图。图23中示出的为装配在胶带14上的引线框402。引线框402具有上表面404、腔406和407、挡板408、多个引线框导线410和多个引线框导线412。腔406和407暴露一部分胶带14。挡板408由接头409连接至引线框402。应该理解，由多个引线框导线410和412组成的引线框导线的数量不是本发明的限制。引线框导线416延伸进腔406中，以及引线框导线417延伸进腔407中。每个引线框导线416具有接头部分418和接合部分(bonding portion)420。类似地，每个引线框导线417具有接头部分422和接合部分424。引线框402包括接近开407的栅极导线411。还应该理解，引线框402包括形成半导体器件的多个有效区域。优选地，有效区域是完全相同的并且可以被单个参考符号标注。然而，为了清楚起见，有效区域由参考符号414A和414B识别。作为样例，引线框402为具有范围从大约5密耳(大约127微米)至大约25密耳(大约635微米)的厚度的铜。对于本领域的技术人员而言，形成引线框导线的技术是众所周知的。
半导体芯片426连接至有效区域414B中的挡板408。半导体芯片426的源极导体经由电热传导环氧树脂429连接至挡板408，而栅极导体通过电热传导环氧树脂429(图25中所示)连接至栅极导线411。为了进一步示出引线框402的结构，未在有效区域414A中示出半导体器件。半导体芯片426的源极区域通过电热传导环氧树脂427连接至挡板408，而半导体芯片426的栅极区域通过电热传导环氧树脂427连接至栅极导线411。
现在参照图24，电传导芯片428通过热传导环氧树脂427(图25中所示)连接至半导体芯片426的漏极区域以及连接至引线框导线416和417。可选地，电传导芯片428通过焊剂连接至半导体芯片426。具有设置在上表面上的接合焊盘432的半导体芯片430通过芯片连接材料433连接至传导芯片428。应该注意，图24示出了装配至有效区域414A和414B的半导体器件426、芯片428和半导体芯片430。
接合引线434将引线框导线410连接至相应的接合焊盘432，而接合引线436将引线框导线412连接至相应的接合焊盘432。优选地，单个接合引线将引线框导线连接至相应的接合焊盘。然而，这不是本发明的限制。例如，多个接合引线可以将两个或更多的接合焊盘连接至单个引线框导线。此外，接合引线438将接合焊盘432连接至栅极导线411。
象引线框12一样，引线框402一般包括形成半导体器件的多个有效区域。在形成接合引线之后，每个有效区域封装在保护半导体器件免受物理和环境应力的模压复合物中。接着从引线框中分割单独的半导体器件。图25为源极导线408、栅极导线411、漏极导线420和424、半导体器件426、传导芯片428以及接合引线434、436和438由模压复合物440封装之后半导体器件400的横截面视图。图26为去除胶带14并分割引线框402之后的半导体器件400的横截面视图。
图27为根据本发明的另一实施例的在制备期间的半导体器件450的俯视图。图27所示为装配在胶带14上的引线框12。参照图1描述了引线框12和胶带14。应该进一步理解，引线框12包括形成半导体器件的多个有效区域，但是图27示出了单个有效区域15。
模制半导体器件装配在被腔18暴露的胶带14的一部分上。更具体地，半导体器件34装配在有效区域15中的引线框导线28和30之间。根据一个实施例，半导体器件34主要由装配在引线框上的半导体芯片组成，其中半导体芯片和一部分引线框封装在模压复合物中。参照图1描述了半导体器件34。
参照图27和28，半导体结构452通过环氧树脂454连接至模制半导体器件34。半导体结构452包括具有诸如传导轨迹458的传导轨迹的电路板456。半导体结构452还包括通过芯片连接材料461装配至电路板456的半导体芯片460。接合焊盘462A和462B在电路板456上形成，而接合焊盘464和464A在半导体芯片460上形成。在电路板456上形成的接合焊盘的数量和在半导体芯片460上形成的接合焊盘的数量不是本发明的限制。设置在半导体芯片460上的接合焊盘464A通过引线接合466连接至设置在电路板456上的接合焊盘462A。接合焊盘462A通过传导轨迹458连接至接合焊盘462B，而接合焊盘462B通过引线接合468连接至一个或更多引线框导线28。接合焊盘465通过引线接合470连接至相应的引线框导线28，而接合焊盘464通过引线接合472连接至相应的引线框导线30。半导体芯片460、电路板456以及半导体器件34封装在模压复合物470中，胶带14被去除，且引线框12被切割。将半导体芯片装配至电路板以及将电路板装配至半导体器件的优点是，不用重新设计半导体芯片就可以重新分配引脚输出(pin out)。
至目前为止，应认识到，一种包括两个或更多半导体芯片的半导体器件以及用于制备半导体器件的方法被提供。将半导体芯片装配至封装的半导体器件的优点是，可以在组合进半导体器件封装之前电测试封装的半导体器件。此外，将半导体芯片装配至封装的半导体器件排除了芯片堆叠问题，例如低弯曲度引线接合、在悬挂的半导体芯片上的引线接合、板中引线接合等。根据本发明的封装半导体芯片允许将控制器半导体芯片和驱动器半导体芯片设置在具有场效应晶体管的单个封装中。另一优点是，根据本发明的实施例允许使用封装设备的输入-输出(I/O)导线作为多芯片模块的外部I/O，从而排除对具有增加的轨迹的内部电路板的需要。
尽管这里公开了某些优选实施例和方法，显然根据上述公开，对于本领域的技术人员而言，在不背离本发明的精神和范围的情况下可以对这样的实施例和方法进行变更和修改。例如，可以将一个或更多被动半导体器件装配至封装的半导体芯片。意图是本发明应该仅仅被限制到所附权利要求和可适用的法律的法规和法则所要求的程度。

Claims (10)

1.一种用于制备半导体器件的方法，其包括：
提供封装的半导体芯片，所述封装的半导体芯片包括装配至第一载体的第一半导体芯片以及覆盖所述第一半导体芯片的一部分和所述第一载体的一部分的第一保护性材料；以及
将第二半导体芯片装配至所述封装的半导体芯片。
2.根据权利要求1所述的方法，其中，所述第二半导体芯片具有一个或更多接合焊盘，以及还包括：
将所述一个或更多接合焊盘中的第一接合焊盘电连接至所述第一载体；
提供第二载体；以及
将所述一个或更多接合焊盘中的第二接合焊盘连接至所述第二载体。
3.根据权利要求1所述的方法，其中，所述第二半导体芯片具有一个或更多接合焊盘，以及还包括提供第二载体，且其中：
提供所述封装的半导体芯片的步骤还包括：
将所述封装的半导体芯片装配至临时载体；以及
将所述第二载体装配至所述临时载体。
4.根据权利要求3所述的方法，其中，所述临时载体为聚合材料。
5.一种用于制备半导体器件的方法，其包括：
提供具有第一接触结构的第一半导体芯片和覆盖所述第一半导体芯片的一部分的材料；
将第二半导体芯片装配在所述材料上；以及
在所述第二半导体芯片的一部分和所述保护性材料上形成保护性材料。
6.根据权利要求5所述的方法，还包括：
将第一引线框装配至包括聚合材料的临时载体；以及
将所述第一半导体芯片和覆盖所述第一半导体芯片的所述部分的所述材料装配至所述临时载体。
7.根据权利要求6的方法，还包括将第三半导体芯片装配至所述材料，以及其中，形成所述保护性材料的步骤包括：在所述第三半导体芯片的一部分上形成所述保护性材料以及将所述第三半导体芯片连接至所述第一引线框的第三部分。
8.根据权利要求7所述的方法，其中，将第二半导体芯片装配在所述材料上的步骤包括：
将所述半导体芯片装配至基底；以及
将所述基底装配至覆盖所述第一半导体芯片的所述材料。
9.根据权利要求5所述的方法，还包括：
将所述第二半导体芯片连接至第一引线框的第一部分；以及
将所述第一接触结构连接至所述第一引线框的第二部分。
10.一种半导体器件，其包括：
具有第一接触结构的第一半导体芯片和覆盖所述第一半导体芯片的一部分的材料；
第二半导体芯片，其在所述材料上；以及
保护性材料，其在所述第二半导体芯片的一部分以及所述保护性材料之上。
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