CN107409469B - 单层压体电流隔离体组件 - Google Patents
单层压体电流隔离体组件 Download PDFInfo
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Abstract
公开了一种隔离体组件。该组件包括本质上由均质材料块和一组电接触体构成的层压体。第一裸芯耦接到层压体的表面。隔离屏障完全位于层压体的表面上方。第二裸芯耦接到层压体的表面。第二裸芯通过隔离屏障与第一裸芯电流隔离。第二裸芯经由隔离屏障和层压体上的导电迹线与第一裸芯可操作地通信。第一裸芯、第二裸芯、层压体以及隔离屏障全部包含在组件封装体内。
Description
相关申请的交叉引用
本申请要求2015年2月13日提交的申请号为14/621,752的美国非临时申请的优先权,其全部内容为全部目的通过引用并入本文。
背景技术
在特定的情况下,电子装置需要在仍处于可操作通信的同时,被彼此电流隔离。例如,需要通信地耦接以交换信息同时在不同功率体制下运行的装置需要被隔离,以使得较低功率装置不会因暴露于其不能承受的电流等级而损坏。作为另一示例,使用具有第一接地电平(例如电池的负端子)的电源来操作的外围装置可能需要与使用具有分开的接地电平(例如主墙插座的接地端子)的主机装置通信。在这些情况下,当装置耦接在一起时,需要隔离以防止电流从一个“接地”流向另一个。作为另一个示例,隔离可以保护装置免受分开的装置中的故障状况的不利影响。在所有这些情况下,装置可以被电流隔离,同时仍经由电、光学、机械或声学手段进行通信。
在设计隔离体时必须考虑的主要考虑因素之一是隔离体承受大功率级同时保持期望的隔离度的能力。因此,传统的隔离体已经使用了分离桨(split paddle)组合过程,其中隔离体的每侧由完全分开的基板支撑。两个分开的基板进而通过到总体引线框架的封装体工艺结合在一起,总体引线框架通常也支持到总体电路的接触体。隔离装置本身形成在分开的桨之间,并且在保持它们的电流隔离的同时在两者之间提供通信通道。
图1示出了增强隔离体的功率阻断能力的另一种途径,在隔离装置连接到的基板中形成隔离装置本身。图1示出了包括基板101的隔离体组件100,基板101中已经经由电介质层103和导电迹线104形成了两个电容器102。分开的隔离装置105可以在位置106和107处连接到导电迹线,并且从而经由两个电容器102被隔离。由于隔离装置形成在基板中并且电介质103的击穿电压比空气大得多,所以隔离体的电压阻断能力相应地增加。分开的装置105可以包含用于编码要通过电容器102发送的信号的收发器电路,并且可以经由导电迹线108连接到外部隔离的电路。
发明内容
在一个实施例中,提供了隔离体组件。实施例包括实质上由均质材料块和电接触体组构成的层压体。实施例还包括耦接到层压体的表面的第一裸芯。实施例还包括完全位于层压体的表面上方的隔离屏障。实施例还包括耦接到层压体的第二裸芯。第二裸芯通过隔离屏障与第一裸芯电流隔离。第二裸芯经由隔离屏障和层压体上的导电迹线与第一裸芯可操作地通信。第一裸芯、第二裸芯、层压体以及隔离屏障全部包含在组件封装体内。
在另一实施例中,提供了一种设备。实施例包括层压体。实施例还包括经由第一裸芯的端子连接到层压体上的第一导电迹线的第一裸芯。实施例还包括经由第二裸芯的端子连接到层压体上的第二导电迹线的第二裸芯。实施例还包括隔离屏障,隔离屏障包括连接到第一导电迹线和第二导电迹线的离散电容器,并完全位于层压体上方。第一裸芯通过隔离屏障与第二裸芯电流隔离。隔离屏障、第一导电迹线以及第二导电迹线形成从第一裸芯到第二裸芯的信号传输通路。
在另一实施例中,提供了封装体的隔离体组件。实施例包括层压体。实施例还包括接合到层压体的第一封装集成电路。实施例还包括接合到层压体的第二封装集成电路。实施例还包括接合到层压体的离散表面安装电容器。实施例还包括在层压体上形成的导电迹线的组。导电迹线和离散表面安装电容器形成第一封装集成电路和第二封装集成电路之间的通信通道。离散表面安装电容器将第一封装集成电路与第二封装集成电路电流隔离。
附图说明
图1示出了根据当前工艺的隔离体组件的截面。
图2A和2B示出了各自根据本发明的实施例的两个隔离体组件的截面。
图3A和3B示出了各自根据本发明的实施例的使用离散隔离装置的隔离体组件的截面。
图4示出了根据本发明的实施例的使用共形涂层和包封剂的隔离体组件的截面。
图5示出了根据本发明的实施例的使用注射塑模的隔离体组件的截面。
图6A和6B示出了各自根据本发明的实施例的两个隔离体组件的截面,裸芯附接到层压体的任一侧。
图7示出了根据本发明的实施例的封装隔离体组件。
图8示出了形成参考图2-7所公开的隔离体组件的方法的流程图。
图9示出了封装体参考图2-7所公开的隔离体组件的方法的流程图。
具体实施方式
现在详细参考所公开的发明的实施例,附图中示出了其一个或多个示例。每个示例以解释本技术的方式提供,而不是作为本技术的限制。事实上,对于本领域的技术人员来说,对本技术做修改和变化而不脱离其精神和范围是显而易见的。例如,作为一个实施例的部分所示出或描述的特征可以与另一实施例使用,以产生更进一步的实施例。因此,本主题旨在覆盖所附权利要求和它们的等效的范围内的所有这样的修改和变化。
可以参考图2-7描述单层压体上形成的各种多裸芯隔离体组件。可以参考图8和图9描述这些组件的制造方法。隔离体组件可以用于传输电流隔离的数据或功率信号。例如,隔离体组件可充当用于根据通用串行总线(USB)标准来传输信息的一个或多个通道的隔离体。可以通过包括隔离装置的隔离屏障提供电流隔离,隔离装置也连接到层压体。多裸芯隔离体组件的多个裸芯可以通过隔离装置隔离,并含有跨隔离屏障通信的收发器(transceiver)。收发器可以是中继器(repeater)或转接器(redriver),其接收来自外部源的信号,并且将它们准备用于跨隔离屏障的传输,或其接收来自隔离屏障的信号并且准备它们,以传输出隔离体组件。隔离体组件可以为外部系统提供隔离功能,外部系统独立地耦接到隔离屏障任意侧上的多裸芯组件中的不同裸芯。外部系统可以经由多裸芯封装体上的导电端子耦接到隔离体,导电端子为例如含有组件的封装体上的引脚、线或焊料凸块。
多裸芯隔离体组件的多个裸芯耦接到的层压体可以是均质材料的块。例如,层压体可以是非导电材料的块,其具有其表面上形成的多层导电迹线、插入体、蚀刻的布线板或微型印刷电路板(mini-PCB)。层压体还可以包含用于与隔离体组件外部的系统连接的电接触体,系统为例如组件对其提供隔离的系统。下面描述的途径允许使用具有多个裸芯的单层压体,同时仍提供高度的电流隔离,并且由此还在比使用分裂桨组件的途径更廉价和较不复杂的方式的情况下为整体组件提供了给定程度的稳定性。
组件可以包含多个隔离的通道和多个隔离屏障。通道可以各自是双向的或单向的。根据组件意图处理的信号的复杂度及被选择用于跨所选的隔离屏障传输信号的编码方案,可能需要不同数目的通道。例如,为了符合USB 3.0,可能需要包括两个通道的四个单向隔离屏障,而如果相同的隔离装置旨在向后兼容USB 2.0标准,则可能需要完全独立的通道。
隔离体需要为其隔离的设备提供电流隔离,并且还需要在装置之间快速传输信息。理想地,隔离体不会对隔离的信号引入任何延迟或延时。为了减少延时,被隔离的装置应该紧密靠近隔离设备放置,以最小化隔离的设备之间发送的信号的传输时间。然而,最小化两个隔离的装置之间的距离可能增加隔离的装置的端子之间击穿的可能性。如参考图1所述,隔离体组件的导电隔离的部件之间的接近的冲突影响的一个解决方案是在基板中形成隔离装置。然而,符合该技术的途径需要经由通常用于单片集成电路结构的制造工艺或涉及复杂异质基板的接合的系统级工艺来生产定制基板。这些解决方案族都不具吸引力,因为它们在不同程度上既昂贵又在技术上复杂。因此,使用隔离屏障完全位于层压体的表面上方的途径是有益的。
在下面参考图3-5和图9描述了隔离体组件的不同封装技术。这些技术包含使用共形涂层、电介质包封剂、注射塑模以及对层压体上的系统级设计形成保护层的其他方法。这些途径还允许将被隔离的装置的紧密接近的放置,因为保护层具有比空气更高的击穿电压,位于其间,并且将被隔离的装置的导电部分彼此隔离,并且起到增加隔离体组件的阻断能力的作用。
就可以添加到整体隔离体组件的附加部件而言,基本层压体的使用允许更高的灵活度。组件可以包括同一层压体上形成的附加无源装置和/或其他裸芯。附加裸芯可以对整体组件提供定时、配置控制、过程修剪或通用逻辑功能。它们还可以包括用于功率调节的线性稳压器。附加裸芯也可以串联连接在上述外部系统与隔离装置之间,使得它们中的一些经由隔离装置通信,但也被隔离装置电流隔离。这些附加裸芯还可以包含容纳诸如电容器或电感的实际隔离装置的无源装置,或用于其他目的的无源装置,例如电源去耦电容器。
图2A和2B示出了两个隔离体组件的截面200和210。所示出的组件提供上面关于在单层压体上的被隔离的设备的潜在接近度所指出的一些好处。截面200包含耦接到层压体203的多个裸芯201和202。截面210包含耦接到层压体213的多个裸芯211和212。由截面200和210示出的两个组件都包括被隔离的裸芯中形成的隔离装置204和214。注意,虽然图2A和图2B示出了每个裸芯中的隔离装置,但是隔离屏障可以完全位于单个裸芯内。无论如何,多个裸芯201和202通过隔离屏障彼此电流隔离,而同时多个裸芯201和202经由隔离屏障和它们的层压体上的导电迹线206和216彼此可操作地通信。此途径的优点是,隔离装置经由裸芯的封装而绝缘,使得隔离体组件具有更高的击穿电压。此外,方法可以与不包含层压体本身中形成的无源装置的基本层压体使用。因此,此途径提供了更高隔离阻断的优点,而不需要复杂和昂贵的基板。
隔离的裸芯中形成的隔离装置可以是能够与集成电路封装的任何类型的隔离体。如图所示,隔离装置204和214是电容器。然而,隔离装置也可以是光耦合器、变压器或任何其他感应(inductive)电路。在隔离装置是电容器的情况下,可以使用芯片上氧化物电介质层、生产线后端工艺(back-end-of-line process)期间形成的重新分布层(RDL)或其组合来将电容器构建到裸芯中。例如,电容器可以是形成在裸芯中形成的集成电路中的布线层中或上方形成的金属-绝缘体-金属(MIM)电容器。电容器还可以部分地形成在裸芯中且部分地形成在层压体的表面上。例如,电容器的板可以形成在裸芯的布线层或重新分布层中,而第二板由层压体上的导电迹线形成。如果将裸芯倒装芯片地接合到层压体,则电容器可以有效地包括裸芯和层压体之间的电接触体之一。换句话说,电容器可以替代焊料凸块或其他接触体,否则焊料凸块或其他接触体将会把裸芯连接到层压体。
可以使用各种技术将包括隔离体的多个裸芯耦接到层压体。例如,裸芯201和202被倒装芯片地连接到层压体203的表面上形成的导电迹线206和207,而裸芯211和212经由引线键合体连接到层压体213的表面上形成的导电迹线216和217。在任一情况下,导电迹线可以是沉积在层压体的表面上或者沉积在层压体的被蚀刻的区域中的导电线路。导电线路可以是诸如铜或钨的金属。图2A和图2B所示,裸芯201和202经由倒装芯片封装体和与裸芯上的顶侧接触连接的焊料凸块205而连接到层压体,而裸芯211和212经由引线键合体215连接到层压体。倒装芯片连接提供的优点在于,裸芯的内部电路与导电迹线之间的连接物理上较短,这允许跨隔离屏障的信号的更快传输。引线键合体提供的优点在于,当隔离装置使用电感时,引线键合体本身可以通过其自身的固有阻抗充当隔离装置的部分。值得注意的是,尽管截面200和210中的组件被示为限于单个连接类型,但是在某些途径中,层压体上的多个裸芯的子集将被倒装芯片地连接,而其余的使用引线键合体连接。
图3A和图3B示出了隔离体组件300在制造工艺的两个阶段的截面301和302。隔离体组件300包含倒装芯片地连接到层压体305的多个裸芯303和304。隔离体组件还包含以离散表面安装电容器306形式形成在层压体的表面上方的隔离装置。在其他所有都相同的情况下,使用离散装置使得隔离体组件300比参考图2A和图2B所讨论的隔离体组件的类型更廉价,因为离散隔离装置可以现成获得以用于任何设计中,而不是为了特定目的而定制。此外,使用离散器件相对于参考图1所讨论的隔离体组件的类型提供了一些益处,因为在基板上方形成隔离设备消除了以在基板本身中形成隔离装置为目的而蚀刻到基板中或进行其他工艺来制造独特的基板的需要。
虽然根据本文所述的方法可以使用层压体中的隔离装置,例如通孔电容器和层压体中形成的其他无源装置,但是这种方法不能用于薄层压体。薄层压体是重要的,因为它们限制了封装组件所需的封装材料的量。此外,根据定义,薄层压体具有较少的材料,并且因此比较厚的层压材料廉价。通常,限制封装体宽度的部件选择在这方面提供了益处,使得使用诸如表面安装电容器的薄电容器和其他薄的离散装置可以根据本文所述的方法来有利地使用。
参考截面200、210以及301所描述的途径可以提供足够的隔离,并且不需要进一步的处理。这些装置可以被留下为暴露于环境空气,或者它们可以以将装置留下为暴露于封装体内的气穴的方式而被封装。然而,隔离体组件的电压承受能力由暴露于跨隔离体的高电压差的最小气隙决定。空气的击穿抗性在干燥空气中典型地为1kV/mm。因此,如截面301中的层压体表面上方的离散装置的使用,以及如截面200和210中的将导电线暴露于开放的空气可能会穿过层压体上方的空气产生有害地薄弱的击穿路径。这个问题可以通过进一步的工艺步骤来解决,其引入了系统级封装体以切断薄弱击穿路径。一种这样的途径是在封装体中形成真空穴,或通过引入诸如氩气的惰性气体来形成高压区域,但是这些封装方法可能是昂贵的。下面描述的附加封装途径起到解决该设计考虑的作用,允许将被隔离的装置放置在更靠近的附近,并允许使用层压体表面上方的离散隔离装置。
一种可以提高隔离体组件的击穿抗性的封装体途径是在隔离的装置之上引入共形涂层。截面302包含共形涂层307,可以在形成隔离屏障并且将裸芯附接到层压体之后将共形涂层307形成在隔离体组件上。共形涂层可以是可被制成至少临时地符合其所施加的表面的具有高击穿电压的任何材料。潜在的材料包括:塑料喷涂、丙烯酸树脂(acrylic)、环氧树脂、聚氨酯硅氧烷、聚对二甲苯或无定形含氟聚合物。因此,共形涂层307覆盖第一裸芯303和第二裸芯304且还覆盖离散电容器306。共形涂层有利地具有高介电系数,并且起到将组件的导电端子彼此隔离以防止系统的短路和灾难性击穿的作用。此共形涂层是允许离散器件的使用和将裸芯放置于紧密的附近并同时保持期望的击穿抗性水平的方法的示例。
虽然参考包括电容器的隔离装置讨论了隔离体组件300,但组件可以可替代地使用上述的任意隔离装置,包含光耦合器、变压器以及其他电感装置。使用参考截面302所描述的途径将允许使用任何种类的离散隔离装置,只要它们能够被共形涂层覆盖。此限制将有效地覆盖被出售用于与PCB或其他系统级层压体使用的任何开放市场的离散装置。然而,诸如由层压体上的导电线路形成的电感或薄表面安装电容器的低档装置对此途径将是最有益的,因为共形涂层的厚度可能是就整体组件的加工时间和成本而言的限制因素。
一种可以提高隔离体组件击穿抗性的封装方法是在层压体表面上的多个裸芯和隔离装置之上引入包封剂。包封剂可以形成隔离体组件的封装体的外表面。组件还可以包含外表面,外表面包括层压体的背侧,或者包封剂可以覆盖组件的两侧。图4示出了隔离体组件截面400,其包括与离散表面安装电容器404一起形成在层压体403上的第一裸芯401和第二裸芯402。还示出了形成在第一裸芯、第二裸芯以及隔离屏障之上的包封剂405。包封剂是电介质包封剂,例如:塑料包封剂、树脂、环氧树脂、硅包封剂或聚酰亚胺。
包封剂可以直接设置在基板和被隔离的装置上。然而,如图所示,包封剂405已经沉积共形涂层406的顶部上,共形涂层406在形成包封剂405之前形成。用于形成包封剂405的材料通常比用于形成共形涂层406的材料廉价,并且能够以与等量的共形涂层406相同的价格点提供更大程度的稳定性和免受外力的保护。事实上,用于共形涂层406的某些材料不能用作装置的外部封装,因为它们不能充分地粘合到用作永久包封剂的组件。同时,用于形成包封剂405的特定材料(例如塑料包封剂)可能产生空隙407或包含导电颗粒,其可能损害隔离体的击穿强度。因此,在一些途径中,在装置之上形成共形涂层406然后在共形涂层之上形成包封剂405是有利的。共形涂层和电介质包封剂的组合将允许隔离体装置和被隔离的装置被放置于紧密的附近。例如,共形涂层和电介质包封剂将允许第一裸芯401的端子被放置在离散电容器404的可替代端子的1.25毫米内,同时仍然保持大于1kV的阻断能力。
虽然参考图4讨论的途径包括使用离散电容器作为隔离体组件的隔离装置,但是途径不限于此。使用共形涂层和/或包封剂还可以有益地应用于其中隔离装置全部或部分地形成在裸芯本身中的途径,以及使用任意上述隔离装置的方法。实际上,无论是否使用离散器件,通过引入具有比空气更高的击穿强度的共形涂层,隔离体组件的击穿电压仍然很可能提高。
可以提高隔离体组件的击穿电压的另一种封装途径是在整个组件上引入空间填充电介质材料以包封整个封装体。这种途径的示例是在整个组件上引入塑料注射塑模。这种方法将比上述其他封装方法更昂贵,但是在共形涂层或较廉价的包封剂不可选的情况下将是有用的。此外,由于注射塑模提供了隔离屏障的任意侧的所有暴露部件的完全覆盖,注射塑模将允许把隔离装置和裸芯放置于接近的附近。例如,注射塑模将允许第一裸芯的端子放置在离散电容器的可替代端子的1毫米内,同时仍保持大于1kV的阻断能力。
可以参考图5描述使用注射塑模来封装的隔离体组件的示例。图5中的截面500包括全部位于基板504的表面上方的第一裸芯501、第二裸芯502以及一个或多个隔离装置503。截面500与截面210相似,在于通过隔离体的通信是通过使用将裸芯耦接到层压体上的导电迹线的引线键合体来实现的。然而,截面500中的隔离体组件不是暴露于环境空气,而是被注射塑模505覆盖。接合类型和封装方法的这种组合是合适的,因为共形涂层可能难以粘合到将裸芯连接到层压体的引线键合体上。然而,空间填充电介质材料将能够隔离引线键合体,并且作为整体为隔离体组件另外提供附加的稳定性和隔离。
图6示出了隔离体组件的两个截面600和610,其各自包括全部耦接到层压体604的第一裸芯601、第二裸芯602以及隔离装置603。如图所示,隔离装置603再次各自形成在层压体604的表面上,使得可以使用基本层压体,并且层压体也可以是薄层压体。然而,两个截面中的裸芯形成在层压体604的不同表面上。如图所示,隔离装置在截面600中形成在裸芯中并且在截面610中形成在层压体上。无论隔离装置位于何处,将裸芯放置在层压体的任意侧上有助于提高隔离体组件的击穿电压,因为存在隔离屏障的任意侧之间的开放空气通路的完全缺乏。实际上,层压体通常会从延伸到页面之外并且向左和向右到比所示更大得多的程度,使得围绕层压体边缘的击穿路径将有效地对设备的性能具有可忽略的影响。尽管这些截面绘制为使用电容器隔离体,但是可以使用任意上述的隔离装置。
图7从前侧和后侧示出了封装隔离体组件700。在这种情况下,组件已经被放置在DFN封装体中,其在隔离体的每一侧的封装体中具有6个金属接触体701。组件形成在微型PCB 702上,并且包括由离散表面安装电容器705隔离的第一裸芯703和第二裸芯704。所有上述部件都被共形涂层706和塑料包封剂707覆盖,其已经在附图中移除,以露出第一裸芯703、离散表面安装电容器705以及第二裸芯704。在微型PCB的裸露部分中且由包封剂下的虚线示出了裸芯和电容器之间的导电迹线。注意,封装体含有第一裸芯703和第二裸芯704之间的另一表面安装电容器,其未以虚线示出,因为封装体未从其上方移除。还要注意,封装体包括完全分开的隔离通道708,其类似于使用第一裸芯703和第二裸芯704的通道。在所示途径中,隔离体与USB 3.0标准兼容,所示出的通道中的每一个都是单向的,以允许通过隔离体的双向通信。通过添加附加的装置和接触体,可以将组件修改为向后兼容USB 2.0。
图8示出了可用于形成上述隔离体组件的方法的流程图800。流程图800开始于步骤801,其中第一裸芯和第二裸芯接合到单层压体。可以使用倒装芯片接合、引线键合或者将最终在裸芯和隔离屏障两者的端子之间提供电连接并且在裸芯和层压体之间提供物理连接以确保裸芯在其余的制造过程中保持就位的任意其他方法来进行该接合过程。流程图可以替代地以步骤802继续或以之开始,其中隔离装置接合到层压体。在使用此步骤的途径中,隔离装置是与裸芯分开的离散装置。在这些途径中,步骤801和802可以按任意顺序进行。在其中在裸芯中形成隔离装置的其他途径中,可以完全跳过步骤802。
流程图800以步骤803继续,其中可选地形成引线键合体。引线键合体可以将裸芯上的端子连接到层压体上的导电迹线。可替代地,引线键合体可以将裸芯上的端子连接到离散隔离装置上的端子。在最后的替代方案中,引线键合体可以充当电感,并且从而充当隔离装置本身。在其中裸芯被倒装芯片地连接到基板的途径中,可以保留此步骤,以将离散隔离装置的端子连接到层压体上的导电迹线,或者如果隔离装置也不需要引线键合,则可以完全跳过该步骤。
图9示出了封装上述隔离体组件的方法的流程图900。流程图900开始于可选的步骤901,其中在基板上形成的裸芯和隔离装置上形成共形涂层,例如塑料喷涂或溅射沉积的电介质。然后流程图900以步骤902继续,其中在裸芯和隔离装置上形成包封剂。包封剂可以是充当隔离体组件的整体封装体的外表面的塑料包封剂。
流程图900可以可选地以步骤903开始,其中在隔离体组件之上形成塑模。塑模可以是注入的电介质材料,其在注入之后膨胀,以将隔离体组件的所有暴露部分完全隔离。可以将额外的封装材料施加于注射塑模,以形成封装体(例如金属或陶瓷封装体)的外壳,或者注入的材料本身可以充当封装体的外表面。
流程图900终止于步骤904,其中外部接触体形成到隔离体组件。接触体可以是焊料凸块、从引脚框架延伸的铜或金引脚、用于引线键合体接触体的垫的阵列或能够允许隔离体组件与外部系统通信的任何其他外部接触体。在直接耦接到隔离屏障的裸芯特别复杂的情况下,或者在层压体包含具有编码功能的附加裸芯的情况下,外部接触体可能更复杂,例如USB端子或其他总线接口。
虽然已经关于本发明的具体实施例详细描述了本说明书,但是应当理解,本领域技术人员一经理解上述内容可以容易地想到这些实施例的改变、变化和等同。在不脱离本发明的精神和范围的情况下,本领域技术人员可以实施本发明的这些和其他修改和变化,本发明的精神和范围在所附权利要求中更特别地阐述。
Claims (3)
1.一种隔离体组件,包括:
层压体,所述层压体本质上由均质材料块和一组电接触体构成;
第一裸芯,所述第一裸芯耦接到所述层压体的表面;
隔离屏障,所述隔离屏障完全位于所述层压体的所述表面上方;以及
第二裸芯,所述第二裸芯耦接到所述层压体,其中所述第二裸芯通过所述隔离屏障与所述第一裸芯电流隔离,并且其中所述第二裸芯经由所述隔离屏障和所述层压体上的导电迹线而与所述第一裸芯可操作地通信;
电容器,所述电容器具有第一板和第二板;
其中所述第一裸芯、所述第二裸芯、所述层压体以及所述隔离屏障全部包含在组件封装体内;
其中所述第一板在所述第一裸芯中形成;并且
其中所述隔离体屏障包括所述电容器。
2.如权利要求1所述的隔离体组件,还包括:
电介质包封剂,所述电介质包封剂将所述第一裸芯与所述第二裸芯隔离;以及
共形涂层,所述共形涂层覆盖所述第一裸芯和所述第二裸芯;
其中所述共形涂层和所述电介质包封剂将所述第一裸芯与所述第二裸芯隔离;并且
其中所述电介质包封剂覆盖所述共形涂层。
3.如权利要求1所述的隔离体组件,还包括:
所述第二板在所述层压体上形成;
所述第一裸芯是倒装芯片裸芯;并且
所述第一裸芯经由所述第一裸芯的顶侧接触体耦接到所述层压体。
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