WO2013157285A1 - 表示装置 - Google Patents
表示装置 Download PDFInfo
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- WO2013157285A1 WO2013157285A1 PCT/JP2013/052672 JP2013052672W WO2013157285A1 WO 2013157285 A1 WO2013157285 A1 WO 2013157285A1 JP 2013052672 W JP2013052672 W JP 2013052672W WO 2013157285 A1 WO2013157285 A1 WO 2013157285A1
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- WIPO (PCT)
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- electrode
- transistor
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- pixel
- display device
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- 239000000758 substrate Substances 0.000 claims abstract description 158
- 239000003990 capacitor Substances 0.000 claims abstract description 140
- 238000005401 electroluminescence Methods 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 17
- 229920001187 thermosetting polymer Polymers 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 claims description 3
- 238000007689 inspection Methods 0.000 abstract description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 105
- 239000010408 film Substances 0.000 description 56
- 239000003566 sealing material Substances 0.000 description 54
- 238000000034 method Methods 0.000 description 26
- 241001181114 Neta Species 0.000 description 21
- 239000011159 matrix material Substances 0.000 description 19
- 230000000694 effects Effects 0.000 description 14
- 238000002347 injection Methods 0.000 description 14
- 239000007924 injection Substances 0.000 description 14
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- 239000011521 glass Substances 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 238000000016 photochemical curing Methods 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000004044 response Effects 0.000 description 5
- 239000004925 Acrylic resin Substances 0.000 description 4
- 229920000178 Acrylic resin Polymers 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000001723 curing Methods 0.000 description 4
- 239000012775 heat-sealing material Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000001934 delay Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011701 zinc Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910052800 carbon group element Inorganic materials 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000013081 microcrystal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 244000126211 Hericium coralloides Species 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000012508 resin bead Substances 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1341—Filling or closing of cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/84—Passivation; Containers; Encapsulations
- H10K50/841—Self-supporting sealing arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/80—Constructional details
- H10K59/87—Passivation; Containers; Encapsulations
- H10K59/871—Self-supporting sealing arrangements
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1306—Details
- G02F1/1309—Repairing; Testing
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
Definitions
- the present invention relates to a display device. More specifically, the present invention relates to a display device suitable for a display device including a shift register.
- An active matrix display device for example, an active matrix liquid crystal display, usually selects pixels arranged in a matrix in units of rows, and writes a voltage corresponding to display data to the selected pixels, thereby displaying an image. indicate.
- a shift register that sequentially shifts output signals (scanning signals) based on a clock signal is provided in a gate bus line driving circuit (hereinafter also referred to as a gate driver).
- the gate driver may be formed at the same time as the TFT in the pixel using a manufacturing process to form a thin film transistor (TFT) in the pixel.
- TFT thin film transistor
- a shift register included in the gate driver is also formed using amorphous silicon in order to reduce manufacturing costs.
- the gate driver may be monolithically formed on the array substrate.
- a drop injection method (ODF method) has been developed as a method of filling a liquid crystal material in a liquid crystal panel of a liquid crystal display.
- ODF method a drop injection method
- the step of bonding the two substrates and the step of enclosing the liquid crystal material between the two substrates can be performed simultaneously.
- Examples of the technology related to the monolithic formation of the gate driver include the following.
- the display panel includes a first substrate provided with a plurality of gate lines and a plurality of data lines, a second substrate facing the first substrate, and a hermetic seal that couples the first substrate and the second substrate.
- the gate driving unit includes a wiring unit that receives a plurality of signals from the outside and a circuit unit that outputs a driving signal in response to the plurality of signals, and the sealing member is cured in the wiring unit. Therefore, a display device provided with an opening that transmits light incident through the back surface of the first substrate is disclosed (see, for example, Patent Document 1).
- Patent Document 1 describes that the bonding force between the first substrate and the second substrate is improved by a sealing material.
- a drive unit including a circuit unit and a wiring unit, wherein the circuit unit includes a plurality of subordinately connected stages, outputs a drive signal in accordance with a plurality of control signals, and the wiring unit includes a plurality of externally connected stages.
- First and second signal wirings that receive control signal inputs, first connection wirings that connect the first signal wirings to the plurality of stages, and second connection wirings that connect the second signal wirings to the plurality of stages.
- a drive unit is disclosed in which the first signal wiring, the first and second connection wirings are arranged in a different layer from the second signal wiring (see, for example, Patent Document 2).
- a display substrate including a gate wiring, a driving circuit portion, a signal wiring portion, a connection wiring portion, and a contact portion, wherein the gate wiring is formed in the display region, intersects with the source wiring, and the driving circuit portion surrounds the display region. Formed in the peripheral region, outputs a gate signal to the gate wiring, and the signal wiring section is formed adjacent to the driving circuit section, extends in the extension direction of the source wiring, and transmits the driving signal.
- the portion includes one end portion that overlaps the signal wiring portion and the other end portion that is electrically connected to the drive circuit portion, and the contact portion is formed on the signal wiring portion.
- a display substrate that electrically connects a wiring portion is disclosed (for example, see Patent Document 3).
- a drive circuit composed of a plurality of drive stages and dummy stages, wherein the plurality of drive stages are connected in a subordinate manner by connecting the output terminals of each stage to the control terminals of the previous stage, and a matrix
- the switching element driving signal is sequentially output to a plurality of driving signal lines connected to the switching element formed on each pixel arranged in the form, and the dummy stage has a dummy output terminal at the last of the plurality of driving stages.
- a driving circuit connected to the control terminal of the stage and the dummy control terminal of the stage is disclosed (for example, see Patent Document 4).
- a TFT including a third lead wiring, a fourth lead wiring, a first wiring, and a second wiring is disclosed (for example, refer to Patent Document 6).
- a shift register configured by connecting unit circuits in multiple stages, the unit circuit being provided between a clock terminal and an output terminal, and an output transistor that switches whether or not to pass a clock signal according to a gate potential;
- One conduction terminal includes one or more control transistors connected to the gate of the output terminal, and the gate potential of the output transistor is the high level potential of the clock signal in a period in which the output transistor is on and the clock signal is high level.
- a shift register in which a transistor having a channel length longer than that of an output transistor is included in the control transistor (see, for example, Patent Document 7).
- a shift register formed to have a configuration in which a plurality of shift register stages are cascade-connected on a substrate, wherein the shift register stage is opposite to a gate electrode with respect to at least one of two source / drain electrodes
- the first transistor is provided with a capacitor electrode facing in the film thickness direction, and either the capacitor electrode or one of the source / drain electrodes facing the capacitor electrode is an output of the shift register stage.
- a shift register that is electrically connected to a control electrode of a transistor is disclosed (see, for example, Patent Document 8).
- Examples of techniques relating to the dropping injection method include the following.
- a TFT substrate a CF substrate disposed opposite to the TFT substrate, a sealing material sandwiched between the TFT substrate and the CF substrate and formed at the periphery of both substrates, and a liquid crystal layer interposed between the TFT substrate and the CF substrate,
- a liquid crystal display panel including a CF substrate having a light shielding layer in a peripheral portion where a sealing material is provided, and the light shielding layer having a gap in a region overlapping a wiring of a TFT substrate.
- a liquid crystal display panel comprising an active matrix substrate and a counter substrate arranged to face each other, and a liquid crystal layer provided between both substrates, wherein a display region and a non-display region around the display region are defined, In the region, the active matrix substrate is provided with a frame-shaped seal portion made of a photo-curing material having a narrow linear portion and a wider portion wider than the linear portion between the two substrates.
- a liquid crystal display panel in which light-shielding display wiring is patterned and a counter substrate is provided with a black matrix formed along the inner peripheral edge of the seal portion and having a cutout portion at a position corresponding to the wide portion Is disclosed (for example, see Patent Document 10).
- a seal inspection process for sealing between substrates facing each other is performed. More specifically, whether a seal is formed at an appropriate location, whether the seal width is sufficiently secured, the seal is not interrupted, the seal material is sufficiently cured, etc. May be inspected using other observation equipment. Further, even after product shipment, when a display defect occurs, a seal may be inspected to investigate the cause. In addition, when the width
- the shift register includes various elements such as TFTs. Among them, the size of the output transistor connected to the bus line is large. Also, the shift register typically includes a bootstrap capacitor connected to the output transistor, but the size of this bootstrap capacitor is also large. In particular, when amorphous silicon is used or when the resolution or panel size increases, the size of the output transistor and the bootstrap capacitor increases. In addition, these TFTs and capacitors usually include a light-shielding electrode and thus function as a light-shielding member.
- the counter substrate facing the array substrate generally has a black matrix (BM).
- BM black matrix
- the shift register is arranged particularly in the BM. It may be formed opposite to the region.
- the sticker may approach the display region and be disposed between the light shielding member such as BM, the output transistor, and the bootstrap capacitor. Therefore, the seal state may not be easily observed from either the array substrate side or the counter substrate side.
- the present invention has been made in view of the above-described present situation, and an object thereof is to provide a display device capable of easily performing a seal inspection.
- the inventors of the present invention have made various studies on display devices that can easily perform seal inspection, and have focused on the structure of the bootstrap capacitor. More specifically, by providing the bootstrap capacitor with a light transmitting portion, more specifically, a first notch and / or a first opening is formed in the first electrode of the bootstrap capacitor, and the bootstrap capacitor is provided. By forming a second notch and / or a second opening facing the first notch and / or the first opening in the second electrode, a light shielding member such as a BM is disposed on the counter substrate. Even if it has been done, it has been found that the state of the seal can be confirmed from the array substrate side through the translucent part, and it has been conceived that the above problem can be solved brilliantly, and the present invention has been achieved.
- an aspect of the present invention is a display device including a first substrate, a second substrate facing the first substrate, and a seal provided between the first substrate and the second substrate.
- the first substrate includes an insulating substrate, a shift register monolithically formed on the insulating substrate, and a plurality of bus lines.
- the shift register includes a plurality of unit circuits connected in multiple stages.
- Each of the unit circuits is connected to a clock terminal to which a clock signal is input, a corresponding bus line, an output terminal from which an output signal is output, one of a source and a drain is connected to the clock terminal, and the source and A transistor having the other drain connected to the output terminal (output transistor), a first terminal connected to the gate of the transistor, and a second terminal connected to the output terminal
- a capacitor bootstrap capacitor connected, the capacitor including a first electrode, an insulating layer on the first electrode, and a second electrode on the insulating layer, the plurality of unit circuits
- the first electrode is provided with a first notch and / or a first opening
- the second electrode is provided with the first notch and / or the first opening.
- a display device provided with a second notch and / or a second opening facing the opening (hereinafter also referred to as “display device according to the present invention”).
- the configuration of the display device according to the present invention is not particularly limited by other components as long as such components are essential.
- a preferred embodiment of the display device according to the present invention will be described below. Note that the following preferred embodiments may be appropriately combined with each other, and an embodiment in which the following two or more preferred embodiments are combined with each other is also one of the preferred embodiments.
- the counter substrate may or may not include a light shielding member that faces the shift register.
- inspection can be performed easily can be show
- the seal can be observed more easily than in the case where the translucent portion is not provided in the bootstrap capacitor, so that the above effect can be obtained.
- the seal may include a cured product of a photocurable material.
- the material may further have thermosetting properties.
- the sealing material can be cured more reliably by heat treatment even when an uncured portion is generated in the sealing material only by light irradiation. Can do. Therefore, the substrates can be bonded very firmly. Further, in the case of a liquid crystal display, it is possible to effectively suppress a reduction in display quality due to the sealing material component of the uncured portion.
- the transistor may be disposed in a region between the capacitor and the display region of the first substrate, and the seal may not be disposed on the transistor.
- the seal can be easily arranged so as not to overlap the output transistor. Therefore, the seal can be inspected more reliably.
- the sealing material which has photocurability it can prevent more reliably that a non-hardened part generate
- the capacitor is disposed in a region between the transistor and a display region of the first substrate, the transistor is covered with the seal, and at least a part of the capacitor is disposed under the seal. May be.
- the capacitor may further include a second insulating layer on the second electrode and a transparent electrode on the second insulating layer, and the transparent electrode may be connected to the first electrode.
- the capacity of the bootstrap capacitor can be increased, so that the frame area can be made narrower.
- the type of the bus line is not particularly limited, but the following embodiments (A) to (C) are preferable.
- the plurality of bus lines are normally connected in common to one row or one column of pixel circuits.
- the first substrate includes a plurality of pixel circuits provided in a display area, and each of the plurality of pixel circuits includes a pixel transistor and a pixel electrode connected to the pixel transistor. And each of the plurality of bus lines is connected to gates of a corresponding plurality of pixel transistors.
- This embodiment is suitable when the display device according to the present invention is applied to a liquid crystal display.
- the first substrate includes a plurality of pixel circuits provided in a display region, and each of the plurality of pixel circuits includes a pixel transistor and an electroluminescence connected to the pixel transistor.
- Each of the plurality of bus lines is connected to a gate of a corresponding plurality of pixel transistors.
- the plurality of bus lines are a first plurality of bus lines
- the first substrate includes a plurality of pixel circuits provided in a display region, and a plurality of data bus lines.
- Each of the plurality of pixel circuits includes a first pixel transistor, a second pixel transistor connected to a corresponding data bus line, and an electroluminescence (EL) connected to the first pixel transistor.
- the first plurality of bus lines are connected to the gates of the corresponding plurality of second pixel transistors, respectively.
- the transistor may include an oxide semiconductor.
- the oxide semiconductor may include indium (In), gallium (Ga), zinc (Zn), and oxygen (O).
- the display apparatus which can perform a test
- FIG. 3 is a schematic plan view of a liquid crystal panel included in the liquid crystal display of Embodiment 1.
- FIG. FIG. 2 is a schematic cross-sectional view taken along the line AB in FIG. 1.
- 3 is a schematic plan view of a liquid crystal panel included in the liquid crystal display of Embodiment 1.
- FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display according to Embodiment 1.
- FIG. 2 is a block diagram illustrating a configuration of a shift register in Embodiment 1.
- FIG. 3 is a circuit diagram of a unit circuit included in the shift register in Embodiment 1.
- FIG. 3 shows a timing chart of the shift register in Embodiment 1.
- 3 shows a timing chart of the shift register in Embodiment 1.
- FIG. 3 is a schematic plan view showing a configuration in a frame region of the liquid crystal display of Embodiment 1.
- FIG. 3 is a schematic plan view showing a configuration in a frame region of the liquid crystal display of Embodiment 1.
- FIG. 10 is a schematic cross-sectional view taken along line CD in FIG. 9.
- FIG. 10 is a schematic sectional view taken along line EF in FIG. 9.
- 3 is a schematic plan view showing a configuration in a frame region of the liquid crystal display of Embodiment 1.
- FIG. 6 is a schematic plan view of a bootstrap capacitor in the liquid crystal display according to Embodiment 2.
- FIG. It is a cross-sectional schematic diagram in the JK line
- FIG. 6 is a schematic plan view illustrating a configuration in a frame region of the liquid crystal display of Embodiment 3.
- FIG. 9 is a schematic plan view of a bootstrap capacitor in the liquid crystal displays of Embodiments 1 to 7.
- FIG. 9 is a schematic plan view of a bootstrap capacitor in the liquid crystal displays of Embodiments 1 to 7.
- FIG. 9 is a schematic plan view of a bootstrap capacitor in the liquid crystal displays of Embodiments 1 to 7.
- FIG. 10 is a circuit diagram showing a circuit configuration of unit pixels (pixels or sub-pixels) included in an active matrix type organic EL display according to Embodiment 8.
- 10 is a schematic plan view of an organic EL substrate included in an active matrix organic EL display according to Embodiment 8.
- FIG. 6 is a schematic plan view illustrating a configuration in a frame region of a liquid crystal display according to Embodiment 4.
- FIG. FIG. 23 is a schematic cross-sectional view taken along line MN in FIG.
- FIG. 10 is a schematic plan view illustrating a configuration in a frame region of a liquid crystal display according to a fifth embodiment.
- FIG. 10 is a schematic plan view illustrating a configuration in a frame region of a liquid crystal display according to a sixth embodiment.
- FIG. 26 is a schematic sectional view taken along line PQ in FIG. 25.
- FIG. 10 is a schematic plan view illustrating a configuration in a frame region of a liquid crystal display according to a seventh embodiment.
- FIG. 1 is a schematic plan view of a liquid crystal panel included in the liquid crystal display according to the first embodiment.
- FIG. 2 is a schematic cross-sectional view taken along the line AB in FIG.
- FIG. 3 is a schematic plan view of a liquid crystal panel included in the liquid crystal display according to the first embodiment.
- the liquid crystal display of the present embodiment is an active matrix drive type and transmissive liquid crystal display, and includes a liquid crystal panel 1, a backlight (not shown) disposed behind the liquid crystal panel 1, the liquid crystal panel 1, and A control unit (not shown) for driving and controlling the backlight unit and a flexible substrate (not shown) for connecting the liquid crystal panel 1 to the control unit are provided.
- the liquid crystal panel 1 includes a display unit 2 that displays an image.
- a plurality of pixels 3 are arranged in a matrix.
- Each pixel 3 may be composed of sub-pixels of a plurality of colors (for example, three colors of red, green, and blue), and FIG. 3 shows such a case.
- the liquid crystal display of this embodiment may be a monochrome liquid crystal display. In this case, it is not necessary to divide each pixel 3 into a plurality of subpixels.
- the liquid crystal panel 1 is provided between an array substrate (active matrix substrate) 10 corresponding to the first substrate, a counter substrate 50 corresponding to the second substrate and facing the array substrate 10, and the substrates 10 and 50.
- An alignment film (not shown) provided and a source driver 5 mounted on the array substrate 10 are provided.
- the liquid crystal panel 1, the array substrate 10, and the counter substrate 50 include a region (display region) 7 corresponding to the display unit 2 and a region (frame region) 8 around the display region 7.
- the source driver 5 is a source bus line driving circuit described later.
- the seal 62 is formed in the frame area 8 so as to surround the display area 7.
- the seal 62 adheres the substrates 10 and 50 to each other and seals the liquid crystal layer 61 between the substrates 10 and 50.
- the array substrate 10 is provided on the back side of the liquid crystal display, and the counter substrate 50 is provided on the viewer side.
- a polarizing plate (not shown) is attached on the surface of each substrate 10, 50 opposite to the liquid crystal layer 61. These polarizing plates are usually arranged in crossed Nicols.
- the source driver 5 is mounted by a COG (Chip On Glass) technique in a region of the array substrate 10 that does not face the counter substrate 50, that is, a region that protrudes from the counter substrate 50 (hereinafter also referred to as an overhang region).
- COG Chip On Glass
- the array substrate 10 vertically crosses the display area 7 with gate drivers 6a and 6b monolithically formed on the left and right sides of the display area 7, terminals 26, 27, 28, 29, and 30 formed in the overhang area.
- the source bus line (data signal line) 12 provided, the gate bus line (scanning signal line) 13 and the common bus line 17 provided so as to cross the display area 7, and the frame area 8 are formed respectively.
- the gate bus line 13 includes a gate bus line 13 connected to the output terminal of the left gate driver 6a and a gate bus line 13 connected to the output terminal of the right gate driver 6b, which are alternately arranged. ing.
- the gate bus line 13 corresponds to the bus line in the embodiment (A).
- a flexible substrate is mounted in a region where the terminals 26, 28, and 30 are provided (region surrounded by a thick two-dot chain line in FIG. 3).
- Each source bus line 12 is connected to the output section of the source driver 5 via a corresponding lead line 18 and terminal 27.
- Various signals and a power supply voltage are input from the control unit to the input unit of the source driver 5 through the flexible substrate, the terminal 28, the input wiring 25, and the terminal 29.
- a common signal is input to the common trunk line 16 from the control unit via the flexible substrate and the terminal 30.
- the common signal is a signal applied in common to all pixels.
- the common bus line 17 is connected to the common trunk line 16 in the frame region 8, and a common signal is applied to the common bus line 17 from the common trunk line 16.
- Gate drivers 6 a and 6 b Various signals and a power supply voltage are supplied to the gate drivers 6 a and 6 b from the control unit via the flexible substrate, the terminal 26 and the lead wire 19. Details will be described later.
- Gate drivers called gate monolithic, gate driverless, panel built-in gate driver, gate-in panel, gate-on-array, etc. can all be included in the gate drivers 6a and 6b. Instead of providing the two gate drivers 6a and 6b, only one gate driver that exhibits the same function as the two gate drivers 6a and 6b may be provided.
- the counter substrate 50 includes a transparent insulating substrate 51 such as a glass substrate, a black matrix (BM) 52 that functions as a light shielding member, and a plurality of columnar spacers (not shown).
- the BM 52 is formed so as to shield the frame area 8 and the area facing the bus line. In FIG. 2, the BM 52 is not shown in the display area 7.
- the counter substrate 50 may include a plurality of color filters (not shown). Each color filter is provided in the display area 7 and is formed so as to cover an area partitioned by the BM 52, that is, an opening of the BM 52.
- the counter substrate 50 may have an overcoat film, and the overcoat film may cover all the color filters.
- the columnar spacer is disposed in the light shielding region on the BM 52.
- the liquid crystal mode of the liquid crystal display of this embodiment is not specifically limited.
- the counter substrate 50 In a liquid crystal mode using a vertical electric field such as a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode, the counter substrate 50 has a counter electrode to which a common signal is applied, and the array substrate 10 is common.
- a common transfer electrode 14 is connected to the main wiring 16, and both electrodes are connected to each other through a conductive member.
- the conductive member include a resin mixed in the seal 62 and coated with a metal such as gold, a carbon paste, and the like.
- FIG. 4 is a block diagram illustrating a configuration of the liquid crystal display according to the first embodiment.
- FIG. 5 is a block diagram illustrating a configuration of the shift register according to the first embodiment.
- FIG. 6 is a circuit diagram of a unit circuit included in the shift register according to the first embodiment. 7 and 8 are timing charts of the shift register according to the first embodiment.
- the liquid crystal display of this embodiment includes a pixel array 71, a display control circuit 72 provided in the control unit, a source driver 5, and gate drivers 6a and 6b.
- the pixel array 71 is formed on the n gate bus lines G1 to Gn corresponding to the gate bus line 13, the m source bus lines S1 to Sm corresponding to the source bus line 12, and the pixel 3, respectively.
- n and m are integers of 2 or more, i is an integer of 1 to n, and j is an integer of 1 to m.
- the gate bus lines G1 to Gn are arranged in parallel to each other, and the source bus lines S1 to Sm are arranged in parallel to each other so as to be orthogonal to the gate bus lines G1 to Gn.
- a pixel circuit Pij is arranged near the intersection of the gate bus line Gi and the source bus line Sj.
- the (m ⁇ n) pixel circuits Pij are arranged two-dimensionally, m in the row direction and n in the column direction.
- the gate bus line Gi is connected in common to the pixel circuit Pij arranged in the i-th row
- the source bus line Sj is connected in common to the pixel circuit Pij arranged in the j-th column.
- Each pixel circuit Pij is provided with a pixel TFT 4 as a switching element and a pixel electrode 9.
- the gate of the TFT 4 is connected to the gate bus line Gi, and one of the drain and the source of the TFT 4 is The other is connected to the pixel electrode 9 while being connected to the source bus line Sj.
- the liquid crystal display of this embodiment is supplied with control signals such as a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC and an image signal DAT from the outside. Based on these signals, the display control circuit 72 outputs the clock signals CK1, CK2, and the start pulse SP1 to the gate driver 6a, and the clock signals CK3, CK4, and the start pulse SP2 to the gate driver 6b. And the control signal SC and the digital video signal DV are output to the source driver 5.
- control signals such as a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC and an image signal DAT from the outside. Based on these signals, the display control circuit 72 outputs the clock signals CK1, CK2, and the start pulse SP1 to the gate driver 6a, and the clock signals CK3, CK4, and the start pulse SP2 to the gate driver 6b.
- the control signal SC and the digital video signal DV are output to the source driver 5.
- the gate driver 6a includes a shift register 73a, and the shift register 73a includes a plurality of unit circuits SR1, SR3,.
- the unit circuits SR1, SR3,..., SRn-1 are connected to odd-numbered gate bus lines G1, G3,.
- the gate driver 6b includes a shift register 73b, and the shift register 73b includes a plurality of unit circuits SR2, SR4,.
- the unit circuits SR2, SR4,..., SRn are connected to the even-numbered gate bus lines G2, G4,.
- the shift registers 73a and 73b control the output signals SROUT1 to SROUTn to a high level (indicating a selected state) one by one in order.
- Output signals SROUT1 to SROUTn are applied to gate bus lines G1 to Gn, respectively. Accordingly, the gate bus lines G1 to Gn are sequentially selected one by one, and the pixel circuits Pij for one row are selected at a time. That is, the pixel TFT 4 of the pixel circuit Pij for one row is turned on.
- the source driver 5 applies a voltage corresponding to the digital video signal DV to the source bus lines S1 to Sm based on the control signal SC and the digital video signal DV. As a result, a voltage corresponding to the digital video signal DV is written (applied) to the selected pixel circuits Pij for one row. In this way, the liquid crystal display of the present embodiment displays an image.
- each of the unit circuits SR1 to SRn has input terminals INa and INb, clock terminals CKA and CKB, a power supply terminal VSS, and an output terminal OUT.
- the shift register 73a is supplied with a start pulse SP1, an end pulse EP1, two-phase clock signals CK1 and CK2, and a low-level potential VSS (for the sake of convenience, the same reference numerals as those of the power supply terminals). .
- the start pulse SP1 is input to the input terminal INa of the first stage unit circuit SR1 in the shift register 73a.
- the end pulse EP1 is input to the input terminal INb of the unit circuit SRn-1 at the final stage in the shift register 73a.
- the clock signal CK1 is input to the clock terminal CKA of the odd-numbered unit circuit in the shift register 73a and to the clock terminal CKB of the even-numbered unit circuit in the shift register 73a.
- the clock signal CK2 is input to the clock terminal CKA of the even-numbered unit circuit in the shift register 73a and the clock terminal CKB of the odd-numbered unit circuit 10 in the shift register 73a.
- the low level potential VSS is input to the power supply terminal VSS of all the unit circuits in the shift register 73a.
- the output signals SROUT1, SROUT3,..., SROUTn-1 are output from the output terminals OUT of the unit circuits SR1, SR3,..., SRn-1, respectively, and the output signals SROUT1, SROUT3,.
- ⁇ 1 is output to the gate bus lines G1, G3,..., Gn ⁇ 1, respectively.
- Each output signal includes an input terminal INa of the unit circuit after two stages (one stage after when considered in the shift register 73a) and an input terminal of the unit circuit four stages before (when considered within the shift register 73a). It is input to INb.
- a start pulse SP2, an end pulse EP2, two-phase clock signals CK3 and CK4, and a low level potential VSS are supplied to the shift register 73b.
- the start pulse SP2 is input to the input terminal INa of the first stage unit circuit SR2 in the shift register 73b.
- the end pulse EP2 is input to the input terminal INb of the unit circuit SRn at the final stage in the shift register 73b.
- the clock signal CK3 is input to the clock terminal CKA of the odd-numbered unit circuit in the shift register 73b and to the clock terminal CKB of the even-numbered unit circuit in the shift register 73b.
- the clock signal CK4 is input to the clock terminal CKA of the even-numbered unit circuit in the shift register 73b and to the clock terminal CKB of the odd-numbered unit circuit 10 in the shift register 73b.
- the low level potential VSS is input to the power supply terminal VSS of all the unit circuits in the shift register 73b.
- the output signals SROUT2, SROUT4,..., SROUTn are output from the output terminals OUT of the unit circuits SR2, SR4,..., SRn, respectively, and the output signals SROUT2, SROUT4,. Output to the gate bus lines G2, G4,..., Gn.
- Each output signal includes an input terminal INa of the unit circuit after two stages (one stage after when considered in the shift register 73b) and an input terminal of the unit circuit four stages before (when considered within the shift register 73b). It is input to INb.
- the low level potential VSS is preferably a negative potential from the viewpoint of surely turning off the n-channel TFT.
- the low-level potential VSS is positive.
- the potential may be
- each unit circuit includes transistors Tr1 to Tr4, which are n-channel TFTs, and a capacitor (hereinafter also referred to as a bootstrap capacitor) CAP.
- the transistor Tr1 is also referred to as an output transistor Tr1.
- the output transistor Tr1 has a drain connected to the clock terminal CKA and a source connected to the output terminal OUT.
- the transistor Tr2 has a drain and a gate connected to the input terminal INa, and a source connected to the gate of the output transistor Tr1.
- the bootstrap capacitor CAP is provided between the gate and source of the output transistor Tr1, one first terminal is connected to the gate of the output transistor Tr1, and the other second terminal is connected to the output terminal OUT.
- the transistor Tr3 has a drain connected to the output terminal OUT, a gate connected to the clock terminal CKB, and a source connected to the power supply terminal VSS.
- the transistor Tr4 has a drain connected to the gate of the output transistor Tr1, a gate connected to the input terminal INb, and a source connected to the power supply terminal VSS.
- the output transistor Tr1 is provided between the clock terminal CKA and the output terminal OUT, and functions as a transistor (transmission gate) that switches whether or not to pass the clock signal according to the gate potential.
- the gate of the output transistor Tr1 is capacitively coupled to a conduction terminal (source) on the output terminal OUT side. Therefore, as will be described later, in a period in which the output transistor Tr1 is on and the clock signal CK1 or CK3 (hereinafter also referred to as clock signal CKA) input to the clock terminal CKA is at a high level, The gate potential becomes higher than the high level potential of the clock signal CKA.
- netA the node to which the gate of the output transistor Tr1 is connected
- FIG. 7 and 8 show timing charts of the shift registers 73a and 73b.
- FIG. 7 shows the input / output signals of the odd-numbered unit circuits and the voltage change of the node netA in each shift register.
- the clock signal CK1 or CK3 is input to the odd-numbered unit circuit in each shift register through the clock terminal CKA, and the clock signal CK2 or CK4 is input through the clock terminal CKB. Is done.
- the period in which the potentials of the clock signals CK1 to CK4 are at the high level is substantially the same as the 1 ⁇ 2 cycle.
- the clock signal CK2 delays the clock signal CK1 by 1 ⁇ 2 period
- the clock signal CK3 delays the clock signal CK1 by 1 ⁇ 4 period
- the clock signal CK4 delays the clock signal CK2 by 1 ⁇ 4 period, respectively. Signal.
- the start pulses SP1 and SP2 become high level for the same length of time as the period of the clock signals CK2 and CK4 being high level before the start of the shift operation, respectively.
- the end pulses EP1 and EP2 (not shown in FIGS. 7 and 8) become high level for the same length of time as the potential of the clock signals CK2 and CK4, respectively, after the end of the shift operation.
- a signal start pulse SP1, SP2 or an output signal of a unit circuit in the previous stage (one stage before when considered in each shift register) input to the input terminal INa.
- start pulse SP1, SP2 or an output signal of a unit circuit in the previous stage input to the input terminal INa.
- INa also referred to as an input signal INa.
- a signal input to the input terminal INb (end pulse EP1, EP2, or the output signal of the unit circuit after four stages (after two stages in each shift register), hereinafter also referred to as the input signal INb).
- the transistor Tr4 Changes from low level to high level, the transistor Tr4 is turned on.
- the transistor Tr4 is turned on, the low level potential VSS is applied to the node netA, the potential of the node netA changes to the low level, and the output transistor Tr1 is turned off.
- the transistor Tr4 is turned off. At this time, the node netA is in a floating state, but the output transistor Tr1 is kept off. Ideally, the output transistor Tr1 is kept off and the output signal SROUT is kept low until the input signal INa becomes the next high level.
- the transistor Tr3 is turned on when the clock signal CKB is at a high level. Therefore, every time the clock signal CKB becomes high level, the low level potential VSS is applied to the output terminal OUT. As described above, the transistor Tr3 has a function of repeatedly setting the output terminal OUT to the low level potential VSS and stabilizing the output signal SROUT.
- Even-numbered unit circuits operate in the same manner as odd-numbered unit circuits.
- gate pulses are sequentially output to the gate bus lines G1, G2, G3,.
- FIGS. 9, 10 and 13 are schematic plan views illustrating the configuration in the frame region of the liquid crystal display of the first embodiment.
- FIG. 11 is a schematic cross-sectional view taken along line CD of FIG. 12 is a schematic cross-sectional view taken along line EF in FIG.
- each gate driver is provided with a wiring group 78 extending in a direction perpendicular to the gate bus line 13 described above.
- the wiring group 78 includes a wiring 74 set to the low level potential VSS, a wiring 75 that transmits the clock signal CK1 or CK3, and a wiring 76 that transmits the clock signal CK2 or CK4.
- a slit-shaped opening is formed in each wiring.
- Each shift register 73a, 73b is provided in an area between the wiring group 78 and the display area, and the output transistor Tr1 and the bootstrap capacitor CAP are arranged adjacent to each other.
- the transistors Tr2 to Tr4 are arranged adjacent to each other.
- a region (hereinafter also referred to as a control element region) 77 in which the transistors Tr2 to Tr4 are disposed is located between the wiring group 78 and the bootstrap capacitor CAP.
- the seal 62 is formed in a band-like region (hereinafter also referred to as a seal application region) 63 sandwiched between thick broken lines, and one edge of the seal application region 63 is a wiring group. 78 and the edge 10a of the array substrate 10, and the other edge is set between the bootstrap capacitor CAP and the output transistor Tr1.
- Each of the transistors Tr1 to Tr4 is a bottom gate type thin film transistor.
- the output transistor Tr1 is large in size and has a comb-like source / drain structure. Thereby, a large channel width of, for example, about several tens of ⁇ m to several hundreds of mm is secured.
- the array substrate 10 includes a transparent insulating substrate 11 such as a glass substrate.
- the output transistor Tr1 includes a gate electrode 41 on the insulating substrate 11 and a gate insulating film 42 on the gate electrode 41. And an i layer (semiconductor active layer) 43 on the gate insulating film 42, an n + layer 44 on the i layer 43, and a source electrode 45 and a drain electrode 46 provided on the n + layer 44, respectively.
- Each of the source electrode 45 and the drain electrode 46 has a plurality of comb teeth, and the source electrode 45 and the drain electrode 46 are arranged to face each other so that the comb teeth are engaged with each other.
- the bootstrap capacitor CAP includes a first electrode 31 on the insulating substrate 11, a gate insulating film 42 provided on the first electrode 31 and shared with the output transistor Tr1, and gate insulation. And a second electrode 32 on the film 42.
- the first electrode 31 is connected to the first terminal, the gate of the output transistor Tr1 (gate electrode 41) and the node netA, and the second electrode 32 is the second terminal, the source of the output transistor Tr1 (source electrode 45) and the output terminal. Connected to OUT.
- the gate electrode 41 and the first electrode 31 are formed of the same conductive film containing materials such as molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), and alloys thereof.
- the gate electrode 41 and the first electrode 31 may be formed from a laminated film of these conductive films.
- the gate insulating film 42 is formed of a transparent insulating film containing an inorganic insulating material such as silicon nitride or silicon oxide.
- the gate insulating film 42 may be formed using a laminated film of these insulating films.
- the i layer (semiconductor active layer) 43 is made of amorphous silicon
- the n + layer 44 is made of amorphous silicon containing an impurity (for example, phosphorus).
- the source electrode 45, the drain electrode 46, and the second electrode 32 are formed from the same conductive film containing materials such as Mo, Ti, Al, Cu, and alloys thereof.
- the source electrode 45, the drain electrode 46, and the second electrode 32 may be formed of a laminated film of these conductive films.
- a transparent insulating film 47 that functions as a passivation film is formed on the source electrode 45, the drain electrode 46, and the second electrode 32.
- the insulating film 47 is formed from an inorganic insulating film such as a silicon nitride film or a silicon oxide film.
- the insulating film 47 may be formed using a laminated film of these inorganic insulating films.
- a transparent insulating film 48 functioning as a planarizing film is formed on the insulating film 47.
- the insulating film 48 is formed from an organic insulating film. Examples of the material for the organic insulating film include a photosensitive resin such as a photosensitive acrylic resin.
- the transistors Tr2 to Tr4 differ only in the planar structure from the output transistor Tr1, and their cross-sectional structure is the same as that of the output transistor Tr1.
- the hatched member, the gate electrode 41, and the first electrode 31 are formed of the same conductive film
- the electrode 46 and the second electrode 32 are formed of the same conductive film.
- a white square region arranged in a region where a hatched member and a dot-shaped member overlap each other is a contact hole for connecting both members to each other Is shown.
- the pixel TFT 4 is a bottom-gate thin film transistor, like the transistors Tr1 to Tr4, and is formed together with the transistors Tr1 to Tr4 through the same process.
- a light transmitting part (light transmitting part) is provided in the bootstrap capacitor CAP. More specifically, at least one opening is formed in the first electrode 31, and at least one opening is formed in the second electrode 32 corresponding to the opening.
- the first electrode 31 has a plurality of slit-shaped openings 31a parallel to each other, and the second electrode 32 has a slit-like shape corresponding to the openings 31a.
- a plurality of openings 32a are formed. The openings 32a are arranged in parallel to each other, and each opening 32a faces the corresponding opening 31a. Therefore, light can pass through these openings.
- the state of the seal 62 is easily confirmed through the light transmitting portion of the bootstrap capacitor CAP, such as whether the seal 62 is formed at an appropriate place or whether the seal 62 is securely cured. Can do.
- the BM 52 is disposed to face the frame region 8 of the array substrate 10, particularly the region where the transistors of the shift registers 73 a and 73 b are disposed. Therefore, it is difficult to inspect the state of the seal 62 from the counter substrate 50 side, and it is not usually possible to inspect.
- the state of the seal 62 can be easily inspected from the array substrate 10 side.
- the liquid crystal display of the present embodiment can be manufactured by a general method. More specifically, first, the array substrate 10 and the counter substrate 50 are respectively produced by a normal method.
- a substrate bonding process and a liquid crystal injection process are performed.
- a drop injection method (ODF method) or a vacuum injection method is generally used.
- a seal material before curing (also referred to as a seal material in this specification) is applied to either the array substrate 10 or the counter substrate 50 by a method such as a screen printing method or a dispenser drawing method.
- the sealing material is applied in a closed annular shape.
- a liquid crystal material is dropped on a substrate on which a sealing material is applied or a substrate on which a sealing material is not applied.
- the type of the sealing material is not particularly limited, and a general sealing material can be used.
- a thermosetting sealing material a sealing material that does not have thermosetting property and has photocuring property (for example, UV curable property) (hereinafter, also referred to as photocurable sealing material), and photocuring property (for example, Examples thereof include a sealing material having ultraviolet curing properties and thermosetting properties (hereinafter also referred to as a combined light / heat sealing material). Of these, a photocurable sealing material and a combined light / heat sealing material are suitable.
- the sealing material generally includes an acrylic resin and / or an epoxy resin. Specific examples of the light / heat combination type sealing material include, for example, Photorec S series (manufactured by Sekisui Chemical Co., Ltd.) mainly composed of an epoxy acrylic resin.
- the sealing material is located at a location overlapping the BM 52.
- light sealing and / or heat treatment is performed to cure the sealing material.
- the light / heat combination type sealing material first, light is irradiated from the array substrate 10 side. This is because the BM 52 is formed on the counter substrate 50. Then, heat treatment is performed to fully cure the sealing material.
- the conditions of light irradiation and heat treatment can be set as appropriate according to the characteristics of the sealing material. However, when the Photorec S series is used, for example, ultraviolet rays of about 10 J are irradiated and heat treatment is performed at 120 ° C. for 60 minutes.
- a sealing material is applied to either the array substrate 10 or the counter substrate 50 by a method such as a screen printing method or a dispenser drawing method.
- the sealing material is applied in a ring shape except for the region where the liquid crystal injection port is formed.
- the type of the sealing material is not particularly limited, and a general sealing material can be used.
- a thermosetting sealing material a photocurable sealing material, a combined light / heat type A sealing material is mentioned.
- a thermosetting sealing material is preferable.
- the sealing material is located at a location overlapping the BM 52.
- the sealing material is cured by performing light irradiation and / or heat treatment.
- a liquid crystal inlet serving as an opening is formed in a portion where the sealing material is not applied.
- the liquid crystal injection port is immersed in the liquid crystal material under vacuum, and then returned to atmospheric pressure, and the liquid crystal material is injected between the array substrate 10 and the counter substrate 50 through the liquid crystal injection port. Finally, the liquid crystal injection port is sealed.
- the seal application area approaches the display area, and a seal may be formed on the shift register. Further, the size of the output transistor and the bootstrap capacitor connected to the gate bus line is large. Therefore, if a photo-curing type sealing material or a combined photo / heat type sealing material is applied on the output transistor and the bootstrap capacitor, an uncured portion is generated in the seal because light is blocked by the output transistor and the capacitor. Is concerned. When the uncured portion is generated, the bonding force (adhesive strength) between the array substrate and the counter substrate is lowered. In addition, the sealant component of the uncured portion may diffuse into the display area, and display quality may be degraded. That is, there is a high possibility that a display abnormality will occur at the end of the display area.
- the output transistor Tr1 is as far as possible from the seal 62 and as close as possible to the display area 7.
- the bootstrap capacitor CAP is as far as possible from the display area 7 and as close as possible to the seal 62. Therefore, the bootstrap capacitor CAP is disposed at a position farther from the display area 7 (place closer to the edge 10a of the array substrate 10), and the output transistor Tr1 is disposed at a position closer to the display area 7.
- the output transistor Tr1 is disposed on the display area 7 side of the bootstrap capacitor CAP and is disposed in an area between the bootstrap capacitor CAP and the display area 7. Further, as described above, the bootstrap capacitor CAP is provided with a light transmitting portion.
- the photocurable sealing material or the combined light / heat sealing material can be reliably cured. As a result, it is possible to suppress a decrease in the bonding force between the substrates and a decrease in display quality due to the diffusion of the sealing material component of the uncured portion into the display region, and the frame region 8 can be further narrowed.
- the position and width of the seal 62 are not particularly limited.
- the seal 62 may not overlap the bootstrap capacitor CAP as shown in FIG. 10, or may overlap part or all of the bootstrap capacitor CAP as shown in FIG.
- the seal 62 is preferably formed so as not to overlap the output transistor Tr1.
- the area of the bootstrap capacitor CAP is increased by the amount of the light transmitting portion.
- the seal application area 63 can be extended over the bootstrap capacitor CAP, and the seal 62 can be placed close to the display area 7. Therefore, even if the area of the bootstrap capacitor CAP increases, the width of the frame region 8 can be reduced.
- FIG. 14 is a schematic plan view of a bootstrap capacitor in the liquid crystal display according to the second embodiment.
- FIG. 15 is a schematic cross-sectional view taken along the line JK of FIG.
- the bootstrap capacitor CAP further includes a third electrode 33 on the insulating film 48.
- the third electrode 33 is formed so as to cover the first electrode 31 and the second electrode 32, and is formed on the first electrode 31 through the contact hole 34 that penetrates the gate insulating film 42, the insulating film 47, and the insulating film 48.
- One electrode 31 is connected.
- the 1st electrode 31 and the 3rd electrode 33 are arrange
- the third electrode 33 is formed of a transparent conductive film including a transparent conductive material such as indium tin oxide (ITO: Indium Tin Oxide) or indium zinc oxide (IZO: Indium Zinc Oxide). Therefore, light can pass through the third electrode 33.
- the third electrode 33 may be formed using a laminated film of these transparent conductive films.
- the third electrode 33 may be formed of the same conductive film as the pixel electrode 9 and / or the auxiliary capacitance electrode.
- a liquid crystal mode using a lateral electric field such as an IPS (In Plane Switching) mode or an FFS (Fringe Field Switching) mode
- the third electrode 33 may be formed of the same conductive film as the common electrode. .
- the bootstrap capacitor CAP is maintained even in a narrow region while maintaining the effects described in the first embodiment, for example, the effect that the seal state can be easily inspected and the effect that the sealing material is sufficiently cured.
- the capacity of can be increased. Therefore, the bootstrap capacitor CAP can be reduced, and a further frame can be formed.
- the counter substrate 50 when a liquid crystal mode using a vertical electric field such as a TN mode or a VA mode is employed, the counter substrate 50 includes a counter electrode, and therefore a conductive material (for example, it is preferable that resin beads coated with a metal such as gold are not mixed. This is because the counter electrode may leak from the third electrode 31 when the sealing material includes a conductive material. Therefore, in the above-described case, it is preferable that the conductive material is selectively applied only on the common transfer electrode 14 without mixing the conductive material into the sealing material. For example, the carbon paste may be applied only on the common transfer electrode 14 by a syringe.
- At least one opening and / or notch may be formed corresponding to the light transmitting portion.
- FIG. 16 is a schematic plan view illustrating a configuration in a frame region of the liquid crystal display according to the third embodiment.
- the output transistor Tr ⁇ b> 1 and the bootstrap capacitor CAP are disposed between the wiring group 78 and the control element region 77.
- the output transistor Tr1 is arranged on the edge 10a side of the array substrate 10 with respect to the bootstrap capacitor CAP, that is, in a region between the bootstrap capacitor CAP and the edge 10a.
- the output transistor Tr1 is disposed below the seal 62.
- the bootstrap capacitor CAP is disposed in a region between the output transistor Tr1 and the display region, and at least one opening (translucent portion) is formed in the bootstrap capacitor CAP as described above. ing.
- an uncured portion may occur in the seal 62 in a region corresponding to the output transistor Tr1.
- the portion of the uncured portion on the display area side is irradiated with light through the light transmitting portion of the bootstrap capacitor CAP, and can be cured stably. Therefore, it is possible to prevent the sealing material component of the uncured portion from diffusing into the display area. Further, in the present embodiment, since the seal 62 can be disposed closer to the display area than in the first embodiment, the frame area can be made narrower.
- FIG. 22 is a schematic plan view illustrating a configuration in a frame region of the liquid crystal display according to the fourth embodiment.
- FIG. 23 is a schematic sectional view taken along line MN in FIG.
- the bootstrap capacitor CAP is divided into two or more parts, for example, a capacitor part CAP (1) and a capacitor part CAP (2).
- a translucent part is formed in each of the capacitor portions CAP (1) and CAP (2).
- One of them, for example, the capacitor portion CAP (2) is disposed at a position farther from the display region than the other capacitor portions, and is disposed between the wiring group 78 and the control element region 77. This makes it possible to bring the control element region 77 closer to the display region as compared with the first embodiment, and the distance from the edge 10a of the array substrate to the transistors Tr2 to Tr4 is increased. Accordingly, it is possible to secure a margin for the characteristic deterioration of the transistors Tr2 to Tr4 due to moisture intrusion from the outside.
- the capacitor portion CAP (1) is different from the bootstrap capacitor CAP described in the first embodiment only in plan structure, and the cross-sectional structure is the same as the cross-sectional structure of the bootstrap capacitor CAP described in the first embodiment. is there. That is, the capacitor portion CAP (1) includes the first electrode 31 on the insulating substrate 11, the gate insulating film 42 on the first electrode 31, and the second electrode 32 on the gate insulating film 42.
- the first electrode 31 is connected to the first terminal, the gate (gate electrode) of the output transistor Tr1 and the node netA
- the second electrode 32 is connected to the second terminal, the source (source electrode) of the output transistor Tr1 and the output terminal OUT. It is connected.
- the capacitor portion CAP (2) includes a first electrode 35 on the insulating substrate 11, a gate insulating film 42 on the first electrode 35, and a second electrode 36 on the gate insulating film 42.
- the first electrode 35 has a plurality of slit-shaped openings 35a parallel to each other
- the second electrode 36 has a plurality of slit-shaped openings 36a corresponding to the openings 35a.
- the openings 36a are arranged in parallel to each other, and each opening 36a faces the corresponding opening 35a. Therefore, light can pass through these openings.
- One of the electrodes 35 and 36 is connected to the first terminal, the gate (gate electrode) of the output transistor Tr1 and the node netA via the first electrode 31, and the other of the electrodes 35 and 36 is connected to the second electrode 32.
- the location of the electrode connected to the node netA and the electrode connected to the output terminal OUT may be interchanged between the capacitor portions CAP (1) and CAP (2).
- the lower layer first electrode 31 is connected to the node netA
- the upper layer second electrode 32 is connected to the output terminal OUT.
- the upper layer second electrode 31 is connected to the node netA.
- the electrode 36 may be connected to the node netA, and the lower first electrode 35 may be connected to the output terminal OUT.
- the connection destination of each of the electrodes 31, 32, 35, and 36 can be selected as appropriate from among the output terminal OUT and the node netA.
- each of the wirings is connected between the lower electrode layer where the electrodes 31 and 35 exist and the upper electrode layer where the electrodes 32 and 36 exist. It is preferable.
- FIG. 24 is a schematic plan view illustrating a configuration in a frame region of the liquid crystal display according to the fifth embodiment.
- the translucent part is not formed in the capacitor part CAP (2), and the first electrode 35 and the second electrode 36 of the capacitor part CAP (2) have openings. Is not formed.
- This embodiment is suitable when the widths of the electrodes 35 and 36 are sufficiently narrow, for example, 10 ⁇ m or less.
- FIG. 25 is a schematic plan view illustrating a configuration in a frame region of the liquid crystal display according to the sixth embodiment.
- FIG. 26 is a schematic sectional view taken along the line PQ in FIG.
- the bootstrap capacitor CAP is divided into two or more parts, for example, a capacitor part CAP (1) and a capacitor part CAP (2).
- the capacitor portion CAP (2) has a light transmitting portion, but the capacitor portion CAP (1) has no light transmitting portion.
- the capacitor portion CAP (2) in which the translucent portion is formed is disposed at a position farther from the display area than the capacitor portion CAP (1), and is disposed between the wiring group 78 and the control element region 77. Yes. This makes it possible to bring the control element region 77 closer to the display region as compared with the first embodiment, and the distance from the edge 10a of the array substrate to the transistors Tr2 to Tr4 is increased. Accordingly, it is possible to secure a margin for the characteristic deterioration of the transistors Tr2 to Tr4 due to moisture intrusion from the outside.
- the capacitor portion CAP (1) is different from the bootstrap capacitor CAP described in the first embodiment only in plan structure, and the cross-sectional structure is the same as the cross-sectional structure of the bootstrap capacitor CAP described in the first embodiment. is there. That is, the capacitor portion CAP (1) includes the first electrode 31 on the insulating substrate 11, the gate insulating film 42 on the first electrode 31, and the second electrode 32 on the gate insulating film 42.
- the first electrode 31 is connected to the first terminal, the gate (gate electrode) of the output transistor Tr1 and the node netA
- the second electrode 32 is connected to the second terminal, the source (source electrode) of the output transistor Tr1 and the output terminal OUT. It is connected. However, no opening is formed in the first electrode 31 and the second electrode 32.
- the capacitor portion CAP (2) includes a first electrode 35 on the insulating substrate 11, a gate insulating film 42 on the first electrode 35, and a second electrode 36 on the gate insulating film 42.
- the first electrode 35 has a plurality of slit-shaped openings 35a parallel to each other
- the second electrode 36 has a plurality of slit-shaped openings 36a corresponding to the openings 35a.
- the openings 36a are arranged in parallel to each other, and each opening 36a faces the corresponding opening 35a. Therefore, light can pass through these openings.
- the first electrode 35 is connected to the first terminal, the gate (gate electrode) of the output transistor Tr1 and the node netA via the first electrode 31, and the second electrode 36 is connected to the second electrode 32 via the second electrode 32.
- the terminal is connected to the source (source electrode) of the output transistor Tr1 and the output terminal OUT.
- FIG. 25 shows an example in which the upper and lower positional relationship between the electrode connected to the node netA and the electrode connected to the output terminal OUT is the same between the capacitor portions CAP (1) and CAP (2). However, these arrangement relationships may be switched as described in the fourth embodiment according to the shape and / or size of the empty space in the control element region 77.
- FIG. 27 is a schematic plan view illustrating a configuration in a frame region of the liquid crystal display according to the seventh embodiment.
- the arrangement locations of the output transistor Tr1 and the capacitor portion CAP (1) are interchanged, and the output transistor Tr1 and the control element region 77 have the capacitor portions CAP (1) and CAP ( 2).
- the output transistor Tr1 can be disposed closer to the wiring 75 connected to the output transistor Tr1 than in the case of the sixth embodiment. Therefore, the size of the capacitor portion CAP (1) can be secured, and the occurrence of a short circuit between the capacitor portion CAP (1) and the wiring connecting the output transistor Tr1 to the wiring 75 can be suppressed.
- FIGS. 17 to 19 are schematic plan views of bootstrap capacitors in the liquid crystal displays of the first to seventh embodiments. 17-19 each show a bootstrap capacitor CAP, capacitor portion CAP (1), or capacitor portion CAP (2).
- the shape and arrangement of the openings formed in the bootstrap capacitor are not particularly limited.
- the openings 31a, 32a, 35a, and 36a are vertically and horizontally May be arranged.
- the first electrodes 31 and 35 may have at least one notch, and the second electrodes 32 and 36 have at least one notch corresponding to the notch. May be.
- the first electrodes 31 and 35 may be formed with a plurality of slit-shaped notches 31b and 35b which are parallel to each other, and the second electrodes 32 and 36 A plurality of slit-shaped notches 32b and 36b may be formed corresponding to the notches 31b and 35b.
- the notches 32b and 36b are arranged in parallel to each other, and the notches 32b and 36b face the corresponding notches 31b and 36b. Further, the bootstrap capacitor may have a mixture of openings and notches. Furthermore, the opening and the notch may be opposed to each other.
- variety of each linear part of a 1st and 2nd electrode are not specifically limited, It can set suitably.
- the width of each opening and notch is preferably 5 ⁇ m or more, more preferably 10 ⁇ m or more, and The width is preferably 40 ⁇ m or less, and more preferably 10 ⁇ m or less.
- the area of the translucent portion can be ensured by the gap, so that the effects described in the first embodiment, for example, the effect that the state of the seal can be easily inspected and the sealing material are sufficiently obtained. The effect of curing can be achieved more effectively.
- the latter structure it is possible to further reduce the frame.
- the semiconductor material of each TFT is not particularly limited, and can be appropriately selected.
- a group 14 element semiconductor such as silicon, an oxide semiconductor, or the like can be given.
- the crystallinity of the semiconductor material of each TFT is not particularly limited, and may be single crystal, polycrystal, amorphous, or microcrystal, and may include two or more of these crystal structures.
- the output transistor includes amorphous silicon
- the channel width of the output transistor and the size of the bootstrap capacitor are particularly large from the viewpoint of increasing the driving capability. Therefore, when the output transistor contains amorphous silicon, the effect that the seal state can be easily inspected and the effect that the sealing material is sufficiently cured can be remarkably exhibited.
- the oxide semiconductor contains at least one element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), and silicon (Si), and oxygen (O). It is preferable that In, Ga, Zn, and O are included.
- the number and arrangement location of the bootstrap capacitors in which the light transmitting portions (openings and / or notches) are formed are not particularly limited and can be set as appropriate. That is, it is only necessary to form a light-transmitting part in at least one bootstrap capacitor, and all bootstrap capacitors may include a light-transmitting part, or only some bootstrap capacitors include a light-transmitting part. May be. However, from the viewpoint of exhibiting the above-described effects particularly effectively, it is preferable to form a light transmitting portion (opening and / or notch) in all bootstrap capacitors.
- the types of elements and wirings of each gate driver are not particularly limited except for the output transistor and the bootstrap capacitor, and can be determined as appropriate.
- the liquid crystal display has been described.
- the display device according to the present invention may be a display device including a shift register including an output transistor and a bootstrap capacitor, and is not particularly limited to the liquid crystal display.
- a microcapsule-type electrophoretic electronic paper, an organic or inorganic EL display, or the like may be used.
- FIG. 20 is a circuit diagram illustrating a circuit configuration of unit pixels (pixels or sub-pixels) included in the active matrix organic EL display according to the eighth embodiment. As shown in FIG. 20, this pixel circuit is provided with six pixel transistors Tr11 to Tr16 and one organic EL element 161.
- the transistor Tr13 corresponds to the second pixel transistor in the embodiment (C)
- the transistor Tr16 includes the pixel transistor in the embodiment (B) and the first pixel transistor in the embodiment (C). It corresponds to.
- the transistor Tr11 is a wiring (hereinafter also referred to as an initialization voltage line) set to a predetermined potential in response to a signal (initialization signal) input from the bus line (hereinafter also referred to as an initialization signal line) 115. .) Discharge the capacitor C through 120. As a result, the gate voltage of the transistor Tr14 is initialized.
- the transistor Tr12 compensates for variations in threshold voltage of the transistor Tr14.
- the transistor Tr13 performs switching of the data signal input from the data bus line 112 in response to a gate signal (scanning signal) input from the gate bus line 113.
- the gate bus line 113 corresponds to the first bus line in the embodiment (C).
- the data signal is a signal generated by a display or a data driver based on an image signal input from the outside, and includes gradation data of unit pixels.
- the transistor Tr14 controls the amount of current supplied to the organic EL element 161 in response to the data signal input via the transistor Tr13.
- the transistor Tr15 responds to a signal input from a bus line (hereinafter also referred to as a light emission control line) 121, and is connected to a transistor Tr14 from a wiring (hereinafter also referred to as an anode side power supply line) 122 set to a predetermined potential.
- the current supplied to the is switched.
- the light emission control line 121 corresponds to the bus line in the embodiment (B).
- the transistor Tr16 performs switching of a current supplied to the organic EL element 161 via the transistor Tr14 in response to a signal input from the light emission control line 121.
- the capacitor C is provided to hold the gate voltage applied to the transistor Tr14.
- the organic EL element 161 emits light with luminance corresponding to the current supplied via the transistor Tr15, the transistor Tr14, and the transistor Tr16.
- the anode of the organic EL element 161 is connected to the drain of the transistor Tr16, and the cathode of the organic EL element 161 is connected to a wiring 123 (hereinafter also referred to as a cathode side power supply line) set to a predetermined potential.
- a wiring 123 hereinafter also referred to as a cathode side power supply line
- FIG. 21 is a schematic plan view of an organic EL substrate included in the active matrix organic EL display according to the eighth embodiment.
- the organic EL substrate corresponds to the first substrate.
- the initialization voltage line 120, the gate bus line 113, and the light emission control line 121 extend in the row direction.
- the anode power line 122 and the data bus line 112 extend in the column direction. Note that the anode-side power supply lines 122 adjacent in the row direction may be connected to each other in the display region 107.
- a drive circuit for the gate bus line 113 and a drive circuit for the light emission control line 121 are provided outside the display area 107.
- a drive circuit 113D for the gate bus line 113 may be provided on the left side of the display area 107
- a drive circuit 121D for the light emission control line 121 may be provided on the right side of the display area 107.
- a drive circuit for the gate bus line 113 may be provided on both the left and right sides of the display area 107
- a drive circuit for the light emission control line 121 may be provided on the outer side (that is, a position farther from the display area 107).
- the light emission control line 121 passes through the drive circuit for the gate bus line 113 and is connected to the drive circuit for the light emission control line 121.
- the initialization signal line 115 extends in the row direction in the same manner as the bus line such as the initialization voltage line 120, and is connected to the gate bus line 113 for pixels in the adjacent row. They may be connected to each other, or may be connected to a drive circuit provided exclusively for the initialization signal line 115 (hereinafter also referred to as an initialization signal line drive circuit).
- Each of the above-described drive circuits may include a shift register configured by connecting a plurality of unit circuits in multiple stages.
- the initialization voltage line 120 and the anode side power supply line 122 are connected to the wiring (initialization voltage line main wiring) 120W and the wiring (anode power supply main wiring) 122W outside the display area 107, respectively. ing.
- the cathodes of all the organic EL elements 161 are connected to each other in the display area 107 and are connected to the cathode-side power line 123 outside the display area 107.
- the pixels in each row are provided with three periods (steps) in this order in one frame, that is, an initialization period, a writing period, and a light emission period.
- the transistor Tr11 is turned on by an ON signal input from the initialization signal line 115, and the charge of the capacitor C is discharged through the initialization voltage line 120. Thereby, the gate voltage of the transistor Tr14 is initialized.
- gray scale data input from the data bus line 112 is written to the transistor Tr14 in accordance with the ON signal input from the gate bus line 113.
- the gate voltage of the transistor Tr14 is lower than the voltage input from the data bus line 112 by the threshold voltage of the transistor Tr14.
- the capacitor C is charged with a charge corresponding to the gate potential of the transistor Tr14.
- the transistor Tr15 and the transistor Tr16 are turned on by an on signal input from the light emission control line 121, and a current having a current amount corresponding to the gate voltage of the transistor Tr14 is supplied to the organic EL element 161.
- the organic EL element 161 emits light.
- a general organic EL element is easily deteriorated by moisture, oxygen, or the like. Therefore, in order to protect the organic EL element 161, a counter substrate corresponding to the second substrate and facing the organic EL substrate is provided, and a seal is provided between the organic EL substrate and the counter substrate. Thereby, the space between both the substrates is sealed.
- the seal material include frit glass.
- the seal may include a portion where the frit glass is cured and a portion where the resin is cured. This resin portion is provided on one or both sides of the inside and outside of the frit glass portion (that is, the display region side and the edge side of the substrate).
- Specific examples of the resin include a photocurable and / or thermosetting epoxy resin, a photocurable and / or thermosetting acrylic resin, and a composition containing such a resin.
- the shift register in the display device is applicable to the above-described drive circuit for the gate bus line 113, drive circuit for the light emission control line 121, and drive circuit for the initialization signal line. That is, these drive circuits can include the output transistor described in the first to seventh embodiments and a bootstrap capacitor in which a light-transmitting portion (an opening and / or a notch) is formed. Therefore, also in the present embodiment, the effects described in the first embodiment, for example, the effect that the seal state can be easily inspected and the effect that the sealing material is sufficiently cured can be achieved.
- the first to eighth embodiments may be combined with each other.
- bootstrap capacitors having different structures may be formed in the same shift register, or a plurality of shift registers may have different structures.
- a capacitor may be included.
- the width of each opening and notch provided in the bootstrap capacitor may be 5 ⁇ m or 10 ⁇ m or more, and the width of each linear portion is 40 ⁇ m or 10 ⁇ m or less.
- the semiconductor material of each TFT is not particularly limited, and examples thereof include a group 14 element semiconductor such as silicon, and an oxide semiconductor.
- the crystallinity of the semiconductor material of each TFT is not particularly limited, and may be single crystal, polycrystal, amorphous, or microcrystal, and may include two or more of these crystal structures.
- the output transistor may include amorphous silicon.
- the oxide semiconductor preferably contains at least one element selected from the group consisting of In, Ga, Zn, Al, and Si and O, and more preferably contains In, Ga, Zn, and O.
- the number and arrangement location of the bootstrap capacitors in which the light transmitting parts (openings and / or notches) are formed are not particularly limited. For example, all the bootstrap capacitors are transparent. The light portion may be included, or only some bootstrap capacitors may include the light transmitting portion.
- Pixel 4 TFT for pixel 5: Source bus line drive circuit (source driver) 6a, 6b: gate bus line drive circuit (gate driver) 7, 107: Display area 8: Frame area 9: Pixel electrode 10: Array substrate 10a: Edge 11: Insulating substrate 12, S1 to Sm: Source bus lines 13, 113, G1 to Gn: Gate bus line 14: For common transition Electrode 16: Common trunk line 17: Common bus line 18, 19: Lead line 25: Input lines 26, 27, 28, 29, 30: Terminal 31, 35: First electrodes 31a, 32a, 35a, 36a: Opening 31b 32b, 35b, 36b: notches 32, 36: second electrode 33: third electrode 34: contact hole 41: gate electrode 42: gate insulating film 43: i layer (semiconductor active layer) 44: n + layer 45: source electrode 46: drain electrode 47, 48: insulating film 50: counter substrate 51: insulating substrate 52: black matrix (BM) 61: Liquid crystal layer 62: Seal
Abstract
Description
本発明に係る表示装置における好ましい実施形態について以下に説明する。なお、以下の好ましい実施形態は、適宜、互いに組み合わされてもよく、以下の2以上の好ましい実施形態を互いに組み合わせた実施形態もまた、好ましい実施形態の一つである。
図1~13を参照して、実施形態1の液晶ディスプレイについて説明する。まず、図1~3を参照して、本実施形態の液晶ディスプレイの全体の構造について説明する。図1は、実施形態1の液晶ディスプレイに含まれる液晶パネルの平面模式図である。図2は、図1のA-B線における断面模式図である。図3は、実施形態1の液晶ディスプレイに含まれる液晶パネルの平面模式図である。
まず、入力端子INaに入力される信号(スタートパルスSP1、SP2、又は、前々段(各シフトレジスタ内で考えると一段前)の単位回路の出力信号。以下、入力信号INaとも言う。)がローレベルからハイレベルに変化すると、ダイオード接続されたトランジスタTr2を介してノードnetAの電位もハイレベルに変化し、出力トランジスタTr1はオン状態になる。
本実施形態の液晶ディスプレイは、一般的な方法により製造することができるが、より詳細には、まず、アレイ基板10と対向基板50とを通常の方法により各々作製する。
まず、スクリーン印刷法、ディスペンサ描画法等の方法により、アレイ基板10及び対向基板50のいずれかに硬化前のシールの材料(本明細書ではシール材とも言う。)を塗布する。シール材は、閉じた環状に塗布される。また、シール材が塗布された基板、又は、塗布されてない基板上に液晶材料を滴下する。
まず、スクリーン印刷法、ディスペンサ描画法等の方法により、アレイ基板10及び対向基板50のいずれかにシール材を塗布する。シール材は、液晶注入口が形成される領域を除いて、環状に塗布される。
実施形態2の液晶ディスプレイは、ブートストラップ・コンデンサの構造が異なることを除いて、実施形態1の液晶ディスプレイと実質的に同じである。図14は、実施形態2の液晶ディスプレイにおけるブートストラップ・コンデンサの平面模式図である。図15は、図14のJ-K線における断面模式図である。
実施形態3の液晶ディスプレイは、シフトレジスタ中の素子のレイアウトが異なることを除いて、実施形態1の液晶ディスプレイと実質的に同じである。図16は、実施形態3の液晶ディスプレイの額縁領域における構成を示す平面模式図である。
実施形態4の液晶ディスプレイは、シフトレジスタ中の素子のレイアウトが異なることを除いて、実施形態1の液晶ディスプレイと実質的に同じである。図22は、実施形態4の液晶ディスプレイの額縁領域における構成を示す平面模式図である。図23は、図22のM-N線における断面模式図である。
実施形態5の液晶ディスプレイは、コンデンサ部分CAP(2)の平面構造が異なることを除いて、実施形態4の液晶ディスプレイと実質的に同じである。図24は、実施形態5の液晶ディスプレイの額縁領域における構成を示す平面模式図である。
実施形態6の液晶ディスプレイは、シフトレジスタ中の素子のレイアウトが異なることを除いて、実施形態1の液晶ディスプレイと実質的に同じである。図25は、実施形態6の液晶ディスプレイの額縁領域における構成を示す平面模式図である。図26は、図25のP-Q線における断面模式図である。
実施形態7の液晶ディスプレイは、シフトレジスタ中の素子のレイアウトが異なることを除いて、実施形態6の液晶ディスプレイと実質的に同じである。図27は、実施形態7の液晶ディスプレイの額縁領域における構成を示す平面模式図である。
以下にアクティブマトリクス型有機ELディスプレイに係る実施形態8を示す。
図20は、実施形態8のアクティブマトリクス型有機ELディスプレイに含まれる単位画素(画素又はサブ画素)の回路構成を示す回路図である。図20に示すように、この画素回路には、6つの画素用トランジスタTr11~Tr16と、1つの有機EL素子161とが設けられている。トランジスタTr13は、上記実施形態(C)における第2の画素用トランジスタに相当し、トランジスタTr16は、上記実施形態(B)における画素用トランジスタと、上記実施形態(C)における第1の画素用トランジスタとに相当する。
2:表示部
3:画素
4:画素用TFT
5:ソースバスライン用の駆動回路(ソースドライバ)
6a、6b:ゲートバスライン用の駆動回路(ゲートドライバ)
7、107:表示領域
8:額縁領域
9:画素電極
10:アレイ基板
10a:エッジ
11:絶縁基板
12、S1~Sm:ソースバスライン
13、113、G1~Gn:ゲートバスライン
14:コモン転移用電極
16:共通幹配線
17:コモンバスライン
18、19:引き出し線
25:入力配線
26、27、28、29、30:端子
31、35:第1電極
31a、32a、35a、36a:開口部
31b、32b、35b、36b:切り欠き部
32、36:第2電極
33:第3電極
34:コンタクトホール
41:ゲート電極
42:ゲート絶縁膜
43:i層(半導体活性層)
44:n+層
45:ソース電極
46:ドレイン電極
47、48:絶縁膜
50:対向基板
51:絶縁基板
52:ブラックマトリクス(BM)
61:液晶層
62:シール
63:シール塗布領域
71:画素アレイ
72:表示制御回路
73a、73b:シフトレジスタ
74~76:配線
77:制御素子領域
78:配線群
112:データバスライン
113D:ゲートバスライン用の駆動回路
115:初期化信号線
120:初期化電圧線
120W:初期化電圧線用幹配線
121:発光制御線
121D:発光制御線用の駆動回路
122:陽極側電源線
122W:陽極電源線用幹配線
123:陰極側電源線
161:有機EL素子
Pij:画素回路
SR1~SRn:単位回路
INa、INb:入力端子
CKA、CKB:クロック端子
VSS:電源端子
OUT:出力端子
Tr1~Tr4、Tr11~Tr16:トランジスタ
CAP:ブートストラップ・コンデンサ
CAP(1)、CAP(2):コンデンサ部分
C:コンデンサ
Claims (11)
- 第1基板と、前記第1基板に対向する第2基板と、前記第1基板及び前記第2基板の間に設けられたシールとを備える表示装置であって、
前記第1基板は、絶縁基板と、前記絶縁基板上にモノリシック形成されたシフトレジスタと、複数のバスラインとを含み、
前記シフトレジスタは、多段接続された複数の単位回路を含み、
前記複数の単位回路は各々、クロック信号が入力されるクロック端子と、対応するバスラインに接続され、出力信号が出力される出力端子と、ソース及びドレインの一方が前記クロック端子に接続され、前記ソース及び前記ドレインの他方が前記出力端子に接続されたトランジスタと、第1端子が前記トランジスタのゲートに接続され、第2端子が前記出力端子に接続されたコンデンサとを含み、
前記コンデンサは、第1電極と、前記第1電極上の絶縁層と、前記絶縁層上の第2電極とを含み、
前記複数の単位回路のうちの少なくとも一つにおいて、前記第1電極には、第1切り欠き部及び/又は第1開口部が設けられ、前記第2電極には、前記第1切り欠き部及び/又は前記第1開口部に対向する第2切り欠き部及び/又は第2開口部が設けられる表示装置。 - 前記シールは、光硬化性を有する材料の硬化物を含む請求項1記載の表示装置。
- 前記材料は、熱硬化性を更に有する請求項2記載の表示装置。
- 前記トランジスタは、前記コンデンサと、前記第1基板の表示領域との間の領域内に配置され、
前記シールは、前記トランジスタ上に配置されない請求項1~3のいずれかに記載の表示装置。 - 前記コンデンサは、前記トランジスタと、前記第1基板の表示領域との間の領域内に配置され、
前記トランジスタは、前記シールに覆われ、
前記コンデンサの少なくとも一部は、前記シールの下に配置される請求項1~3のいずれかに記載の表示装置。 - 前記コンデンサは、前記第2電極上の第2絶縁層と、前記第2絶縁層上の透明電極とを更に含み、
前記透明電極は、前記第1電極に接続される請求項1~5のいずれかに記載の表示装置。 - 前記第1基板は、表示領域内に設けられた複数の画素回路を含み、
前記複数の画素回路は各々、画素用トランジスタと、前記画素用トランジスタに接続された画素電極とを含み、
前記複数のバスラインは各々、対応する複数の画素用トランジスタのゲートに接続される請求項1~6のいずれかに記載の表示装置。 - 前記第1基板は、表示領域内に設けられた複数の画素回路を含み、
前記複数の画素回路は各々、画素用トランジスタと、前記画素用トランジスタに接続されたエレクトロルミネッセンス素子とを含み、
前記複数のバスラインは各々、対応する複数の画素用トランジスタのゲートに接続される請求項1~6のいずれかに記載の表示装置。 - 前記複数のバスラインは、第1の複数のバスラインであり、
前記第1基板は、表示領域内に設けられた複数の画素回路と、複数のデータバスラインとを含み、
前記複数の画素回路は各々、第1の画素用トランジスタと、対応するデータバスラインに接続された第2の画素用トランジスタと、前記第1の画素用トランジスタに接続されたエレクトロルミネッセンス素子とを含み、
前記第1の複数のバスラインは各々、対応する複数の第2の画素用トランジスタのゲートに接続される請求項1~6のいずれかに記載の表示装置。 - 前記トランジスタは、酸化物半導体を含む請求項1~9のいずれかに記載の表示装置。
- 前記酸化物半導体は、インジウム(In)、ガリウム(Ga)、亜鉛(Zn)及び酸素(O)を含む請求項10記載の表示装置。
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Also Published As
Publication number | Publication date |
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JPWO2013157285A1 (ja) | 2015-12-21 |
JP5973556B2 (ja) | 2016-08-23 |
US9223161B2 (en) | 2015-12-29 |
JP2016167093A (ja) | 2016-09-15 |
TW201344315A (zh) | 2013-11-01 |
KR20140133924A (ko) | 2014-11-20 |
EP2840566A1 (en) | 2015-02-25 |
US20150070616A1 (en) | 2015-03-12 |
EP2840566A4 (en) | 2015-04-15 |
TWI544260B (zh) | 2016-08-01 |
SG11201406630YA (en) | 2015-01-29 |
KR101697841B1 (ko) | 2017-01-18 |
MY167330A (en) | 2018-08-16 |
JP6235652B2 (ja) | 2017-11-22 |
CN104221072B (zh) | 2016-09-07 |
CN104221072A (zh) | 2014-12-17 |
EP2840566B1 (en) | 2017-06-14 |
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