WO2021046987A1 - 一种goa电路布局 - Google Patents

一种goa电路布局 Download PDF

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Publication number
WO2021046987A1
WO2021046987A1 PCT/CN2019/114173 CN2019114173W WO2021046987A1 WO 2021046987 A1 WO2021046987 A1 WO 2021046987A1 CN 2019114173 W CN2019114173 W CN 2019114173W WO 2021046987 A1 WO2021046987 A1 WO 2021046987A1
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WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
driving thin
capacitor
circuit layout
Prior art date
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PCT/CN2019/114173
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English (en)
French (fr)
Inventor
张留旗
韩佰祥
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/627,785 priority Critical patent/US11488557B2/en
Publication of WO2021046987A1 publication Critical patent/WO2021046987A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G09G2330/045—Protection against panel overheating

Definitions

  • the present invention relates to the field of display technology, in particular to a GOA circuit layout.
  • GOA Gate Driver on Array
  • FIG. 1 is a schematic diagram of the layout relationship between the driving thin film transistor and the capacitor in the existing GOA circuit layout.
  • the existing GOA circuit layout has the capacitor area 2 independently arranged below or on the right side of the driving thin film transistor area 1 (not shown), which has heat dissipation. The problem of insufficient effect.
  • the present invention provides a GOA circuit layout to solve the technical problem of insufficient heat dissipation effect of the existing GOA circuit layout.
  • the present invention provides a GOA circuit layout, including a plurality of driving thin film transistor units, each of the driving thin film transistor units has a wiring side and a capacitor side, and any two adjacent driving thin film transistor units are arranged at intervals and connected in series; and A plurality of first capacitor regions, each of the first capacitor regions is disposed between the capacitor sides of two adjacent driving thin film transistor units.
  • the driving thin film transistor unit is rectangular, the wiring side is located on the short side of the rectangle, and the capacitor side is located on the long side of the rectangle.
  • the GOA circuit layout further includes a series line, which is arranged on the wiring side of the driving thin film transistor unit, and any two adjacent driving thin film transistor units pass through the series line Connect each other in series.
  • each of the driving thin film transistor units has two channels, the length direction of the channels is parallel to the capacitor side, and two adjacent first capacitor regions have two channels.
  • the spacing is greater than or equal to the width of the two channels.
  • the width of the channel is adjustable.
  • each of the driving thin film transistor units further has a source side and a drain side, which are located on the wiring side.
  • the GOA circuit layout further includes a plurality of second capacitor regions, and each of the second capacitor regions is disposed on the source side and is connected to the source side through the source side.
  • the first capacitance area is a plurality of second capacitor regions.
  • the drive thin film transistor units connected in series with each other include the drive thin film transistor units located at both ends of the series structure and the drive thin film transistor units located in the middle of the series structure, and are located at two ends of the series structure.
  • the driving thin film transistor unit at the end has a channel, and the length direction of the channel is parallel to the capacitor side.
  • the GOA circuit layout further includes a plurality of second capacitor regions, and each of the second capacitor regions is disposed on the drain side and is connected to the drain side through the drain side.
  • the first capacitance area is a plurality of second capacitor regions.
  • the GOA circuit layout provided by the present invention increases the heat dissipation area of the driving thin film transistor and is more conducive to heat dissipation. On the other hand, due to the full utilization of the first capacitor area, the layout size is basically not increased.
  • FIG. 1 is a schematic diagram of the layout relationship between driving thin film transistors and capacitors in the existing GOA circuit layout.
  • FIG. 2 is a schematic diagram of the layout relationship between the driving thin film transistor and the capacitor in the GOA circuit layout of the present invention.
  • FIG. 3 is a schematic diagram of the GOA circuit layout of the first embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the GOA circuit layout of the second embodiment of the present invention.
  • the present invention addresses the technical problem of insufficient heat dissipation effect of the existing GOA circuit layout, and this embodiment can solve this defect.
  • the present invention divides the driving thin film transistor area 1 into a series structure of a plurality of driving thin film transistor units 1', and each smaller driving thin film transistor
  • the capacitor area 2 is inserted between the cells 1', so that the capacitor area 2 can be reasonably used to divide the driving thin film transistor area 1, and the heat dissipation area of the driving thin film transistor area 1 can be increased to realize the heat dissipation function.
  • the GOA circuit layout includes: a plurality of driving thin film transistor units 1', each of the driving thin film transistor units 1'has a wiring side 11 and a capacitor side 12 , Any two adjacent driving thin film transistor units 1'are arranged at intervals and connected in series; and a plurality of capacitor regions 2, each of the capacitor regions 2 is arranged on the capacitor side 12 of two adjacent driving thin film transistor units 1' between.
  • the driving thin film transistor unit 1' is rectangular, the wiring side 11 is located on the short side of the rectangle, and the capacitor side 12 is located on the long side of the rectangle.
  • the GOA circuit layout further includes a series circuit 3, which is arranged on the wiring side 11 of the driving thin film transistor unit 1', and any two adjacent driving thin film transistor units 1'are connected in series through the series circuit 3.
  • the first capacitor region 2 is inserted between the driving thin film transistor unit 1', and the driving thin film transistor unit 1'is divided into five parts, and each driving thin film transistor unit 1'is connected in series through the wiring side 11
  • the lines 3 are connected in series, which increases the heat dissipation area of the driving thin film transistor unit 1'on the one hand, and is more conducive to heat dissipation.
  • the layout size is not substantially increased.
  • each of the driving thin film transistor units 1' has two channels 13, the length direction of the channels 13 is parallel to the capacitor side 12, and two adjacent first capacitor regions 2 The spacing is greater than or equal to the width of the two channels 13. The width of the channel 13 is adjustable.
  • Each driving thin film transistor unit 1' also has a source side 14 and a drain side 15 located on the wiring side 11.
  • the GOA circuit layout further includes a plurality of second capacitor regions 4, each of the second capacitor regions 4 is disposed on the source side 14, and is connected to the first capacitor region 2 through the source side 14. .
  • FIG. 4 is a schematic diagram of the GOA circuit layout of the second embodiment of the present invention.
  • the first capacitor region 2 is inserted between the driving thin film transistor unit 1', and the driving thin film transistor unit 1'is divided into six parts, each The driving thin film transistor unit 1'is then connected in series with each other through the series circuit 3 on the wiring side 11.
  • the heat dissipation area of the driving thin film transistor unit 1' is increased, which is more conducive to heat dissipation. Utilize, but basically does not increase the layout size.
  • the driving thin film transistor unit 1'connected in series with each other includes the driving thin film transistor unit 1'located at both ends of the series structure and the driving thin film transistor unit 1'located in the middle of the series structure. 1', and the driving thin film transistor unit 1'located at both ends of the series structure has a channel 13, and the length direction of the channel is parallel to the capacitor side.
  • Each driving thin film transistor unit 1' also has a source side 14 and a drain side 15 located on the wiring side 11.
  • the GOA circuit layout further includes a plurality of second capacitor regions 4, each of the second capacitor regions 4 is disposed on the drain side 15 and is connected to the first capacitor region 2 through the drain side 15 .
  • the present invention provides the above Two embodiments.
  • the GOA circuit layout provided by the present invention increases the heat dissipation area of the driving thin film transistor and is more conducive to heat dissipation.
  • the layout size is not substantially increased.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种GOA电路布局，包括多个驱动薄膜晶体管单元（1'），每一所述驱动薄膜晶体管单元（1'）具有走线侧（11）与电容侧（12），任两相邻所述驱动薄膜晶体管单元（1'）间隔设置且彼此串联；及多个第一电容区域（2），每一所述第一电容区域（2）设置于两相邻所述驱动薄膜晶体管单元（1'）的电容侧（12）之间。所述GOA电路布局，增大了驱动薄膜晶体管的散热面积，更有利于散热，另一方面由于第一电容区域（2）的充分利用，而基本没有增大布局尺寸。

Description

一种GOA电路布局 技术领域
本发明涉及显示技术领域，尤其涉及一种GOA电路布局。
 背景技术
随着显示技术的不断发展，人们高对比度，高分辨率，窄边框，薄型化的需求日益强烈。为了实现这一目的，目前液晶显示、有机发光二级管显示等显示技术的主流产品，广泛采用GOA（Gate Driver on Array）驱动电路作为栅极驱动电路，但由于GOA电路采用交流驱动方式，其中部分薄膜晶体管会由于严重的自热效应而失效，特别是尺寸较大的驱动薄膜晶体管。
图1为现有GOA电路布局中驱动薄膜晶体管与电容的布局关系示意图，现有的GOA电路布局将电容区域2独立设置于驱动薄膜晶体管区域1的下方或者右方(图未示)，有散热效果不足的问题。
 技术问题
本发明提供一种GOA电路布局，以解决现有GOA电路布局散热效果不足的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种GOA电路布局，包括多个驱动薄膜晶体管单元，每一所述驱动薄膜晶体管单元具有走线侧与电容侧，任两相邻所述驱动薄膜晶体管单元间隔设置且彼此串联；及多个第一电容区域，每一所述第一电容区域设置于两相邻所述驱动薄膜晶体管单元的电容侧之间。
在本发明的至少一种实施例中，所述驱动薄膜晶体管单元为矩形，所述走线侧位于所述矩形的短边，所述电容侧位于所述矩形的长边。
在本发明的至少一种实施例中，所述GOA电路布局还包括串联线路，设置于所述驱动薄膜晶体管单元的走线侧，且任两相邻所述驱动薄膜晶体管单元通过所述串联线路彼此串联。
在本发明的至少一种实施例中，每一所述驱动薄膜晶体管单元具有两个沟道，所述沟道的长度方向平行于所述电容侧，且两相邻所述第一电容区域的间距大于或等于两个所述沟道的宽度。
在本发明的至少一种实施例中，所述沟道的宽度为可调整。
在本发明的至少一种实施例中，每一所述驱动薄膜晶体管单元还具有源极侧与漏极侧，位于所述走线侧。
在本发明的至少一种实施例中，所述GOA电路布局还包括多个第二电容区域，每一所述第二电容区域设置于所述源极侧，并通过所述源极侧连接于所述第一电容区域。
在本发明的至少一种实施例中，彼此串联的所述驱动薄膜晶体管单元包括位于串联结构两端的所述驱动薄膜晶体管单元与位于串联结构中间的所述驱动薄膜晶体管单元，且位于串联结构两端的所述驱动薄膜晶体管单元具有一个沟道，所述沟道的长度方向平行于所述电容侧。
在本发明的至少一种实施例中，所述GOA电路布局还包括多个第二电容区域，每一所述第二电容区域设置于所述漏极侧，并通过所述漏极侧连接于所述第一电容区域。
 有益效果
本发明提供的GOA电路布局，增大了驱动薄膜晶体管的散热面积，更有利于散热，另一方面由于第一电容区域的充分利用，而基本没有增大布局尺寸。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有GOA电路布局中驱动薄膜晶体管与电容的布局关系示意图。
图2为本发明GOA电路布局中驱动薄膜晶体管与电容的布局关系示意图。
图3为本发明第一实施例的GOA电路布局示意图。
图4为本发明第二实施例的GOA电路布局示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明针对现有GOA电路布局散热效果不足的技术问题，本实施例能够解决该缺陷。
图2为本发明GOA电路布局中驱动薄膜晶体管与电容的布局关系示意图，本发明将驱动薄膜晶体管区域1分成多个驱动薄膜晶体管单元1’的串联结构，并在每个较小的驱动薄膜晶体管单元1’之间插入电容区域2，这样可以合理利用电容区域2分割驱动薄膜晶体管区域1，增大驱动薄膜晶体管区域1的散热面积，实现散热功能。
图3为本发明第一实施例的GOA电路布局示意图，所述GOA电路布局包括：多个驱动薄膜晶体管单元1’，每一所述驱动薄膜晶体管单元1’具有走线侧11与电容侧12，任两相邻所述驱动薄膜晶体管单元1’间隔设置且彼此串联；及多个电容区域2，每一所述电容区域2设置于两相邻所述驱动薄膜晶体管单元1’的电容侧12之间。所述驱动薄膜晶体管单元1’为矩形，所述走线侧11位于所述矩形的短边，所述电容侧12位于所述矩形的长边。所述GOA电路布局还包括串联线路3，设置于所述驱动薄膜晶体管单元1’的走线侧11，且任两相邻所述驱动薄膜晶体管单元1’通过所述串联线路3彼此串联。
如图3所示，第一电容区域2插入驱动薄膜晶体管单元1’之间，将驱动薄膜晶体管单元1’分成了五个部分，每一个驱动薄膜晶体管单元1’再通过走线侧11的串联线路3彼此串联，一方面增大了驱动薄膜晶体管单元1’的散热面积，更有利于散热，另一方面由于第一电容区域2的充分利用，而基本没有增大布局尺寸。
在本实施例中，每一所述驱动薄膜晶体管单元1’具有两个沟道13，所述沟道13的长度方向平行于所述电容侧12，且两相邻所述第一电容区域2的间距大于或等于两个所述沟道13的宽度。所述沟道13的宽度为可调整。每一所述驱动薄膜晶体管单元1’还具有源极侧14与漏极侧15，位于所述走线侧11。所述GOA电路布局还包括多个第二电容区域4，每一所述第二电容区域4设置于所述源极侧14，并通过所述源极侧14连接于所述第一电容区域2。
图4为本发明第二实施例的GOA电路布局示意图，如图所示，第一电容区域2插入驱动薄膜晶体管单元1’之间，将驱动薄膜晶体管单元1’分成了六个部分，每一个驱动薄膜晶体管单元1’再通过走线侧11的串联线路3彼此串联，一方面增大了驱动薄膜晶体管单元1’的散热面积，更有利于散热，另一方面由于第一电容区域2的充分利用，而基本没有增大布局尺寸。
在本实施例中，不同于第一实施例，彼此串联的所述驱动薄膜晶体管单元1’包括位于串联结构两端的所述驱动薄膜晶体管单元1’与位于串联结构中间的所述驱动薄膜晶体管单元1’，且位于串联结构两端的所述驱动薄膜晶体管单元1’具有一个沟道13，所述沟道的长度方向平行于所述电容侧。每一所述驱动薄膜晶体管单元1’还具有源极侧14与漏极侧15，位于所述走线侧11。所述GOA电路布局还包括多个第二电容区域4，每一所述第二电容区域4设置于所述漏极侧15，并通过所述漏极侧15连接于所述第一电容区域2。
由于薄膜晶体管运行过程中漏极电压较高，栅漏极之间的电压差较栅源极之间的电压差小，因此栅漏极之间的电阻较大更易生热，因此本发明提供以上两种实施例。
有益效果：本发明提供的GOA电路布局，增大了驱动薄膜晶体管的散热面积，更有利于散热，另一方面由于第一电容区域2的充分利用，而基本没有增大布局尺寸。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种GOA电路布局，包括：
    多个驱动薄膜晶体管单元，每一所述驱动薄膜晶体管单元具有走线侧与电容侧，任两相邻所述驱动薄膜晶体管单元间隔设置且彼此串联；及
    多个第一电容区域，每一所述第一电容区域设置于两相邻所述驱动薄膜晶体管单元的电容侧之间。
  2. 根据权利要求1所述的GOA电路布局，其中，所述驱动薄膜晶体管单元为矩形，所述走线侧位于所述矩形的短边，所述电容侧位于所述矩形的长边。
  3. 根据权利要求2所述的GOA电路布局，其中，还包括串联线路，设置于所述驱动薄膜晶体管单元的走线侧，且任两相邻所述驱动薄膜晶体管单元通过所述串联线路彼此串联。
  4. 根据权利要求3所述的GOA电路布局，其中，每一所述驱动薄膜晶体管单元具有两个沟道，所述沟道的长度方向平行于所述电容侧，且两相邻所述第一电容区域的间距大于或等于两个所述沟道的宽度。
  5. 根据权利要求4所述的GOA电路布局，其中，所述沟道的宽度为可调整。
  6. 根据权利要求4所述的GOA电路布局，其中，每一所述驱动薄膜晶体管单元还具有源极侧与漏极侧，位于所述走线侧。
  7. 根据权利要求6所述的GOA电路布局，其中，还包括多个第二电容区域，每一所述第二电容区域设置于所述源极侧，并通过所述源极侧连接于所述第一电容区域。
  8. 根据权利要求3所述的GOA电路布局，其中，彼此串联的所述驱动薄膜晶体管单元包括位于串联结构两端的所述驱动薄膜晶体管单元与位于串联结构中间的所述驱动薄膜晶体管单元，且位于串联结构两端的所述驱动薄膜晶体管单元具有一个沟道，所述沟道的长度方向平行于所述电容侧。
  9. 根据权利要求8所述的GOA电路布局，其中，每一所述驱动薄膜晶体管单元还具有源极侧与漏极侧，位于所述走线侧。
  10. 根据权利要求9所述的GOA电路布局，其中，还包括多个第二电容区域，每一所述第二电容区域设置于所述漏极侧，并通过所述漏极侧连接于所述第一电容区域。
  11. 一种GOA电路布局，包括：
    多个驱动薄膜晶体管单元，每一所述驱动薄膜晶体管单元具有走线侧与电容侧，任两相邻所述驱动薄膜晶体管单元间隔设置且彼此串联；
    多个第一电容区域，每一所述第一电容区域设置于两相邻所述驱动薄膜晶体管单元的电容侧之间；及
    串联线路，设置于所述驱动薄膜晶体管单元的走线侧，且任两相邻所述驱动薄膜晶体管单元通过所述串联线路彼此串联。
  12. 根据权利要求11所述的GOA电路布局，其中，所述驱动薄膜晶体管单元为矩形，所述走线侧位于所述矩形的短边，所述电容侧位于所述矩形的长边。
  13. 根据权利要求12所述的GOA电路布局，其中，每一所述驱动薄膜晶体管单元具有两个沟道，所述沟道的长度方向平行于所述电容侧，且两相邻所述第一电容区域的间距大于或等于两个所述沟道的宽度。
  14. 根据权利要求13所述的GOA电路布局，其中，所述沟道的宽度为可调整。
  15. 根据权利要求13所述的GOA电路布局，其中，每一所述驱动薄膜晶体管单元还具有源极侧与漏极侧，位于所述走线侧。
  16. 根据权利要求15所述的GOA电路布局，其中，还包括多个第二电容区域，每一所述第二电容区域设置于所述源极侧，并通过所述源极侧连接于所述第一电容区域。
  17. 根据权利要求11所述的GOA电路布局，其中，彼此串联的所述驱动薄膜晶体管单元包括位于串联结构两端的所述驱动薄膜晶体管单元与位于串联结构中间的所述驱动薄膜晶体管单元，且位于串联结构两端的所述驱动薄膜晶体管单元具有一个沟道，所述沟道的长度方向平行于所述电容侧。
  18. 根据权利要求17所述的GOA电路布局，其中，每一所述驱动薄膜晶体管单元还具有源极侧与漏极侧，位于所述走线侧。
  19. 根据权利要求18所述的GOA电路布局，其中，还包括多个第二电容区域，每一所述第二电容区域设置于所述漏极侧，并通过所述漏极侧连接于所述第一电容区域。
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