CN110675832A - 一种goa电路布局 - Google Patents
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Abstract
一种GOA电路布局,包括多个驱动薄膜晶体管单元,每一所述驱动薄膜晶体管单元具有走线侧与电容侧,任两相邻所述驱动薄膜晶体管单元间隔设置且彼此串联;及多个第一电容区域,每一所述第一电容区域设置于两相邻所述驱动薄膜晶体管单元的电容侧之间。本发明提供的GOA电路布局,增大了驱动薄膜晶体管的散热面积,更有利于散热,另一方面由于第一电容区域的充分利用,而基本没有增大布局尺寸。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种GOA电路布局。
背景技术
随着显示技术的不断发展,人们高对比度,高分辨率,窄边框,薄型化的需求日益强烈。为了实现这一目的,目前液晶显示、有机发光二级管显示等显示技术的主流产品,广泛采用GOA(Gate Driver on Array)驱动电路作为栅极驱动电路,但由于GOA电路采用交流驱动方式,其中部分薄膜晶体管会由于严重的自热效应而失效,特别是尺寸较大的驱动薄膜晶体管。
图1为现有GOA电路布局中驱动薄膜晶体管与电容的布局关系示意图,现有的GOA电路布局将电容区域2独立设置于驱动薄膜晶体管区域1的下方或者右方(图未示),有散热效果不足的问题。
发明内容
本发明提供一种GOA电路布局,以解决现有GOA电路布局散热效果不足的技术问题。
为解决上述问题,本发明提供的技术方案如下:
本发明提供一种GOA电路布局,包括多个驱动薄膜晶体管单元,每一所述驱动薄膜晶体管单元具有走线侧与电容侧,任两相邻所述驱动薄膜晶体管单元间隔设置且彼此串联;及多个第一电容区域,每一所述第一电容区域设置于两相邻所述驱动薄膜晶体管单元的电容侧之间。
在本发明的至少一种实施例中,所述驱动薄膜晶体管单元为矩形,所述走线侧位于所述矩形的短边,所述电容侧位于所述矩形的长边。
在本发明的至少一种实施例中,所述GOA电路布局还包括串联线路,设置于所述驱动薄膜晶体管单元的走线侧,且任两相邻所述驱动薄膜晶体管单元通过所述串联线路彼此串联。
在本发明的至少一种实施例中,每一所述驱动薄膜晶体管单元具有两个沟道,所述沟道的长度方向平行于所述电容侧,且两相邻所述第一电容区域的间距大于或等于两个所述沟道的宽度。
在本发明的至少一种实施例中,所述沟道的宽度为可调整。
在本发明的至少一种实施例中,每一所述驱动薄膜晶体管单元还具有源极侧与漏极侧,位于所述走线侧。
在本发明的至少一种实施例中,所述GOA电路布局还包括多个第二电容区域,每一所述第二电容区域设置于所述源极侧,并通过所述源极侧连接于所述第一电容区域。
在本发明的至少一种实施例中,彼此串联的所述驱动薄膜晶体管单元包括位于串联结构两端的所述驱动薄膜晶体管单元与位于串联结构中间的所述驱动薄膜晶体管单元,且位于串联结构两端的所述驱动薄膜晶体管单元具有一个沟道,所述沟道的长度方向平行于所述电容侧。
在本发明的至少一种实施例中,所述GOA电路布局还包括多个第二电容区域,每一所述第二电容区域设置于所述漏极侧,并通过所述漏极侧连接于所述第一电容区域。
本发明的有益效果为:本发明提供的GOA电路布局,增大了驱动薄膜晶体管的散热面积,更有利于散热,另一方面由于第一电容区域的充分利用,而基本没有增大布局尺寸。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍,显而易见地,下面描述中的附图仅仅是发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为现有GOA电路布局中驱动薄膜晶体管与电容的布局关系示意图;
图2为本发明GOA电路布局中驱动薄膜晶体管与电容的布局关系示意图;
图3为本发明第一实施例的GOA电路布局示意图;
图4为本发明第二实施例的GOA电路布局示意图。
具体实施方式
以下各实施例的说明是参考附加的图示,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。在图中,结构相似的单元是用以相同标号表示。
本发明针对现有GOA电路布局散热效果不足的技术问题,本实施例能够解决该缺陷。
图2为本发明GOA电路布局中驱动薄膜晶体管与电容的布局关系示意图,本发明将驱动薄膜晶体管区域1分成多个驱动薄膜晶体管单元1’的串联结构,并在每个较小的驱动薄膜晶体管单元1’之间插入电容区域2,这样可以合理利用电容区域2分割驱动薄膜晶体管区域1,增大驱动薄膜晶体管区域1的散热面积,实现散热功能。
图3为本发明第一实施例的GOA电路布局示意图,所述GOA电路布局包括:多个驱动薄膜晶体管单元1’,每一所述驱动薄膜晶体管单元1’具有走线侧11与电容侧12,任两相邻所述驱动薄膜晶体管单元1’间隔设置且彼此串联;及多个电容区域2,每一所述电容区域2设置于两相邻所述驱动薄膜晶体管单元1’的电容侧12之间。所述驱动薄膜晶体管单元1’为矩形,所述走线侧11位于所述矩形的短边,所述电容侧12位于所述矩形的长边。所述GOA电路布局还包括串联线路3,设置于所述驱动薄膜晶体管单元1’的走线侧11,且任两相邻所述驱动薄膜晶体管单元1’通过所述串联线路3彼此串联。
如图3所示,第一电容区域2插入驱动薄膜晶体管单元1’之间,将驱动薄膜晶体管单元1’分成了五个部分,每一个驱动薄膜晶体管单元1’再通过走线侧11的串联线路3彼此串联,一方面增大了驱动薄膜晶体管单元1’的散热面积,更有利于散热,另一方面由于第一电容区域2的充分利用,而基本没有增大布局尺寸。
在本实施例中,每一所述驱动薄膜晶体管单元1’具有两个沟道13,所述沟道13的长度方向平行于所述电容侧12,且两相邻所述第一电容区域2的间距大于或等于两个所述沟道13的宽度。所述沟道13的宽度为可调整。每一所述驱动薄膜晶体管单元1’还具有源极侧14与漏极侧15,位于所述走线侧11。所述GOA电路布局还包括多个第二电容区域4,每一所述第二电容区域4设置于所述源极侧14,并通过所述源极侧14连接于所述第一电容区域2。
图4为本发明第二实施例的GOA电路布局示意图,如图所示,第一电容区域2插入驱动薄膜晶体管单元1’之间,将驱动薄膜晶体管单元1’分成了六个部分,每一个驱动薄膜晶体管单元1’再通过走线侧11的串联线路3彼此串联,一方面增大了驱动薄膜晶体管单元1’的散热面积,更有利于散热,另一方面由于第一电容区域2的充分利用,而基本没有增大布局尺寸。
在本实施例中,不同于第一实施例,彼此串联的所述驱动薄膜晶体管单元1’包括位于串联结构两端的所述驱动薄膜晶体管单元1’与位于串联结构中间的所述驱动薄膜晶体管单元1’,且位于串联结构两端的所述驱动薄膜晶体管单元1’具有一个沟道13,所述沟道的长度方向平行于所述电容侧。每一所述驱动薄膜晶体管单元1’还具有源极侧14与漏极侧15,位于所述走线侧11。所述GOA电路布局还包括多个第二电容区域4,每一所述第二电容区域4设置于所述漏极侧15,并通过所述漏极侧15连接于所述第一电容区域2。
由于薄膜晶体管运行过程中漏极电压较高,栅漏极之间的电压差较栅源极之间的电压差小,因此栅漏极之间的电阻较大更易生热,因此本发明提供以上两种实施例。
有益效果:本发明提供的GOA电路布局,增大了驱动薄膜晶体管的散热面积,更有利于散热,另一方面由于第一电容区域2的充分利用,而基本没有增大布局尺寸。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。
Claims (10)
1.一种GOA电路布局,其特征在于,包括:
多个驱动薄膜晶体管单元,每一所述驱动薄膜晶体管单元具有走线侧与电容侧,任两相邻所述驱动薄膜晶体管单元间隔设置且彼此串联;及
多个第一电容区域,每一所述第一电容区域设置于两相邻所述驱动薄膜晶体管单元的电容侧之间。
2.根据权利要求1所述的GOA电路布局,其特征在于,所述驱动薄膜晶体管单元为矩形,所述走线侧位于所述矩形的短边,所述电容侧位于所述矩形的长边。
3.根据权利要求2所述的GOA电路布局,其特征在于,还包括串联线路,设置于所述驱动薄膜晶体管单元的走线侧,且任两相邻所述驱动薄膜晶体管单元通过所述串联线路彼此串联。
4.根据权利要求3所述的GOA电路布局,其特征在于,每一所述驱动薄膜晶体管单元具有两个沟道,所述沟道的长度方向平行于所述电容侧,且两相邻所述第一电容区域的间距大于或等于两个所述沟道的宽度。
5.根据权利要求4所述的GOA电路布局,其特征在于,所述沟道的宽度为可调整。
6.根据权利要求4所述的GOA电路布局,其特征在于,每一所述驱动薄膜晶体管单元还具有源极侧与漏极侧,位于所述走线侧。
7.根据权利要求6所述的GOA电路布局,其特征在于,还包括多个第二电容区域,每一所述第二电容区域设置于所述源极侧,并通过所述源极侧连接于所述第一电容区域。
8.根据权利要求3所述的GOA电路布局,其特征在于,彼此串联的所述驱动薄膜晶体管单元包括位于串联结构两端的所述驱动薄膜晶体管单元与位于串联结构中间的所述驱动薄膜晶体管单元,且位于串联结构两端的所述驱动薄膜晶体管单元具有一个沟道,所述沟道的长度方向平行于所述电容侧。
9.根据权利要求8所述的GOA电路布局,其特征在于,每一所述驱动薄膜晶体管单元还具有源极侧与漏极侧,位于所述走线侧。
10.根据权利要求9所述的GOA电路布局,其特征在于,还包括多个第二电容区域,每一所述第二电容区域设置于所述漏极侧,并通过所述漏极侧连接于所述第一电容区域。
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