WO2021022694A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2021022694A1
WO2021022694A1 PCT/CN2019/115848 CN2019115848W WO2021022694A1 WO 2021022694 A1 WO2021022694 A1 WO 2021022694A1 CN 2019115848 W CN2019115848 W CN 2019115848W WO 2021022694 A1 WO2021022694 A1 WO 2021022694A1
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WO
WIPO (PCT)
Prior art keywords
metal layer
metal
insulating layer
gate
array substrate
Prior art date
Application number
PCT/CN2019/115848
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English (en)
French (fr)
Inventor
奚苏萍
王添鸿
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Filing date
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/621,265 priority Critical patent/US20210408050A1/en
Publication of WO2021022694A1 publication Critical patent/WO2021022694A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

Definitions

  • This application relates to the field of display technology, in particular to an array substrate and a display panel.
  • Gate Driver On Array is to use the existing thin-film transistor liquid crystal display's array substrate manufacturing process to fabricate the gate row scan driving signal circuit on the array substrate to realize the driving mode of the gate progressive scan.
  • GOA technology can realize product narrow border or even borderless design, which can increase customer process design options and expand product application fields (for example, public mosaic display field).
  • product application fields for example, public mosaic display field.
  • the existing display panel cannot achieve a narrower frame because the GOA driving circuit occupies a large area.
  • the purpose of the embodiments of the present application is to provide an array substrate and a display panel, which can solve the technical problem that the existing display panel occupies a large area due to the GOA driving circuit, and thus cannot achieve a narrower frame.
  • An embodiment of the present application provides an array substrate.
  • the array substrate is provided with a GOA drive circuit and a plurality of pixel units.
  • the GOA drive circuit includes a bootstrap capacitor and a first thin film transistor.
  • the pixel unit includes a The second thin film transistor, the array substrate includes:
  • a first metal layer, the first metal layer is disposed on the substrate, and the first metal layer forms the first gate of the first thin film transistor and the second gate of the second thin film transistor;
  • a first insulating layer the first insulating layer being disposed on the first metal layer and the substrate;
  • a second metal layer, the second metal layer is disposed on the first insulating layer, the second metal layer forms a scan line, a first connection metal, and a first drain electrode of the first thin film transistor; A first drain, the first connecting metal, and one end of the scan line are connected in sequence, and the other end of the scan line is connected with the second gate;
  • a second insulating layer the second insulating layer being disposed on the second metal layer
  • a third metal layer, the third metal layer is disposed on the second insulating layer, the third metal layer is electrically connected to the first gate, and the third metal layer is connected to the first connecting metal
  • the opposite part forms the bootstrap capacitor
  • the first metal layer is further formed with a common electrode line, the common electrode line is electrically connected to the pixel unit; the first insulating layer is provided with at least one fourth metalized hole, and the scan line passes through the second The four metallized holes are electrically connected to the second gate.
  • a part of the first connecting metal is opposite to the common electrode line.
  • the third metal layer includes a first area and a second area that are connected to each other, and the first area and the first connection metal have the same shape and size and are opposite to each other, The second region is electrically connected to the first gate.
  • the second area is electrically connected to the first gate through a third metallized hole penetrating the first insulating layer and the second insulating layer.
  • the second metal layer is further formed with a second connecting metal
  • the first insulating layer is provided with at least one first metallized hole
  • the second insulating layer is provided with at least one A second metallized hole, the second region, the second metallized hole, the second connecting metal, the first metallized hole and the first gate are electrically connected in sequence.
  • the at least one first metalized hole includes a plurality of first metalized holes arranged in a rectangular array; the at least one second metalized hole includes a plurality of rectangular arrays. The second metalized hole of the cloth.
  • the at least one fourth metallized hole includes a plurality of fourth metallized holes arranged in a rectangular array.
  • An embodiment of the present application also provides an array substrate on which a GOA drive circuit and a plurality of pixel units are provided, the GOA drive circuit includes a bootstrap capacitor and a first thin film transistor, and the pixel unit includes a The second thin film transistor; the array substrate includes:
  • a first metal layer, the first metal layer is disposed on the substrate, and the first metal layer forms the first gate of the first thin film transistor and the second gate of the second thin film transistor;
  • a first insulating layer the first insulating layer being disposed on the first metal layer and the substrate;
  • a second metal layer, the second metal layer is disposed on the first insulating layer, the second metal layer forms a scan line, a first connection metal, and a first drain electrode of the first thin film transistor; A first drain, the first connecting metal, and one end of the scan line are connected in sequence, and the other end of the scan line is connected with the second gate;
  • a second insulating layer the second insulating layer being disposed on the second metal layer
  • a third metal layer, the third metal layer is disposed on the second insulating layer, the third metal layer is electrically connected to the first gate, and the third metal layer is connected to the first connecting metal
  • the opposite part forms the bootstrap capacitor.
  • the first metal layer is further formed with a common electrode line, and the common electrode line is electrically connected to the pixel unit.
  • a part of the first connecting metal is opposite to the common electrode line.
  • the third metal layer includes a first area and a second area that are connected to each other, and the first area and the first connection metal have the same shape and size and are opposite to each other, The second region is electrically connected to the first gate.
  • the second area is electrically connected to the first gate through a third metallized hole penetrating the first insulating layer and the second insulating layer.
  • the second metal layer is further formed with a second connecting metal
  • the first insulating layer is provided with at least one first metallized hole
  • the second insulating layer is provided with at least one A second metallized hole, the second region, the second metallized hole, the second connecting metal, the first metallized hole and the first gate are electrically connected in sequence.
  • the at least one first metalized hole includes a plurality of first metalized holes arranged in a rectangular array; the at least one second metalized hole includes a plurality of rectangular arrays. The second metalized hole of the cloth.
  • the first insulating layer is provided with at least one fourth metallized hole, and the scan line is electrically connected to the second gate through the fourth metallized hole.
  • the at least one fourth metallized hole includes a plurality of fourth metallized holes arranged in a rectangular array.
  • the present application also provides a display panel, which includes an array substrate on which a GOA drive circuit and a plurality of pixel units are arranged, and the GOA drive circuit includes a bootstrap capacitor and a first thin film transistor.
  • the pixel unit includes a second thin film transistor, and the array substrate includes:
  • a first metal layer, the first metal layer is disposed on the substrate, and the first metal layer forms the first gate of the first thin film transistor and the second gate of the second thin film transistor;
  • a first insulating layer the first insulating layer being disposed on the first metal layer and the substrate;
  • a second metal layer, the second metal layer is disposed on the first insulating layer, the second metal layer forms a scan line, a first connection metal, and a first drain electrode of the first thin film transistor; A first drain, the first connecting metal, and one end of the scan line are connected in sequence, and the other end of the scan line is connected with the second gate;
  • a second insulating layer the second insulating layer being disposed on the second metal layer
  • a third metal layer, the third metal layer is disposed on the second insulating layer, the third metal layer is electrically connected to the first gate, and the third metal layer is connected to the first connecting metal
  • the opposite part forms the bootstrap capacitor.
  • the first metal layer is further formed with a common electrode line, and the common electrode line is electrically connected to the pixel unit.
  • a part of the first connecting metal is opposite to the common electrode line.
  • the third metal layer includes a first area and a second area that are connected to each other, and the first area and the first connection metal have the same shape and size and are opposite to each other, The second region is electrically connected to the first gate.
  • a third metal layer opposite to the first connecting metal is provided on the third insulating layer, so that the first connecting metal and the third metal layer form a bootstrap capacitor without extending the first
  • the width of a metal layer is used to form a bootstrap capacitor with the first connecting metal, so that the area occupied by the GOA driving circuit can be reduced, thereby achieving a narrower frame.
  • FIG. 1 is a schematic plan view of an array substrate provided by an embodiment of the application.
  • FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a partial area of an array substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of another structure of an array substrate provided by an embodiment of the application.
  • first and second are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more features. In the description of this application, “multiple articles” means two or more than two unless otherwise specifically defined.
  • FIG. 1 is a schematic plan view of an array substrate provided by an embodiment of the application. From a plane layout perspective, the array substrate includes a substrate 10 and a GOA driving circuit 101 and a plurality of pixel units 102 disposed on the substrate 10.
  • the substrate 10 includes a display area 12 and a non-display area 11, and the non-display area 11 is arranged around the display area 12.
  • the GOA driving circuit 101 is disposed in the non-display area 11, and the plurality of pixel units 102 are disposed in the display area 12.
  • the circuit principle of the GOA drive circuit 101 is the same as that of the GOA drive circuit in the prior art, including a pull-up control module, a pull-up maintenance module, a pull-up module, a bootstrap capacitor, a pull-down control module, a pull-down module, etc. It is a very mature existing technology and does not need to be described too much.
  • the pull-up control module generally uses a field-effect thin film transistor, which is the first thin film transistor in the present invention.
  • the bootstrap capacitor is formed by using two layers of metal blocks facing each other, and the formation of the bootstrap capacitor will be described in detail later.
  • the pixel unit 102 has the same structure as the pixel unit in the prior art, and both include a second thin film transistor for controlling the switch of the entire pixel unit 102 and other components.
  • the pixel unit 102 further includes a storage capacitor, a light-emitting element, etc., which are all existing technologies and need not be described too much.
  • FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the application
  • FIG. 3 is a schematic structural diagram of a partial area of an array substrate provided by an embodiment of the application.
  • the array substrate includes a substrate 10, but also a first metal layer 20, a first insulating layer 30, a second metal layer 40, a second insulating layer 50, and a third metal layer 60.
  • a semiconductor layer is also provided therein, and the position of the semiconductor layer is not specifically limited.
  • the first metal layer 20, the first insulating layer 30, the second metal layer 40, the second insulating layer 50, the third metal layer 60 and the semiconductor layer respectively form a GOA driving circuit located in the non-display area 11 through multiple photomask processes. 101 and a plurality of pixel units 102 located in the display area 12.
  • the substrate 10 is a glass substrate, of course, a substrate of other materials can also be used.
  • the first metal layer 20 is deposited on the substrate 10.
  • the first metal layer 10 uses a photomask process to form the first gate 22 of the first thin film transistor, the second gate 21 of the second thin film transistor and the common electrode line. twenty three.
  • the common electrode line 23 is electrically connected to each pixel unit 102 for providing a common voltage to each pixel unit 102.
  • the first gate 22 and the common electrode line 23 are in the non-display area 12, and the second gate 21 is in the display area 11.
  • the first insulating layer 30 is disposed on the first metal layer 20 and the substrate 10; the first insulating layer 30 is formed by deposition of silicon nitride or silicon dioxide.
  • the second metal layer 40 is disposed on the first insulating layer 30, and the second metal layer 30 uses a photomask process to form the scan line 41, the first connection metal 46, and the first drain of the first thin film transistor.
  • the first drain 42, the first connecting metal 46 and one end of the scan line 41 are connected in sequence, and the other end of the scan line 41 is connected to the second gate 21.
  • a part of the first connection metal 46 is opposed to the common electrode line 23.
  • the first connecting metal 46, the first drain 42 and the first source 43 are all located in the non-display area 12.
  • the first thin film transistor also includes a first semiconductor layer located in the non-display area 12 and a correspondingly formed first channel structure, which is the prior art and need not be described too much.
  • the second thin film transistor also includes a second source electrode and a second drain electrode formed on the display area 11 and a corresponding channel structure, which are not shown in the figure, which is a prior art and need not be described too much.
  • the second source electrode and the second drain electrode are usually formed by the second metal layer 40 using a photomask process.
  • the second insulating layer 50 is disposed on the second metal layer 40 and the first insulating layer 30; the second insulating layer 50 is formed by deposition of silicon nitride or silicon dioxide.
  • the third metal layer 60 is disposed on the second insulating layer 50, the third metal layer 60 is electrically connected to the first gate 22, and the portion of the third metal layer 60 opposite to the first connecting metal 46 forms a bootstrap capacitor Cb.
  • the third metal layer 60 is made of ITO metal. Of course, other transparent metal materials can also be used.
  • the third metal layer 60 includes a first area 61 and a second area 62 that are connected to each other.
  • the first area 61 and the first connecting metal 46 have the same shape and size and are opposite to each other.
  • 62 is electrically connected to the first gate 22.
  • the first region 61 and the first connecting metal 46 form the bootstrap capacitor Cb in the GOA driving circuit mentioned above. Both the first region 61 and the first connecting metal 46 are located directly above the common electrode line 23.
  • the second region 62 of the third metal layer 60 is electrically connected to the first gate 22 through the third metallized hole 53 penetrating the first insulating layer 30 and the second insulating layer 50.
  • the number of the third metallization holes 53 may be one or more.
  • a plurality of third metallization holes 53 evenly arranged are used to realize the connection with the second region 62 and the first gate 22 The electrical connection to improve the stability of the connection.
  • the second region 62 of the third metal layer 60 and the first gate 22 may also be electrically connected by other structures.
  • the second metal layer 40 is further formed with a second connecting metal 44
  • the first insulating layer 30 is provided with at least one first metallized hole 32
  • the second insulating layer 50 is provided with At least one second metallization hole 51
  • the second region 62, the second metallization hole 51, the second connection metal 44, the first metallization hole 32 and the first gate 22 are electrically connected in sequence.
  • the first region 61 and the first connecting metal 46 form the bootstrap capacitor Cb.
  • the at least one first metalized hole 32 includes a plurality of first metalized holes 32 arranged in a rectangular array; the at least one second metalized hole 51 includes a plurality of first metalized holes 32 arranged in a rectangular array. Two metallized holes 51 to improve the stability of the connection.
  • the first insulating layer 30 is provided with at least one fourth metallized hole 31, and the scan line 41 is electrically connected to the second gate 21 through the fourth metallized hole 31.
  • the at least one fourth metallized hole 31 includes a plurality of fourth metallized holes 31 arranged in a rectangular array, thereby improving the stability of electrical connection.
  • the present invention also provides a display panel, which includes the array substrate in any of the foregoing embodiments.
  • a third metal layer opposite to the first connecting metal is provided on the third insulating layer, so that the first connecting metal and the third metal layer form a bootstrap capacitor without extending the first
  • the width of a metal layer is used to form a bootstrap capacitor with the first connecting metal, so that the area occupied by the GOA driving circuit can be reduced, thereby achieving a narrower frame.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

本申请提供一种阵列基板及显示面板，该阵列基板包括：一基板；第一金属层；第一绝缘层；第二金属层，设置在第一绝缘层上，第二金属层形成扫描线、第一连接金属以及第一薄膜晶体管的第一漏极；第二绝缘层；第三金属层，设置在第二绝缘层上，第三金属层与第一栅极电连接，第三金属层与第一连接金属相对的部分形成自举电容。

Description

阵列基板及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及显示面板。
 背景技术
Gate Driver On Array，简称GOA，也就是利用现有薄膜晶体管液晶显示器中的阵列基板制程将栅极行扫描驱动信号电路制作在阵列基板上，实现对栅极逐行扫描的驱动方式。
 GOA技术可实现产品窄边框甚至无边框设计，可以增加客户工艺设计选择，扩展产品应用领域(例如，公用拼接显示领域)。然而，现有的显示面板由于GOA驱动电路占用较大面积，从而无法实现更窄边框。
 技术问题
本申请实施例的目的在于提供一种阵列基板及显示面板，能够解决现有的显示面板由于GOA驱动电路占用较大面积，从而无法实现更窄边框的技术问题。
 技术解决方案
本申请实施例提供一种阵列基板，，所述阵列基板上设置有GOA驱动电路以及多个像素单元，所述GOA驱动电路包括一自举电容以及一第一薄膜晶体管，所述像素单元包括一第二薄膜晶体管，所述阵列基板包括：
一基板；
第一金属层，所述第一金属层设置在所述基板上，所述第一金属层形成所述第一薄膜晶体管的第一栅极以及所述第二薄膜晶体管的第二栅极；
第一绝缘层，所述第一绝缘层设置在所述第一金属层以及所述基板上；
第二金属层，所述第二金属层设置在所述第一绝缘层上，所述第二金属层形成扫描线、第一连接金属以及所述第一薄膜晶体管的第一漏极，所述第一漏极、所述第一连接金属以及所述扫描线的一端依次连接，所述扫描线的另一端与所述第二栅极连接；
第二绝缘层，所述第二绝缘层设置在所述第二金属层上；
第三金属层，所述第三金属层设置在所述第二绝缘层上，所述第三金属层与所述第一栅极电连接，所述第三金属层与所述第一连接金属相对的部分形成所述自举电容；
所述第一金属层还形成有公共电极线，所述公共电极线与所述像素单元电连接；所述第一绝缘层设置有至少一个第四金属化孔，所述扫描线通过所述第四金属化孔与所述第二栅极电连接。
在本申请所述的阵列基板中，所述第一连接金属的局部与所述公共电极线相对。
在本申请所述的阵列基板中，所述第三金属层包括相互连接的第一区域以及第二区域，所述第一区域与所述第一连接金属的形状以及尺寸相同且相互正对，所述第二区域与所述第一栅极电连接。
在本申请所述的阵列基板中，所述第二区域通过贯穿所述第一绝缘层以及所述第二绝缘层的第三金属化孔与所述第一栅极电连接。
在本申请所述的阵列基板中，所述第二金属层还形成有第二连接金属，所述第一绝缘层设置有至少一个第一金属化孔，所述第二绝缘层设置有至少一个第二金属化孔，所述第二区域、所述第二金属化孔、所述第二连接金属、所述第一金属化孔以及所述第一栅极依次电连接。
在本申请所述的阵列基板中，所述至少一个第一金属化孔包括多个呈矩形阵列排布的第一金属化孔；所述至少一个第二金属化孔包括多个呈矩形阵列排布的第二金属化孔。
在本申请所述的阵列基板中，所述至少一个第四金属化孔包括多个呈矩形阵列排布的第四金属化孔。
本申请实施例还提供一种阵列基板，所述阵列基板上设置有GOA驱动电路以及多个像素单元，所述GOA驱动电路包括一自举电容以及一第一薄膜晶体管，所述像素单元包括一第二薄膜晶体管；所述阵列基板包括：
一基板；
第一金属层，所述第一金属层设置在所述基板上，所述第一金属层形成所述第一薄膜晶体管的第一栅极以及所述第二薄膜晶体管的第二栅极；
第一绝缘层，所述第一绝缘层设置在所述第一金属层以及所述基板上；
第二金属层，所述第二金属层设置在所述第一绝缘层上，所述第二金属层形成扫描线、第一连接金属以及所述第一薄膜晶体管的第一漏极，所述第一漏极、所述第一连接金属以及所述扫描线的一端依次连接，所述扫描线的另一端与所述第二栅极连接；
第二绝缘层，所述第二绝缘层设置在所述第二金属层上；
第三金属层，所述第三金属层设置在所述第二绝缘层上，所述第三金属层与所述第一栅极电连接，所述第三金属层与所述第一连接金属相对的部分形成所述自举电容。
在本申请所述的阵列基板中，所述第一金属层还形成有公共电极线，所述公共电极线与所述像素单元电连接。
在本申请所述的阵列基板中，所述第一连接金属的局部与所述公共电极线相对。
在本申请所述的阵列基板中，所述第三金属层包括相互连接的第一区域以及第二区域，所述第一区域与所述第一连接金属的形状以及尺寸相同且相互正对，所述第二区域与所述第一栅极电连接。
在本申请所述的阵列基板中，所述第二区域通过贯穿所述第一绝缘层以及所述第二绝缘层的第三金属化孔与所述第一栅极电连接。
在本申请所述的阵列基板中，所述第二金属层还形成有第二连接金属，所述第一绝缘层设置有至少一个第一金属化孔，所述第二绝缘层设置有至少一个第二金属化孔，所述第二区域、所述第二金属化孔、所述第二连接金属、所述第一金属化孔以及所述第一栅极依次电连接。
在本申请所述的阵列基板中，所述至少一个第一金属化孔包括多个呈矩形阵列排布的第一金属化孔；所述至少一个第二金属化孔包括多个呈矩形阵列排布的第二金属化孔。
在本申请所述的阵列基板中，所述第一绝缘层设置有至少一个第四金属化孔，所述扫描线通过所述第四金属化孔与所述第二栅极电连接。
在本申请所述的阵列基板中，所述至少一个第四金属化孔包括多个呈矩形阵列排布的第四金属化孔。
本申请还提供了一种显示面板，其包括阵列基板，所述阵列基板上设置有GOA驱动电路以及多个像素单元，所述GOA驱动电路包括一自举电容以及一第一薄膜晶体管，所述像素单元包括一第二薄膜晶体管，所述阵列基板包括：
一基板；
第一金属层，所述第一金属层设置在所述基板上，所述第一金属层形成所述第一薄膜晶体管的第一栅极以及所述第二薄膜晶体管的第二栅极；
第一绝缘层，所述第一绝缘层设置在所述第一金属层以及所述基板上；
第二金属层，所述第二金属层设置在所述第一绝缘层上，所述第二金属层形成扫描线、第一连接金属以及所述第一薄膜晶体管的第一漏极，所述第一漏极、所述第一连接金属以及所述扫描线的一端依次连接，所述扫描线的另一端与所述第二栅极连接；
第二绝缘层，所述第二绝缘层设置在所述第二金属层上；
第三金属层，所述第三金属层设置在所述第二绝缘层上，所述第三金属层与所述第一栅极电连接，所述第三金属层与所述第一连接金属相对的部分形成所述自举电容。
在本申请所述的显示面板中，所述第一金属层还形成有公共电极线，所述公共电极线与所述像素单元电连接。
在本申请所述的显示面板中，所述第一连接金属的局部与所述公共电极线相对。
在本申请所述的显示面板中，所述第三金属层包括相互连接的第一区域以及第二区域，所述第一区域与所述第一连接金属的形状以及尺寸相同且相互正对，所述第二区域与所述第一栅极电连接。
 有益效果
本申请实施例的阵列基板及显示面板，通过在第三绝缘层上设置一个与第一连接金属相对的第三金属层，使得第一连接金属与第三金属层形成自举电容，无需延长第一金属层的宽度来与第一连接金属形成自举电容，从而可以缩减GOA驱动电路占用的面积，进而实现更窄边框。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的平面示意图；
图2为本申请实施例提供的阵列基板的结构示意图；
图3本申请实施例提供的阵列基板的的局部区域的结构示意图；以及
图4为本申请实施例提供的阵列基板的另一结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个特征。在本申请的描述中，“多条”的含义是两条或两条以上，除非另有明确具体的限定。
请参阅图1，图1为本申请实施例提供的阵列基板的平面示意图。从平面布局层面来讲，该阵列基板包括基板10以及设置于基板10上的GOA驱动电路101以及多个像素单元102。其中，该基板10包括显示区域12以及非显示区域11，该非显示区域11围绕该显示区域12设置。其中，该GOA驱动电路101设置于该非显示区域11，该多个像素单元102设置于该显示区域12。
其中，该GOA驱动电路101的电路原理与现有技术中的GOA驱动电路相同，均包括上拉控制模块、上拉维持模块、上拉模块、自举电容、下拉控制模块以及下拉模块等，其为很成熟的现有技术，无需对其进行过多描述。其中，该上拉控制模块一般采用场效应薄膜晶体管，在本发明中，其为第一薄膜晶体管。该自举电容为采用两层的金属块正对形成的，后续会对该自举电容的形成进行详细描述。其中，该像素单元102与现有技术中的像素单元的结构相同，均包括用于控制整个像素单元102的开关的第二薄膜晶体管以及其他的元器件。例如，像素单元102还包括存储电容、发光元件等，均为现有技术，无需过多描述。
具体地，请同时参阅图2以及图3，图2为本申请实施例提供的阵列基板的结构示意图，图3本申请实施例提供的阵列基板的的局部区域的结构示意图。
从竖直层状结构来讲，该阵列基板除了包括一基板10，还包括第一金属层20、第一绝缘层30、第二金属层40、第二绝缘层50以及第三金属层60。当然，其中还设置有半导体层，半导体层的位置不具体限定。该第一金属层20、第一绝缘层30、第二金属层40、第二绝缘层50第三金属层60以及半导体层分别通过多次光罩工艺形成了位于非显示区域11的GOA驱动电路101以及位于显示区域12的多个像素单元102。
其中，该基板10为玻璃基板，当然也可以采用其他材料的基板。
其中，第一金属层20沉积在基板10上，该第一金属层10采用光罩工艺形成了第一薄膜晶体管的第一栅极22、第二薄膜晶体管的第二栅极21以及公共电极线23。公共电极线23与每一像素单元102电连接，以用于给每一像素单元102提供公共电压。其中，该第一栅极22以及公共电极线23在非显示区域12，该第二栅极21在显示区域11。
其中，在一些实施例中，第一绝缘层30设置在第一金属层20以及基板10上；第一绝缘层30采用氮化硅或者二氧化硅沉积形成。
其中，在一些实施例中，第二金属层40设置在第一绝缘层30上，第二金属层30采用光罩工艺形成扫描线41、第一连接金属46以及第一薄膜晶体管的第一漏极42以及第一薄膜晶体管的第一源极43。第一漏极42、第一连接金属46以及扫描线41的一端依次连接，扫描线41的另一端与第二栅极21连接。第一连接金属46的局部与公共电极线23相对。其中，该第一连接金属46、第一漏极42以及第一源极43均位于非显示区域12。
当然，可以理解地，第一薄膜晶体管还包括位于非显示区域12的第一半导体层以及对应形成的第一沟道结构，其为现有技术无需过多描述。第二薄膜晶体管还包括形成的位于显示区域11上的第二源极和第二漏极以及对应的沟道结构，图中未画出，其为现有技术，无需过多描述。第二源极和第二漏极通常情况下，也是由该第二金属层40采用光罩工艺形成的。
其中，第二绝缘层50设置在第二金属层40上以及第一绝缘层30上；第二绝缘层50采用氮化硅或者二氧化硅沉积形成。
其中，第三金属层60设置在第二绝缘层50上，第三金属层60与第一栅极22电连接，第三金属层60与第一连接金属46相对的部分形成自举电容Cb。第三金属层60采用ITO金属制成，当然，也可以采用其他透明金属材料。
具体地，在一些实施例中，第三金属层60包括相互连接的第一区域61以及第二区域62，第一区域61与第一连接金属46形状以及尺寸相同且相互正对，第二区域62与第一栅极22电连接。第一区域61与第一连接金属46形成了上述提到的GOA驱动电路中的自举电容Cb。第一区域61与第一连接金属46均位于该公共电极线23的正上方。
其中，在本实施例中，第三金属层60的第二区域62通过贯穿第一绝缘层30以及第二绝缘层50的第三金属化孔53与第一栅极22电连接。第三金属化孔53的数量可以为一个，也可以为多个，在本实施例中，采用多个均匀排布的第三金属化孔53来实现与第二区域62与第一栅极22的电连接，以提高连接的稳定性。
在另一些实施例中，该第三金属层60的第二区域62与第一栅极22还可以通过其他结构来实现电连接。请参照图4，在本实施例中，该第二金属层40还形成有第二连接金属44，该第一绝缘层30设置有至少一个第一金属化孔32，第二绝缘层50设置有至少一个第二金属化孔51，第二区域62、第二金属化孔51、第二连接金属44、第一金属化孔32以及第一栅极22依次电连接。第一区域61与第一连接金属46形成了该自举电容Cb。在本实施例中，该至少一个第一金属化孔32包括多个呈矩形阵列排布的第一金属化孔32；该至少一个第二金属化孔51包括多个呈矩形阵列排布的第二金属化孔51，从而提高连接的稳定性。
其中，该第一绝缘层30设置有至少一个第四金属化孔31，扫描线41通过第四金属化孔31与第二栅极21电连接。其中，该至少一个第四金属化孔31包括多个呈矩形阵列排布的第四金属化孔31，从而提高电连接的稳定性。
本发明还提供了一种显示面板，其包括上述任意实施例中的阵列基板。
本申请实施例的阵列基板及显示面板，通过在第三绝缘层上设置一个与第一连接金属相对的第三金属层，使得第一连接金属与第三金属层形成自举电容，无需延长第一金属层的宽度来与第一连接金属形成自举电容，从而可以缩减GOA驱动电路占用的面积，进而实现更窄边框。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板上设置有GOA驱动电路以及多个像素单元，所述GOA驱动电路包括一自举电容以及一第一薄膜晶体管，所述像素单元包括一第二薄膜晶体管，所述阵列基板包括：
    一基板；
    第一金属层，所述第一金属层设置在所述基板上，所述第一金属层形成所述第一薄膜晶体管的第一栅极以及所述第二薄膜晶体管的第二栅极；
    第一绝缘层，所述第一绝缘层设置在所述第一金属层以及所述基板上；
    第二金属层，所述第二金属层设置在所述第一绝缘层上，所述第二金属层形成扫描线、第一连接金属以及所述第一薄膜晶体管的第一漏极，所述第一漏极、所述第一连接金属以及所述扫描线的一端依次连接，所述扫描线的另一端与所述第二栅极连接；
    第二绝缘层，所述第二绝缘层设置在所述第二金属层上；
    第三金属层，所述第三金属层设置在所述第二绝缘层上，所述第三金属层与所述第一栅极电连接，所述第三金属层与所述第一连接金属相对的部分形成所述自举电容；
    所述第一金属层还形成有公共电极线，所述公共电极线与所述像素单元电连接；所述第一绝缘层设置有至少一个第四金属化孔，所述扫描线通过所述第四金属化孔与所述第二栅极电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述第一连接金属的局部与所述公共电极线相对。
  3. 根据权利要求2所述的阵列基板，其中，所述第三金属层包括相互连接的第一区域以及第二区域，所述第一区域与所述第一连接金属的形状以及尺寸相同且相互正对，所述第二区域与所述第一栅极电连接。
  4. 根据权利要求3所述的阵列基板，其中，所述第二区域通过贯穿所述第一绝缘层以及所述第二绝缘层的第三金属化孔与所述第一栅极电连接。
  5. 根据权利要求3所述的阵列基板，其中，所述第二金属层还形成有第二连接金属，所述第一绝缘层设置有至少一个第一金属化孔，所述第二绝缘层设置有至少一个第二金属化孔，所述第二区域、所述第二金属化孔、所述第二连接金属、所述第一金属化孔以及所述第一栅极依次电连接。
  6. 根据权利要求5所述的阵列基板，其中，所述至少一个第一金属化孔包括多个呈矩形阵列排布的第一金属化孔；所述至少一个第二金属化孔包括多个呈矩形阵列排布的第二金属化孔。
  7. 根据权利要求1所述的阵列基板，其中，所述至少一个第四金属化孔包括多个呈矩形阵列排布的第四金属化孔。
  8. 一种阵列基板，其中，所述阵列基板上设置有GOA驱动电路以及多个像素单元，所述GOA驱动电路包括一自举电容以及一第一薄膜晶体管，所述像素单元包括一第二薄膜晶体管，所述阵列基板包括：
    一基板；
    第一金属层，所述第一金属层设置在所述基板上，所述第一金属层形成所述第一薄膜晶体管的第一栅极以及所述第二薄膜晶体管的第二栅极；
    第一绝缘层，所述第一绝缘层设置在所述第一金属层以及所述基板上；
    第二金属层，所述第二金属层设置在所述第一绝缘层上，所述第二金属层形成扫描线、第一连接金属以及所述第一薄膜晶体管的第一漏极，所述第一漏极、所述第一连接金属以及所述扫描线的一端依次连接，所述扫描线的另一端与所述第二栅极连接；
    第二绝缘层，所述第二绝缘层设置在所述第二金属层上；
    第三金属层，所述第三金属层设置在所述第二绝缘层上，所述第三金属层与所述第一栅极电连接，所述第三金属层与所述第一连接金属相对的部分形成所述自举电容。
  9. 根据权利要求8所述的阵列基板，其中，所述第一金属层还形成有公共电极线，所述公共电极线与所述像素单元电连接。
  10. 根据权利要求9所述的阵列基板，其中，所述第一连接金属的局部与所述公共电极线相对。
  11. 根据权利要求10所述的阵列基板，其中，所述第三金属层包括相互连接的第一区域以及第二区域，所述第一区域与所述第一连接金属的形状以及尺寸相同且相互正对，所述第二区域与所述第一栅极电连接。
  12. 根据权利要求11所述的阵列基板，其中，所述第二区域通过贯穿所述第一绝缘层以及所述第二绝缘层的第三金属化孔与所述第一栅极电连接。
  13. 根据权利要求11所述的阵列基板，其中，所述第二金属层还形成有第二连接金属，所述第一绝缘层设置有至少一个第一金属化孔，所述第二绝缘层设置有至少一个第二金属化孔，所述第二区域、所述第二金属化孔、所述第二连接金属、所述第一金属化孔以及所述第一栅极依次电连接。
  14. 根据权利要求13所述的阵列基板，其中，所述至少一个第一金属化孔包括多个呈矩形阵列排布的第一金属化孔；所述至少一个第二金属化孔包括多个呈矩形阵列排布的第二金属化孔。
  15. 根据权利要求8所述的阵列基板，其中，所述第一绝缘层设置有至少一个第四金属化孔，所述扫描线通过所述第四金属化孔与所述第二栅极电连接。
  16. 根据权利要求15所述的阵列基板，其中，所述至少一个第四金属化孔包括多个呈矩形阵列排布的第四金属化孔。
  17. 一种显示面板，其包括阵列基板，所述阵列基板上设置有GOA驱动电路以及多个像素单元，所述GOA驱动电路包括一自举电容以及一第一薄膜晶体管，所述像素单元包括一第二薄膜晶体管，所述阵列基板包括：
    一基板；
    第一金属层，所述第一金属层设置在所述基板上，所述第一金属层形成所述第一薄膜晶体管的第一栅极以及所述第二薄膜晶体管的第二栅极；
    第一绝缘层，所述第一绝缘层设置在所述第一金属层以及所述基板上；
    第二金属层，所述第二金属层设置在所述第一绝缘层上，所述第二金属层形成扫描线、第一连接金属以及所述第一薄膜晶体管的第一漏极，所述第一漏极、所述第一连接金属以及所述扫描线的一端依次连接，所述扫描线的另一端与所述第二栅极连接；
    第二绝缘层，所述第二绝缘层设置在所述第二金属层上；
    第三金属层，所述第三金属层设置在所述第二绝缘层上，所述第三金属层与所述第一栅极电连接，所述第三金属层与所述第一连接金属相对的部分形成所述自举电容。
  18. 根据权利要求17所述的显示面板，其中，所述第一金属层还形成有公共电极线，所述公共电极线与所述像素单元电连接。
  19. 根据权利要求18所述的显示面板，其中，所述第一连接金属的局部与所述公共电极线相对。
  20. 根据权利要求19所述的显示面板，其中，所述第三金属层包括相互连接的第一区域以及第二区域，所述第一区域与所述第一连接金属的形状以及尺寸相同且相互正对，所述第二区域与所述第一栅极电连接。
PCT/CN2019/115848 2019-08-08 2019-11-06 阵列基板及显示面板 WO2021022694A1 (zh)

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