WO2023070726A1 - 一种阵列基板及显示面板 - Google Patents

一种阵列基板及显示面板 Download PDF

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Publication number
WO2023070726A1
WO2023070726A1 PCT/CN2021/128894 CN2021128894W WO2023070726A1 WO 2023070726 A1 WO2023070726 A1 WO 2023070726A1 CN 2021128894 W CN2021128894 W CN 2021128894W WO 2023070726 A1 WO2023070726 A1 WO 2023070726A1
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WIPO (PCT)
Prior art keywords
line
pixel
sharing
sub
electrically connected
Prior art date
Application number
PCT/CN2021/128894
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English (en)
French (fr)
Inventor
肖军城
李吉
龙芬
赵迎春
葛茹
俞云
刘菁
Original Assignee
Tcl华星光电技术有限公司
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Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/614,394 priority Critical patent/US20240027856A1/en
Priority to KR1020217039244A priority patent/KR102655536B1/ko
Priority to JP2021568264A priority patent/JP7478756B2/ja
Publication of WO2023070726A1 publication Critical patent/WO2023070726A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a display panel.
  • thin film transistor liquid crystal display (English full name: Thin film In the array substrate of transistor liquid crystal display (abbreviation: TFT LCD)
  • the electric field of the data line (data) may flip the surrounding liquid crystal, causing light leakage, and the distance between data and pixel electrode (pixel) is relatively close, and the capacity of data to pixel Sexual coupling can also cause adverse effects such as crosstalk.
  • DBS Black matrix
  • a DBS electrode is arranged above the data line, and the potential of the DBS electrode is the same as that of the common electrode on the color filter substrate, so that the corresponding liquid crystal molecules above the data line are always kept in an undeflected state, thereby playing the role of shading.
  • a common electrode line 200' (A com) can also be used on the side of the data line 100' to shield the lateral electric field of the data line 100', so as to reduce the influence of data on the pixel. But using A The lateral electric field of the com shielding data line 100' will reduce the aperture ratio of the pixel unit.
  • the current sharing electrode line 300' (English full name: share bar) of the shared thin film transistor runs through the main pixel area and the sub-pixel area, thereby reducing the light transmission area of the pixel unit, reducing the aperture ratio and penetration of the pixel unit. Rate.
  • the object of the present invention is to provide an array substrate and a display panel, which can solve the problem of using A
  • the lateral electric field of the com shielding data line leads to problems such as a low aperture ratio of the display panel.
  • the present invention provides an array substrate, which includes a substrate and a plurality of pixel units arranged in an array on the substrate; each of the pixel units includes: a data line arranged on the substrate ; the scanning line is arranged on the substrate and interlaced with the data line; and the first sharing line is arranged between the substrate and the data line and is parallel to the data line.
  • the first sharing line has a first central axis parallel to the data line; the data line has a second central axis parallel to the first sharing line; the first central axis and the The second central axes coincide with each other.
  • widths of the first sharing line and the data line are uniformly set, and the width of the first sharing line is greater than or equal to the width of the data line.
  • each of the pixel units is divided into a main pixel area and a sub-pixel area; the scanning line is arranged between the main pixel area and the sub-pixel area; each of the pixel units also includes: The second sharing line is parallel to the scanning line and is arranged between the scanning line and the sub-pixel region; and the first common line is parallel to the scanning line and is arranged between the scanning line and the sub-pixel area; between the main pixel areas; wherein, one end of each of the first sharing lines is electrically connected to the second sharing line, and the other end extends from a sub-pixel area of the pixel unit along the first axis to The main pixel area of the adjacent pixel unit.
  • the scanning line, the second sharing line, the first common line and the first sharing line are arranged on the same layer.
  • each of the pixel units also includes: a main pixel electrode arranged in the main pixel area, the main pixel electrode includes a first trunk electrode parallel to the data line; a sub-pixel electrode arranged in the In the sub-pixel area, the sub-pixel electrode includes a second main electrode parallel to the data line; the main pixel thin film transistor, its gate is electrically connected to the scanning line, and its source is electrically connected to the data line.
  • the sub-pixel thin film transistor its gate is electrically connected to the scanning line, its source is electrically connected to the data line, and its drain is electrically connected to the sub-pixel a pixel electrode; and a sharing thin film transistor, the gate of which is electrically connected to the scan line, the source of which is electrically connected to the drain of the sub-pixel thin film transistor, and the drain of which is electrically connected to the second sharing line.
  • each of the pixel units further includes: a third sharing line, one end of which is electrically connected to the second sharing line, and the other end of which is connected along the first axis by a sub-pixel of the pixel unit The region extends to the main pixel region of the adjacent pixel unit.
  • each of the pixel units also includes: a second common line, one end of which is electrically connected to the first common line, and the other end of which is connected to the main pixel area of the pixel unit along the first axis. extending to the sub-pixel regions of the adjacent pixel units.
  • the third sharing line in the main pixel area is arranged corresponding to the first trunk electrode, and the third sharing line in the sub-pixel area is arranged corresponding to the second trunk electrode.
  • the second common line in the main pixel area is arranged corresponding to the first stem electrode, and the second common line in the sub-pixel area is arranged corresponding to the second stem electrode.
  • the present invention provides a display panel, which includes the array substrate of the present invention, a color filter substrate corresponding to the array substrate, and a color filter substrate arranged between the array substrate and the color filter substrate. the liquid crystal layer.
  • the first sharing line is correspondingly arranged under the data line, the electric field of the data line is shielded by the first sharing line, and the electric field between the data line and the first common line is alleviated by using the first sharing line. Coupling effect, thereby reducing the crosstalk caused by the fluctuation of the first common line to the data line, avoiding the problem of low aperture ratio of the display panel caused by the use of A com to shield the lateral electric field of the data line in the prior art.
  • the first central axis of the first sharing line coincides with the second central axis of the data line, avoiding the first sharing line in the prior art to pass through the main pixel area and the sub-pixel area, thereby improving the pixel unit The opening rate and penetration rate.
  • FIG. 1 is a schematic plan view of a pixel unit of an array substrate in the prior art
  • Fig. 2 is the A-A sectional view of Fig. 1;
  • FIG. 3 is a schematic plan view of an array substrate according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic plan view of a pixel unit of the array substrate according to Embodiment 1 of the present invention.
  • Fig. 5 is a B-B sectional view among Fig. 4;
  • FIG. 6 is a driving circuit diagram of the array substrate according to Embodiment 1 of the present invention.
  • FIG. 7 is a partial plan view of two pixel units of the array substrate according to Embodiment 1 of the present invention.
  • FIG. 8 is a schematic plan view of a pixel unit of the array substrate according to Embodiment 2 of the present invention.
  • FIG. 9 is a partial plan view of two pixel units of the array substrate according to Embodiment 2 of the present invention.
  • Sub-pixel electrode 8. Main pixel thin film transistor
  • Sub-pixel thin film transistor 10. Share thin film transistors;
  • the display panel includes an array substrate 100 , a color filter substrate corresponding to the array substrate 100 , and a liquid crystal layer arranged between the array substrate 100 and the color filter substrate.
  • the array substrate 100 includes: a substrate 101 and a plurality of pixel units 102 arrayed on the substrate 101 .
  • the material of substrate 101 is one or more in glass, polyimide, polycarbonate, polyethylene terephthalate and polyethylene naphthalate, thus substrate 101 can have Good impact resistance can effectively protect the display panel.
  • each pixel unit 102 is divided into a main pixel area 1021 and a sub-pixel area 1022 .
  • Each pixel unit 102 includes: a data line 1, a scanning line 2, a first sharing line 3, a second sharing line 4, a first common line 5, a main pixel electrode 6, a sub-pixel electrode 7, and a main pixel thin film transistor 8.
  • the sub-pixel thin film transistor 9 , the sharing thin film transistor 10 and the third sharing line 11 are examples of the sub-pixel thin film transistor 9 , the sharing thin film transistor 10 and the third sharing line 11 .
  • the data line 1 is disposed on the substrate 101 .
  • the material of the data line 1 is metal.
  • the material of the data line 1 may also be other conductive materials.
  • the scanning lines 2 are arranged between the main pixel area 1021 and the sub-pixel area 1022 , and are interlaced with the data lines 1 . That is, the extending direction of the data lines 1 is not parallel to the extending direction of the scanning lines 2 . In this embodiment, the extending direction of the data lines 1 and the extending direction of the scanning lines 2 are perpendicular to each other.
  • the scan line 2 is made of metal. In other embodiments, the material of the scan line 2 may also be other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, stacked layers of metal materials and other conductive materials, or other suitable materials.
  • the first sharing line 3 is disposed between the substrate 101 and the data line 1 , and is parallel to the data line 1 .
  • the material of the first sharing line 3 is metal.
  • the material of the first sharing line 3 may also be other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, stacked layers of metal materials and other conductive materials, or other suitable materials.
  • first sharing line 3 to shield the electric field of the data line 1
  • use the first sharing line 3 to reduce the coupling effect between the data line 1 and the first common line 5, and then reduce the coupling effect due to the first common line 5 Crosstalk caused by fluctuations on data line 1.
  • the problem of low aperture ratio of the display panel caused by the use of the A com to shield the lateral electric field of the data line in the prior art is avoided.
  • the first sharing line 3 has a first central axis 12 parallel to the data line 1 , and the first central axis 12 is an axis of symmetry.
  • the data line 1 has a second central axis 13 parallel to the first sharing line 3 , and the second central axis 13 is an axis of symmetry.
  • the first central axis 12 and the second central axis 13 coincide with each other.
  • the first central axis 12 of the first sharing line 3 coincides with the second central axis 13 of the data line 1, so as to avoid the first sharing line 3 in the prior art passing through the main pixel area 1021 and the sub-pixel area 1022 , thereby increasing the aperture ratio and transmittance of the array substrate 100 .
  • each first sharing line 3 is electrically connected to the second sharing line 4 , and the other end is connected by a sub-pixel region 1022 of the pixel unit 102 along the first axis 1011 extending to the main pixel area 1021 of the adjacent pixel unit 102 .
  • the width of the first sharing line 3 is uniformly set, the width of the data line 1 is evenly set, and the width of the first sharing line 3 is greater than or equal to the width of the data line 1 .
  • the range of the difference between the width of the first sharing line 3 and the width of the data line 1 is 0-15 ⁇ m.
  • the first sharing line 3 When the first sharing line 3 When the difference between the width of the data line 1 and the width of the data line 1 is greater than 15 ⁇ m, the first sharing line 3 will occupy the opening area of the array substrate 100 , reducing the aperture ratio and transmittance of the array substrate 100 .
  • an insulating layer 14 is further disposed between the first sharing line 3 and the data line 1 .
  • the insulating layer 14 is mainly used to prevent a short circuit caused by contact between the first sharing line 3 and the data line 1 .
  • the insulating layer 14 can be made of one or more of SiO 2 and SiNx.
  • the second sharing line 4 is parallel to the scan line 2 , is disposed between the scan line 2 and the sub-pixel region 1022 , and is spaced apart from the scan line 2 .
  • the material of the second sharing line 4 is metal.
  • the material of the second sharing line 4 may also be other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, stacked layers of metal materials and other conductive materials, or other suitable materials.
  • the first common line 5 is parallel to the scanning line 2, and is arranged between the scanning line 2 and the main pixel area 1021, and is spaced apart from the scanning line 2.
  • the material of the first common line 5 is metal.
  • the material of the first common line 5 may also be other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, stacked layers of metal materials and other conductive materials, or other suitable materials.
  • the scanning line 2 , the second sharing line 4 , the first common line 5 and the first sharing line 3 are arranged on the same layer.
  • the scanning line 2, the second sharing line 4, the first common line 5, and the first sharing line 3 are made of the same material, so they can be prepared and formed simultaneously in one process, and then The process can be saved and the production cost can be saved.
  • the main pixel electrode 6 is disposed in the main pixel region 1021 .
  • the main pixel electrode 6 includes a first main electrode 61 parallel to the data line 1 .
  • the sub-pixel electrode 7 is disposed in the sub-pixel region 1022 .
  • the sub-pixel electrode 7 includes a second stem electrode 71 parallel to the data line 1 .
  • the gate of the main pixel thin film transistor 8 (ie T1 in Figure 4) is electrically connected to the scanning line 2 (ie Gate in Figure 4); the main pixel thin film transistor 8 (ie, T1 in FIG. 4 ) has its source electrically connected to the data line 1 (ie, Data in FIG. 4 ), and the drain of the main pixel thin film transistor 8 (ie, T1 in FIG. 4 ) is electrically connected to The main pixel electrode 6 .
  • the gate of the sub-pixel thin film transistor 9 (ie T2 in Figure 4) is electrically connected to the scanning line 2 (ie Gate in Figure 4); the sub-pixel thin film transistor 9 (that is, T2 in FIG. 4 ) is electrically connected to the data line 1 (that is, Data in FIG. 4 ), and the drain of the sub-pixel thin film transistor 9 (that is, T2 in FIG. 4 ) is electrically connected to The sub-pixel electrode 7 .
  • the gate of the shared thin film transistor 10 (that is, T3 in FIG. 4 ) is electrically connected to the scan line 2 (that is, the Gate in FIG. 4 ); the shared thin film transistor 10 ( That is, the source of T3 in FIG. 4 ) is electrically connected to the drain of the sub-pixel thin film transistor 9 (that is, T2 in FIG. 4 ), and the drain of the shared thin film transistor 10 (that is, T3 in FIG. 4 ) Connect to the second sharing line 4.
  • the gate of the main pixel thin film transistor 8, the gate of the sub-pixel thin film transistor 9 and the gate of the shared thin film transistor 10 are electrically connected to the same scanning line 2; the main pixel thin film transistor 8 The source of the sub-pixel thin film transistor 9 is electrically connected to the same data line 1 .
  • one end of the third sharing line 11 is electrically connected to the second sharing line 4 , and the other end extends along the first axis 1011 from a sub-pixel region 1022 of the pixel unit 102 to the corresponding adjacent to the main pixel area 1021 of the pixel unit 102 .
  • the third sharing line 11 in the main pixel area 1021 is set corresponding to the first trunk electrode 61, and the third sharing line 11 in the sub-pixel area 1022 is set in correspondence with the The second trunk electrode 71 is correspondingly arranged. In this way, an additional occupation of the light-transmitting area of the array substrate 100 can be avoided, and the aperture ratio of the array substrate 100 can be increased.
  • Embodiment 2 includes most of the technical features of Embodiment 1.
  • the difference between Embodiment 2 and Embodiment 1 is that the third sharing line 11 of Embodiment 1 is removed in Embodiment 2, At the position of the third sharing line 11 in Embodiment 1, a second common line 15 is provided.
  • one end of the second common line 15 is electrically connected to the first common line 5 , and the other end is connected to the main pixel area 1021 of the pixel unit 102 along the first axis 1011 . extending to the sub-pixel region 1022 of the adjacent pixel unit 102 .
  • the second common line 15 in the main pixel area 1021 is set corresponding to the first trunk electrode 61, and the second common line 15 in the sub-pixel area 1022 is set in correspondence with the The second trunk electrode 71 is correspondingly arranged. In this way, an additional occupation of the light-transmitting area of the array substrate 100 can be avoided, and the aperture ratio of the array substrate 100 can be increased.
  • the first sharing line 3 to shield the electric field of the data line 1, use the first sharing line 3 to reduce the coupling effect between the data line 1 and the first common line 5, and then reduce the coupling effect due to the first common line 5 Crosstalk caused by fluctuations on data line 1.
  • the first central axis 12 of the first sharing line 3 coincides with the second central axis 13 of the data line 1, so as to avoid the first sharing line 3 in the prior art passing through the main pixel area 1021 and the sub-pixel area 1022 , thereby increasing the aperture ratio and transmittance of the array substrate 100 .

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Abstract

本发明涉及一种阵列基板及显示面板。本发明将第一分享线对应设置于所述数据线的下方，利用第一分享线屏蔽所述数据线的电场，利用第一分享线减轻所述数据线与所述第一公共线之间的耦合作用，进而减轻由于第一公共线的波动对数据线造成的串扰，避免现有技术中采用A com屏蔽数据线的侧向电场导致显示面板开口率低下的问题。

Description

一种阵列基板及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及显示面板。
 背景技术
目前，薄膜晶体管液晶显示器（英文全称：Thin film transistor liquid crystal display，简称：TFT LCD）的阵列基板中，数据线（data）的电场可能使周围的液晶翻转，造成漏光，而且data距离像素电极（pixel）的距离较近，data对pixel的容性耦合也会造成串扰等不良影响。
目前，除了在数据线上方设置黑色矩阵(英文全称：Black matrix，简称：BM)进行遮光外，还可以采用DBS(英文全称：Data line BM Less)技术，去除数据线上方的黑色矩阵，在数据线上方设置DBS电极，并使得DBS电极的电位与彩膜基板上的公共电极电位相同，使得数据线上方对应的液晶分子始终保持未偏转状态，进而起到遮光的作用。
 技术问题
如图1、图2所示，还可以在数据线100’的侧方使用公共电极线200’（A com）屏蔽数据线100’的侧向电场，以减轻data对pixel的影响。但是采用A com屏蔽数据线100’的侧向电场会降低像素单元的开口率。而且目前的分享薄膜晶体管的分享电极线300’（英文全称：share bar）纵穿主像素区及次像素区，由此会减小像素单元的透光面积，降低像素单元的开口率及穿透率。
 技术解决方案
本发明的目的是提供一种阵列基板及显示面板，其能够解决现有技术采用A com屏蔽数据线的侧向电场导致显示面板开口率低下等问题。
为了解决上述问题，本发明提供了一种阵列基板，其包括基板及阵列排布于所述基板上的多个像素单元；每一所述像素单元均包括：数据线，设置于所述基板上；扫描线，设置于所述基板上，且与所述数据线相互交错设置；以及第一分享线，设置于所述基板与所述数据线之间，且平行于所述数据线。
进一步的，所述第一分享线具有平行于所述数据线的第一中轴线；所述数据线具有平行于所述第一分享线的第二中轴线；所述第一中轴线与所述第二中轴线相互重合。
进一步的，所述第一分享线和所述数据线的宽度均匀设置，且所述第一分享线的宽度大于或等于所述数据线的宽度。
进一步的，每一所述像素单元均分为主像素区和次像素区；所述扫描线设置于所述主像素区和所述次像素区之间；每一所述像素单元均还包括：第二分享线，平行于所述扫描线，且设置于所述扫描线与所述次像素区之间；以及第一公共线，平行于所述扫描线，且设置于所述扫描线与所述主像素区之间；其中，每一所述第一分享线的一端电连接至所述第二分享线，另一端沿着所述第一轴线由一所述像素单元的次像素区延伸至相邻的所述像素单元的主像素区。
进一步的，所述扫描线、所述第二分享线、所述第一公共线以及所述第一分享线同层设置。
进一步的，每一所述像素单元均还包括：主像素电极，设置于所述主像素区内，所述主像素电极包括平行于所述数据线的第一主干电极；次像素电极，设置于所述次像素区内，所述次像素电极包括平行于所述数据线的第二主干电极；主像素薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述数据线，其漏极电连接至所述主像素电极；次像素薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述数据线，其漏极电连接至所述次像素电极；以及分享薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述次像素薄膜晶体管的漏极，其漏极电连接至所述第二分享线。
进一步的，每一所述像素单元均还包括：第三分享线，其一端电连接至所述第二分享线，其另一端且沿着所述第一轴线由一所述像素单元的次像素区延伸至相邻的所述像素单元的主像素区。
进一步的，每一所述像素单元均还包括：第二公共线，其一端电连接至所述第一公共线，其另一端沿着所述第一轴线由一所述像素单元的主像素区延伸至相邻的所述像素单元的次像素区。
进一步的，所述主像素区内的所述第三分享线与所述第一主干电极对应设置，所述次像素区内的所述第三分享线与所述第二主干电极对应设置。
进一步的，所述主像素区内的所述第二公共线与所述第一主干电极对应设置，所述次像素区内的所述第二公共线与所述第二主干电极对应设置。
为了解决上述问题，本发明提供了一种显示面板，其包括本发明所述的阵列基板、与所述阵列基板对应设置的彩膜基板以及设置于所述阵列基板与所述彩膜基板之间的液晶层。
 有益效果
本发明将第一分享线对应设置于所述数据线的下方，利用第一分享线屏蔽所述数据线的电场，利用第一分享线减轻所述数据线与所述第一公共线之间的耦合作用，进而减轻由于第一公共线的波动对数据线造成的串扰，避免现有技术中采用A com屏蔽数据线的侧向电场导致显示面板开口率低下的问题。本发明将第一分享线的第一中轴线与所述数据线的第二中轴线重合，避免现有技术中的第一分享线纵穿所述主像素区和次像素区，进而提升像素单元的开口率和穿透率。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术的阵列基板的一个像素单元的平面示意图；
图2是图1的A-A截面图；
图3是本发明实施例1的阵列基板的平面示意图；
图4是本发明实施例1的阵列基板的一个像素单元的平面示意图；
图5是图4中的B-B截面图；
图6是本发明实施例1的阵列基板的驱动电路图；
图7是本发明实施例1的阵列基板的两个像素单元的局部平面示意图；
图8是本发明实施例2的阵列基板的一个像素单元的平面示意图；
图9是本发明实施例2的阵列基板的两个像素单元的局部平面示意图。
附图标记说明：
100、阵列基板；                   101、基板；
102、像素单元；
1021、主像素区；                  1022、次像素区；
1、数据线；                       2、扫描线；
3、第一分享线；                   4、第二分享线；
5、第一公共线；                   6、主像素电极；
7、次像素电极；                   8、主像素薄膜晶体管；
9、次像素薄膜晶体管；             10、分享薄膜晶体管；
11、第三分享线；                  12、第一中轴线；
13、第二中轴线；                  14、绝缘层；
15、第二公共线；                  61、第一主干电极；
71、第二主干电极。
 本发明的实施方式
以下结合说明书附图详细说明本发明的优选实施例，以向本领域中的技术人员完整介绍本发明的技术内容，以举例证明本发明可以实施，使得本发明公开的技术内容更加清楚，使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例，下文实施例的说明并非用来限制本发明的范围。
本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，本文所使用的方向用语是用来解释和说明本发明，而不是用来限定本发明的保护范围。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。此外，为了便于理解和描述，附图所示的每一组件的尺寸和厚度是任意示出的 ，本发明并没有限定每个组件的尺寸和厚度。
实施例1
本实施例提供了一种显示面板。所述显示面板包括阵列基板100、与所述阵列基板100对应设置的彩膜基板以及设置于所述阵列基板100与所述彩膜基板之间的液晶层。
如图3所示，所述阵列基板100包括：基板101及阵列排布于所述基板101上的多个像素单元102。
其中，基板101的材质为玻璃、聚酰亚胺、聚碳酸酯、聚对苯二甲酸乙二醇酯以及聚萘二甲酸乙二醇酯中的一种或多种，由此基板101可具有较好的抗冲击能力，可以有效保护显示面板。
如图4所示，每一所述像素单元102均分为主像素区1021和次像素区1022。每一所述像素单元102均包括：数据线1、扫描线2、第一分享线3、第二分享线4、第一公共线5、主像素电极6、次像素电极7、主像素薄膜晶体管8、次像素薄膜晶体管9、分享薄膜晶体管10以及第三分享线11。
如图3、图4、图5所示，数据线1设置于所述基板101上。本实施例中，所述数据线1的材质为金属。在其他实施例中，所述数据线1的材质也可以是其他导电材料。例如：合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物、或是金属材料与其他导电材料的堆叠层或其他合适的材料。
如图3、图4所示，扫描线2设置于所述主像素区1021和所述次像素区1022之间，且与所述数据线1相互交错设置。即所述数据线1的延伸方向和扫描线2的延伸方向不平行。本实施例中，所述数据线1的延伸方向与扫描线2的延伸方向相互垂直。本实施例中，所述扫描线2的材质为金属。在其他实施例中，所述扫描线2的材质也可以是其他导电材料。例如：合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物、或是金属材料与其他导电材料的堆叠层或其他合适的材料。
如图3、图4、图5所示，所述第一分享线3设置于所述基板101与所述数据线1之间，且平行于所述数据线1。本实施例中，所述第一分享线3的材质为金属。在其他实施例中，所述第一分享线3的材质也可以是其他导电材料。例如：合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物、或是金属材料与其他导电材料的堆叠层或其他合适的材料。
利用第一分享线3屏蔽所述数据线1的电场，利用第一分享线3减轻所述数据线1与所述第一公共线5之间的耦合作用，进而减轻由于第一公共线5的波动对数据线1造成的串扰。避免现有技术中采用A com屏蔽数据线的侧向电场导致显示面板开口率低下的问题。
如图3、图4、图5所示，所述第一分享线3具有平行于所述数据线1的第一中轴线12，所述第一中轴线12为对称轴。所述数据线1具有平行于所述第一分享线3的第二中轴线13，所述第二中轴线13为对称轴。所述第一中轴线12与所述第二中轴线13相互重合。将第一分享线3的第一中轴线12与所述数据线1的第二中轴线13重合，避免现有技术中的第一分享线3纵穿所述主像素区1021和次像素区1022，进而提升阵列基板100的开口率和穿透率。
如图7所示，每一所述第一分享线3的一端电连接至所述第二分享线4，另一端沿着所述第一轴线1011由一所述像素单元102的次像素区1022延伸至相邻的所述像素单元102的主像素区1021。
如图4、图5所示，所述第一分享线3的宽度均匀设置，所述数据线1的宽度均匀设置，所述第一分享线3的宽度大于或等于所述数据线1的宽度。具体的，所述第一分享线3的宽度与所述数据线1的宽度的差值的范围为0-15μm。当所述第一分享线3的宽度与所述数据线1的宽度的差值较小时，会造成第一分享线3屏蔽数据线1的电场的效果不佳，当所述第一分享线3的宽度与所述数据线1的宽度的差值大于15μm时，第一分享线3会占用阵列基板100的开口面积，降低阵列基板100的开口率及穿透率。
如图5所示，所述第一分享线3与所述数据线1之间还设置有绝缘层14。所述绝缘层14主要是用于防止第一分享线3与数据线1之间接触产生短路现象。绝缘层14的材质可以采用SiO 2、SiNx中的一种或多种。
如图3、图4所示，第二分享线4平行于所述扫描线2，且设置于所述扫描线2与所述次像素区1022之间，且与所述扫描线2间隔设置。本实施例中，所述第二分享线4的材质为金属。在其他实施例中，所述第二分享线4的材质也可以是其他导电材料。例如：合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物、或是金属材料与其他导电材料的堆叠层或其他合适的材料。
如图3、图4所示，第一公共线5平行于所述扫描线2，且设置于所述扫描线2的与所述主像素区1021之间，且与所述扫描线2间隔设置。本实施例中，所述第一公共线5的材质为金属。在其他实施例中，所述第一公共线5的材质也可以是其他导电材料。例如：合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物、或是金属材料与其他导电材料的堆叠层或其他合适的材料。
其中，所述扫描线2、所述第二分享线4、所述第一公共线5以及所述第一分享线3同层设置。本实施例中，所述扫描线2、所述第二分享线4、所述第一公共线5以及所述第一分享线3的材质相同，由此可以在一道工序内同时制备形成，进而可以节省工序，节约生产成本。
如图4所示，主像素电极6设置于所述主像素区1021内。所述主像素电极6包括平行于所述数据线1的第一主干电极61。
如图4所示，次像素电极7设置于所述次像素区1022内。所述次像素电极7包括平行于所述数据线1的第二主干电极71。
如图4、图6所示，所述主像素薄膜晶体管8（即图4中的T1）的栅极电连接至所述扫描线2（即图4中的Gate）；所述主像素薄膜晶体管8（即图4中的T1）的源极电连接至所述数据线1（即图4中的Data），所述主像素薄膜晶体管8（即图4中的T1）的漏极电连接至所述主像素电极6。
如图4、图6所示，所述次像素薄膜晶体管9（即图4中的T2）的栅极电连接至所述扫描线2（即图4中的Gate）；所述次像素薄膜晶体管9（即图4中的T2）的源极电连接至所述数据线1（即图4中的Data），所述次像素薄膜晶体管9（即图4中的T2）的漏极电连接至所述次像素电极7。
如图4、图6所示，所述分享薄膜晶体管10（即图4中的T3）的栅极电连接至所述扫描线2（即图4中的Gate）；所述分享薄膜晶体管10（即图4中的T3）的源极电连接至所述次像素薄膜晶体管9（即图4中的T2）的漏极，所述分享薄膜晶体管10（即图4中的T3）的漏极电连接至所述第二分享线4。
其中，所述主像素薄膜晶体管8的栅极、所述次像素薄膜晶体管9的栅极和所述分享薄膜晶体管10的栅极电连接至同一所述扫描线2；所述主像素薄膜晶体管8的源极和所述次像素薄膜晶体管9的源极电连接至同一条所述数据线1。
如图7所示，第三分享线11的一端电连接至所述第二分享线4，另一端且沿着所述第一轴线1011由一所述像素单元102的次像素区1022延伸至相邻的所述像素单元102的主像素区1021。
如图4所示，所述主像素区1021内的所述第三分享线11与所述第一主干电极61对应设置，所述次像素区1022内的所述第三分享线11与所述第二主干电极71对应设置。由此可以避免额外占用阵列基板100的透光面积，提升阵列基板100的开口率。
实施例2
如图8、图9所示，实施例2包括了实施例1的大部分技术特征，实施例2与实施例1的区别在于：实施例2中去除了实施例1的第三分享线11，在实施例1的第三分享线11的位置处设置了第二公共线15。
如图8、图9所示，第二公共线15的一端电连接至所述第一公共线5，其另一端沿着所述第一轴线1011由一所述像素单元102的主像素区1021延伸至相邻的所述像素单元102的次像素区1022。
如图8所示，所述主像素区1021内的所述第二公共线15与所述第一主干电极61对应设置，所述次像素区1022内的所述第二公共线15与所述第二主干电极71对应设置。由此可以避免额外占用阵列基板100的透光面积，提升阵列基板100的开口率。
利用第一分享线3屏蔽所述数据线1的电场，利用第一分享线3减轻所述数据线1与所述第一公共线5之间的耦合作用，进而减轻由于第一公共线5的波动对数据线1造成的串扰。将第一分享线3的第一中轴线12与所述数据线1的第二中轴线13重合，避免现有技术中的第一分享线3纵穿所述主像素区1021和次像素区1022，进而提升阵列基板100的开口率和穿透率。
以上对本申请所提供的一种阵列基板及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (18)

  1. 一种阵列基板，包括基板及阵列排布于所述基板上的多个像素单元；
    每一所述像素单元均包括：
    数据线，设置于所述基板上；
    扫描线，设置于所述基板上，且与所述数据线相互交错设置；以及
    第一分享线，设置于所述基板与所述数据线之间，且平行于所述数据线。
  2. 根据权利要求1所述的阵列基板，所述第一分享线具有平行于所述数据线的第一中轴线；所述数据线具有平行于所述第一分享线的第二中轴线；所述第一中轴线与所述第二中轴线相互重合。
  3. 根据权利要求2所述的阵列基板，所述第一分享线和所述数据线的宽度均匀设置，且所述第一分享线的宽度大于或等于所述数据线的宽度。
  4. 根据权利要求1所述的阵列基板，每一所述像素单元均分为主像素区和次像素区；所述扫描线设置于所述主像素区和所述次像素区之间；
    每一所述像素单元均还包括：
    第二分享线，平行于所述扫描线，且设置于所述扫描线与所述次像素区之间；以及
    第一公共线，平行于所述扫描线，且设置于所述扫描线与所述主像素区之间；
    其中，每一所述第一分享线的一端电连接至所述第二分享线，另一端沿着所述第一轴线由一所述像素单元的次像素区延伸至相邻的所述像素单元的主像素区。
  5. 根据权利要求4所述的阵列基板，所述扫描线、所述第二分享线、所述第一公共线以及所述第一分享线同层设置。
  6. 根据权利要求4所述的阵列基板，每一所述像素单元均还包括：
    主像素电极，设置于所述主像素区内，所述主像素电极包括平行于所述数据线的第一主干电极；
    次像素电极，设置于所述次像素区内，所述次像素电极包括平行于所述数据线的第二主干电极；
    主像素薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述数据线，其漏极电连接至所述主像素电极；
    次像素薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述数据线，其漏极电连接至所述次像素电极；以及
    分享薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述次像素薄膜晶体管的漏极，其漏极电连接至所述第二分享线。
  7. 根据权利要求6所述的阵列基板，每一所述像素单元均还包括：
    第三分享线，其一端电连接至所述第二分享线，其另一端且沿着所述第一轴线由一所述像素单元的次像素区延伸至相邻的所述像素单元的主像素区。
  8. 根据权利要求6所述的阵列基板，每一所述像素单元均还包括：
    第二公共线，其一端电连接至所述第一公共线，其另一端沿着所述第一轴线由一所述像素单元的主像素区延伸至相邻的所述像素单元的次像素区。
  9. 根据权利要求7所述的阵列基板，所述主像素区内的所述第三分享线与所述第一主干电极对应设置，所述次像素区内的所述第三分享线与所述第二主干电极对应设置。
  10. 一种显示面板，包括阵列基板、与所述阵列基板对应设置的彩膜基板以及设置于所述阵列基板与所述彩膜基板之间的液晶层；
    所述阵列基板包括基板及阵列排布于所述基板上的多个像素单元；
    每一所述像素单元均包括：
    数据线，设置于所述基板上；
    扫描线，设置于所述基板上，且与所述数据线相互交错设置；以及
    第一分享线，设置于所述基板与所述数据线之间，且平行于所述数据线。
  11. 根据权利要求10所述的显示面板，所述第一分享线具有平行于所述数据线的第一中轴线；所述数据线具有平行于所述第一分享线的第二中轴线；所述第一中轴线与所述第二中轴线相互重合。
  12. 根据权利要求11所述的显示面板，所述第一分享线和所述数据线的宽度均匀设置，且所述第一分享线的宽度大于或等于所述数据线的宽度。
  13. 根据权利要求10所述的显示面板，每一所述像素单元均分为主像素区和次像素区；所述扫描线设置于所述主像素区和所述次像素区之间；
    每一所述像素单元均还包括：
    第二分享线，平行于所述扫描线，且设置于所述扫描线与所述次像素区之间；以及
    第一公共线，平行于所述扫描线，且设置于所述扫描线与所述主像素区之间；
    其中，每一所述第一分享线的一端电连接至所述第二分享线，另一端沿着所述第一轴线由一所述像素单元的次像素区延伸至相邻的所述像素单元的主像素区。
  14. 根据权利要求13所述的显示面板，所述扫描线、所述第二分享线、所述第一公共线以及所述第一分享线同层设置。
  15. 根据权利要求13所述的显示面板，每一所述像素单元均还包括：
    主像素电极，设置于所述主像素区内，所述主像素电极包括平行于所述数据线的第一主干电极；
    次像素电极，设置于所述次像素区内，所述次像素电极包括平行于所述数据线的第二主干电极；
    主像素薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述数据线，其漏极电连接至所述主像素电极；
    次像素薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述数据线，其漏极电连接至所述次像素电极；以及
    分享薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述次像素薄膜晶体管的漏极，其漏极电连接至所述第二分享线。
  16. 根据权利要求15所述的显示面板，每一所述像素单元均还包括：
    第三分享线，其一端电连接至所述第二分享线，其另一端且沿着所述第一轴线由一所述像素单元的次像素区延伸至相邻的所述像素单元的主像素区。
  17. 根据权利要求15所述的显示面板，每一所述像素单元均还包括：
    第二公共线，其一端电连接至所述第一公共线，其另一端沿着所述第一轴线由一所述像素单元的主像素区延伸至相邻的所述像素单元的次像素区。
  18. 根据权利要求16所述的显示面板，所述主像素区内的所述第三分享线与所述第一主干电极对应设置，所述次像素区内的所述第三分享线与所述第二主干电极对应设置。
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