WO2023070725A1 - 一种阵列基板及显示面板 - Google Patents

一种阵列基板及显示面板 Download PDF

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Publication number
WO2023070725A1
WO2023070725A1 PCT/CN2021/128862 CN2021128862W WO2023070725A1 WO 2023070725 A1 WO2023070725 A1 WO 2023070725A1 CN 2021128862 W CN2021128862 W CN 2021128862W WO 2023070725 A1 WO2023070725 A1 WO 2023070725A1
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WIPO (PCT)
Prior art keywords
sub
line
pixel
sharing
electrode
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Application number
PCT/CN2021/128862
Other languages
English (en)
French (fr)
Inventor
肖军城
李吉
龙芬
赵迎春
葛茹
Original Assignee
Tcl华星光电技术有限公司
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Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to JP2021568340A priority Critical patent/JP7542009B2/ja
Priority to KR1020217038478A priority patent/KR20230062316A/ko
Priority to US17/614,389 priority patent/US11982914B2/en
Priority to EP21815345.0A priority patent/EP4425249A1/en
Publication of WO2023070725A1 publication Critical patent/WO2023070725A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133753—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers with different alignment orientations or pretilt angles on a same surface, e.g. for grey scale or improved viewing angle
    • G02F1/133757—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers with different alignment orientations or pretilt angles on a same surface, e.g. for grey scale or improved viewing angle with different alignment orientations
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a display panel.
  • liquid crystal display panel has a large difference in birefringence of liquid crystal molecules under different viewing angles, and serious color shift.
  • High Vertical Alignment (English full name: High Vertical Alignment, HVA for short) liquid crystal display panel needs to design multi-domain display to improve color shift. Based on the electrical principle, the pixel unit is divided into the main pixel (full name in English: main pixel) area and the sub-pixel (full name in English: sub pixel) area with different rotation angles of liquid crystal molecules. 8 domain is displayed.
  • the current 8domain display is to control the main pixel electrode through a main pixel thin film transistor, and jointly control the sub pixel electrode through the sub pixel thin film transistor and the shared thin film transistor to realize different potentials of the main pixel electrode and the sub pixel electrode.
  • This design can control the sub pixel electrode separately Pixel electrode bias to achieve low color shift (English full name: Low color shift) and afterimage optimization.
  • the current sharing electrode line 100' (English full name: share bar) of the shared thin film transistor runs through the middle of the main pixel area and the sub-pixel area, thereby reducing the light transmission area of the pixel unit , to reduce the aperture ratio of the pixel unit;
  • the current common line 200' of the shared thin film transistor is the first layer of metal wiring, the shared electrode line 100' is the second layer of metal wiring, and the shared electrode line 100' covers the common line 200' above, thus reducing the transmittance of the pixel unit.
  • the object of the present invention is to provide an array substrate and a display panel, which can solve the problems of low aperture ratio and low transmittance of pixel units existing in the prior art.
  • the present invention provides an array substrate, which includes a substrate and a plurality of pixel units arrayed on the substrate; each of the pixel units is divided into a main pixel area and a sub-pixel area; each Each of the pixel units includes: a data line arranged between adjacent pixel units; a scanning line arranged on the substrate interlaced with the data line and located in the main pixel area and the sub-pixel between regions; a first common line, disposed on the substrate on the side of the scanning line close to the main pixel region, and parallel to the scanning line; and a first sharing line, disposed on the scanning line on the substrate near the side of the sub-pixel region and parallel to the scan line.
  • first common line, the first sharing line and the scanning line are arranged on the same layer.
  • each of the pixel units also includes: a main pixel electrode arranged in the main pixel area, the main pixel electrode includes a first trunk electrode parallel to the data line; a sub-pixel electrode arranged in the In the sub-pixel area, the sub-pixel electrode includes a second main electrode parallel to the data line; the main pixel thin film transistor, its gate is electrically connected to the scanning line, and its source is electrically connected to the data line.
  • the sub-pixel thin film transistor its gate is electrically connected to the scanning line, its source is electrically connected to the data line, and its drain is electrically connected to the sub-pixel a pixel electrode; and a sharing thin film transistor, the gate of which is electrically connected to the scanning line, the source of which is electrically connected to the drain of the sub-pixel thin film transistor, and the drain of which is electrically connected to the first sharing line.
  • each of the pixel units also includes: a second common line parallel to the data line, one end of which is electrically connected to the first common line, and the other end is connected along the extending direction of the data line by a
  • the main pixel area of the pixel unit extends to the sub-pixel area of the adjacent pixel unit.
  • the second common line includes a first sub-common line, a second sub-common line and a third sub-common line arranged at intervals; in the main pixel area, the first sub-common line is arranged on the Between the main pixel electrode and the data line, the second sub-common line is arranged on the side of the main pixel electrode away from the data line, and the third sub-common line corresponds to the first main electrode Setting; in the sub-pixel area, the first sub-common line is disposed between the sub-pixel electrode and the data line, and the second sub-common line is disposed on the sub-pixel electrode away from the data line On one side of the line, the third sub-common line is arranged correspondingly to the second trunk electrode.
  • each of the pixel units also includes: a second sharing line parallel to the data line, one end of which is electrically connected to the first sharing line, and the other end is connected along the extending direction of the data line by a The sub-pixel area of the pixel unit extends to the main pixel area of the adjacent pixel unit.
  • the second sharing line includes a first sub-sharing line, a second sub-sharing line and a third sub-sharing line arranged at intervals; in the main pixel area, the first sub-sharing line is set on the Between the main pixel electrode and the data line, the second sub-sharing line is arranged on the side of the main pixel electrode away from the data line, and the third sub-sharing line corresponds to the first main electrode Setting; in the sub-pixel area, the first sub-sharing line is set between the sub-pixel electrode and the data line, and the second sub-sharing line is set on the sub-pixel electrode away from the data line On one side of the line, the third sub-sharing line is arranged correspondingly to the second trunk electrode.
  • the scanning line, the second common line and the second sharing line are arranged on the same layer.
  • the first main electrode is stacked on the side of the third sub-common line away from the substrate; in the sub-pixel area, the second main electrode is stacked disposed on the side of the third sub-common line away from the substrate; or in the main pixel region, the first trunk electrode is stacked and disposed on the side of the third sub-common line away from the substrate; In the sub-pixel region, the second stem electrode is stacked on a side of the third sub-sharing line away from the substrate.
  • the present invention provides a display panel, which includes the array substrate of the present invention, a color filter substrate corresponding to the array substrate, and a color filter substrate arranged between the array substrate and the color filter substrate. the liquid crystal layer.
  • the first common line and the first sharing line are respectively arranged on both sides of the scanning line, thereby avoiding the first sharing line in the prior art from penetrating through the main pixel area and the sub-pixel area, thereby improving the efficiency of the pixel unit.
  • the first common line, the first sharing line and the scanning line are arranged in the same layer, thereby further improving the penetration rate of the pixel unit.
  • FIG. 1 is a schematic plan view of a pixel unit of an array substrate in the prior art
  • Fig. 2 is the A-A sectional view of Fig. 1;
  • FIG. 3 is a schematic plan view of an array substrate according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic plan view of a pixel unit of the array substrate according to Embodiment 1 of the present invention.
  • Fig. 5 is a B-B sectional view among Fig. 4;
  • FIG. 6 is a partial plan view of two pixel units of the array substrate according to Embodiment 1 of the present invention.
  • Fig. 7 is a C-C sectional view among Fig. 4;
  • Fig. 8 is a D-D sectional view among Fig. 4;
  • FIG. 9 is a driving circuit diagram of the array substrate according to Embodiment 1 of the present invention.
  • FIG. 10 is a schematic plan view of a pixel unit of the array substrate according to Embodiment 2 of the present invention.
  • FIG. 11 is a partial plan view of two pixel units of the array substrate according to Embodiment 2 of the present invention.
  • Fig. 12 is the E-E sectional view among Fig. 10;
  • Fig. 13 is a cross-sectional view taken along line F-F in Fig. 10 .
  • the first trunk electrode 51.
  • the first trunk electrode 61.
  • the second trunk electrode 62.
  • the display panel includes an array substrate, a color filter substrate corresponding to the array substrate, and a liquid crystal layer arranged between the array substrate and the color filter substrate.
  • the array substrate 100 includes: a substrate 101 and a plurality of pixel units 102 arrayed on the substrate 101 .
  • the material of substrate 101 is one or more in glass, polyimide, polycarbonate, polyethylene terephthalate and polyethylene naphthalate, thus substrate 101 can have Good impact resistance can effectively protect the display panel.
  • each pixel unit 102 is divided into a main pixel area 1021 and a sub-pixel area 1022 .
  • Each pixel unit 102 includes: a scanning line 1, a first common line 2, a first sharing line 3, a data line 4, a main pixel electrode 5, a sub-pixel electrode 6, a main pixel TFT 7, a sub-pixel TFT 8. Sharing the thin film transistor 9 and the second common line 10 .
  • the scan lines 1 and the data lines 4 are arranged alternately on the substrate 101 and located between the main pixel area 1021 and the sub-pixel area 1022 .
  • the scan line 1 is made of metal.
  • the material of the scan line 1 may also be other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, stacked layers of metal materials and other conductive materials, or other suitable materials.
  • the first common line 2 is disposed on the substrate 101 on the side of the scan line 1 close to the main pixel region 1021 .
  • the first common line 2 is parallel to the scan line 1 and spaced apart from the scan line 1 .
  • the material of the first common line 2 is metal.
  • the material of the first common line 2 may also be other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, stacked layers of metal materials and other conductive materials, or other suitable materials.
  • the first sharing lines 3 are arranged at intervals on the substrate 101 on the side of the scanning line 1 close to the sub-pixel region 1022 .
  • the first sharing line 3 is parallel to the scanning line 1 and spaced apart from the scanning line 1 .
  • the material of the first sharing line 3 is metal.
  • the material of the first sharing line 3 may also be other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, stacked layers of metal materials and other conductive materials, or other suitable materials.
  • the scanning line 1 , the first common line 2 and the first sharing line 3 are arranged on the same layer.
  • the materials of the scanning lines 1 , the first common lines 2 and the first sharing lines 3 are the same, so they can be prepared and formed in one process at the same time, thereby saving process steps and production costs.
  • the first common line 2 and the first sharing line 3 are respectively arranged on both sides of the scanning line 1, thereby avoiding the first sharing line 100' in the prior art to pass through the main pixel area 1021 and the sub-pixel region 1022 , thereby increasing the aperture ratio and transmittance of the pixel unit 102 .
  • the first common line 2 , the first sharing line 3 and the scanning line 1 are arranged on the same layer, thereby further improving the transmittance of the pixel unit 102 .
  • the data lines 4 are arranged between the adjacent pixel units 102 and interlaced with the scanning lines 1 .
  • the extending direction of the data lines 4 is not parallel to the extending direction of the scanning lines 1 .
  • the extending direction of the data lines 4 and the extending direction of the scanning lines 1 are perpendicular to each other.
  • the material of the data line 4 is metal.
  • the material of the data line 4 may also be other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, stacked layers of metal materials and other conductive materials, or other suitable materials.
  • the main pixel electrode 5 is disposed in the main pixel region 1021 .
  • the main pixel electrode 5 includes a first main electrode 51 parallel to the data line 4 .
  • the sub-pixel electrode 6 is disposed in the sub-pixel region 1022 .
  • the sub-pixel electrode 6 includes a second stem electrode 61 parallel to the data line 4 .
  • one end of the second common line 10 is electrically connected to the first common line 2, and the other end is connected to the main pixel area of the pixel unit 102 along the extending direction of the data line 4. 1021 extends to the sub-pixel region 1022 of the adjacent pixel unit 102 .
  • the second common line 10 is parallel to the data line 4 and spaced apart from the data line 4 . Wherein, the second common line 10 is set on the same layer as the scanning line 1 , the first common line 2 and the first sharing line 3 .
  • the second common line 10 includes a first sub-common line 110 , a second sub-common line 120 and a third sub-common line 130 arranged at intervals.
  • the first sub-common line 110 is arranged between the main pixel electrode 5 and the data line 4, and the second The sub-common line 120 is disposed on a side of the main pixel electrode 5 away from the data line 4 , and the third sub-common line 130 is disposed corresponding to the first trunk electrode 51 .
  • the first main electrode layer 51 is stacked on the side of the third sub-common line 130 away from the substrate 101 . In this way, an additional occupation of the light-transmitting area of the array substrate 100 can be avoided, and the aperture ratio of the array substrate 100 can be increased.
  • the first sub-common line 110 is arranged between the sub-pixel electrode 6 and the data line 4, and the second The sub-common line 120 is disposed on the side of the sub-pixel electrode 6 away from the data line 4 , and the third sub-common line 130 is disposed corresponding to the second trunk electrode 61 .
  • the second main electrode layer 61 is stacked on the side of the third sub-common line 130 away from the substrate 101 . In this way, an additional occupation of the light-transmitting area of the array substrate 100 can be avoided, and the aperture ratio of the array substrate 100 can be improved.
  • the gate of the main pixel thin film transistor 7 (ie T1 in Figure 9) is electrically connected to the scanning line 1 (ie Gate in Figure 9); the main pixel thin film transistor 7 (that is, T1 in FIG. 9 ) source is electrically connected to the data line 4 (that is, Data in FIG. 9 ), and the drain of the main pixel thin film transistor 7 (that is, T1 in FIG. 9 ) is electrically connected to The main pixel electrode 5 .
  • the gate of the sub-pixel thin film transistor 8 (ie T2 in Figure 9) is electrically connected to the scan line 1 (ie Gate in Figure 9); the sub-pixel thin film transistor 8 (that is, T2 in FIG. 9 ) is electrically connected to the data line 4 (that is, Data in FIG. 9 ), and the drain of the sub-pixel thin film transistor 8 (that is, T2 in FIG. 9 ) is electrically connected to The sub-pixel electrode 6 .
  • the gate of the shared thin film transistor 9 (that is, T3 in FIG. 9 ) is electrically connected to the scan line 1 (that is, the Gate in FIG. 9 ); the shared thin film transistor 9 ( That is, the source of T3 in FIG. 9 ) is electrically connected to the drain of the sub-pixel thin film transistor 8 (that is, T2 in FIG. 9 ), and the drain of the shared thin film transistor 9 (that is, T3 in FIG. 9 ) Connect to the first sharing line 3.
  • the gate of the main pixel thin film transistor 7, the gate of the sub-pixel thin film transistor 8 and the gate of the sharing thin film transistor 9 are electrically connected to the same scanning line 1; the main pixel thin film transistor 7 The source of the sub-pixel thin film transistor 8 is electrically connected to the same data line 4 .
  • Embodiment 2 includes most of the technical features of Embodiment 1.
  • the difference between Embodiment 2 and Embodiment 1 is that the second common line 10 of Embodiment 1 is removed in Embodiment 2.
  • a second sharing line 11 is provided.
  • one end of the second sharing line 11 is electrically connected to the first sharing line 3 , and the other end is connected to the sub-pixel area of the pixel unit 102 along the extending direction of the data line 4 1022 extends to the main pixel area 1021 of the adjacent pixel unit 102 .
  • the second sharing line 11 is parallel to the data line and spaced apart from the data line 4 .
  • the second sharing line 11 is arranged on the same layer as the scanning line 1 , the first common line 2 and the first sharing line 3 .
  • the second sharing line 11 includes a first sub-sharing line 111 , a second sub-sharing line 112 and a third sub-sharing line 113 arranged at intervals.
  • the first sub-sharing line 111 is arranged between the main pixel electrode 5 and the data line 4, and the second The sub-sharing line 112 is disposed on a side of the main pixel electrode 5 away from the data line 4 , and the third sub-sharing line 113 is disposed corresponding to the first trunk electrode 51 .
  • the first main electrode 51 is stacked on the side of the third sub-sharing line 113 away from the substrate 101 . In this way, an additional occupation of the light-transmitting area of the array substrate 100 can be avoided, and the aperture ratio of the array substrate 100 can be improved.
  • the first sub-sharing line 111 is arranged between the sub-pixel electrode 6 and the data line 4, and the second The sub-sharing line 112 is disposed on the side of the sub-pixel electrode 6 away from the data line 4 , and the third sub-sharing line 113 is disposed corresponding to the second main electrode 61 .
  • the second main electrode 61 is stacked on the side of the third sub-sharing line 113 away from the substrate 101 . In this way, an additional occupation of the light-transmitting area of the array substrate 100 can be avoided, and the aperture ratio of the array substrate 100 can be improved.
  • the first common line 2 and the first sharing line 3 are respectively arranged on both sides of the scanning line 1, thereby avoiding the first sharing line 100' in the prior art to pass through the main pixel area 1021 and the sub-pixel region 1022 , thereby increasing the aperture ratio and transmittance of the pixel unit 102 .
  • the first common line 2 , the first sharing line 3 and the scanning line 1 are arranged on the same layer, thereby further improving the transmittance of the pixel unit 102 .

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Abstract

本发明涉及一种阵列基板及显示面板。本发明将第一公共线和第一分享线分别设置于扫描线的两侧，由此避免现有技术中的第一分享线纵穿所述主像素区和次像素区，进而提升阵列基板的开口率和穿透率。将第一公共线、第一分享线以及扫描线同层设置，由此进一步提升阵列基板的穿透率。

Description

一种阵列基板及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及显示面板。
 背景技术
目前，垂直配向型（英文全称：Vertical Alignment，简称VA）液晶显示面板在不同视角下，液晶分子双折射率的差异较大，色偏较严重。高垂直配向型（英文全称：High Vertical Alignment，简称HVA）液晶显示面板需设计多畴显示以改善色偏。基于电学原理，将像素单元分为液晶分子转动角度不同的主像素（英文全称：main pixel）区和次像素（英文全称：sub pixel）区，结合物理结构上的 4 畴（domain），可以实现8 domain显示。
目前的8domain显示是通过一个主像素薄膜晶体管控制主像素电极，通过次像素薄膜晶体管和分享薄膜晶体管共同控制次像素电极，实现主像素电极和次像素电极的不同电位，这种设计可单独控制次像素电极偏压，实现低色偏（英文全称：Low color shift）和残像优化。
 技术问题
如图1、图2所示，目前的分享薄膜晶体管的分享电极线100’（英文全称：share bar）纵穿主像素区及次像素区的中间，由此会减小像素单元的透光面积，降低像素单元的开口率；目前的分享薄膜晶体管的公共线200’为第一层金属走线，分享电极线100’为第二层金属走线，分享电极线100’覆盖于公共线200’上方，由此会降低像素单元的穿透率。
 技术解决方案
本发明的目的是提供一种阵列基板及显示面板，其能够解决现有技术中存在的像素单元开口率低下及穿透率低下等问题。
为了解决上述问题，本发明提供了一种阵列基板，其包括基板及阵列排布于所述基板上的多个像素单元；每一所述像素单元均分为主像素区和次像素区；每一所述像素单元均包括：数据线，设置于相邻所述像素单元之间；扫描线，与所述数据线交错设置于所述基板上，且位于所述主像素区和所述次像素区之间；第一公共线，设置于所述扫描线靠近所述主像素区的一侧的所述基板上，且平行于所述扫描线；以及第一分享线，设置于所述扫描线靠近所述次像素区的一侧的所述基板上，且平行于所述扫描线。
进一步的，所述第一公共线、所述第一分享线以及所述扫描线同层设置。
进一步的，每一所述像素单元均还包括：主像素电极，设置于所述主像素区内，所述主像素电极包括平行于所述数据线的第一主干电极；次像素电极，设置于所述次像素区内，所述次像素电极包括平行于所述数据线的第二主干电极；主像素薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述数据线，其漏极电连接至所述主像素电极；次像素薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述数据线，其漏极电连接至所述次像素电极；以及分享薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述次像素薄膜晶体管的漏极，其漏极电连接至所述第一分享线。
进一步的，每一所述像素单元均还包括：第二公共线，平行于所述数据线，其一端电连接至所述第一公共线，另一端沿着所述数据线的延伸方向由一所述像素单元的主像素区延伸至相邻的所述像素单元的次像素区。
进一步的，所述第二公共线包括相互间隔设置的第一子公共线、第二子公共线以及第三子公共线；在所述主像素区内，所述第一子公共线设置于所述主像素电极与所述数据线之间，所述第二子公共线设置于所述主像素电极远离所述数据线的一侧，所述第三子公共线与所述第一主干电极对应设置；在所述次像素区内，所述第一子公共线设置于所述次像素电极与所述数据线之间，所述第二子公共线设置于所述次像素电极远离所述数据线的一侧，所述第三子公共线与所述第二主干电极对应设置。
进一步的，每一所述像素单元均还包括：第二分享线，平行于所述数据线，其一端电连接至所述第一分享线，另一端沿着所述数据线的延伸方向由一所述像素单元的次像素区延伸至相邻的所述像素单元的主像素区。
进一步的，所述第二分享线包括相互间隔设置的第一子分享线、第二子分享线以及第三子分享线；在所述主像素区内，所述第一子分享线设置于所述主像素电极与所述数据线之间，所述第二子分享线设置于所述主像素电极远离所述数据线的一侧，所述第三子分享线与所述第一主干电极对应设置；在所述次像素区内，所述第一子分享线设置于所述次像素电极与所述数据线之间，所述第二子分享线设置于所述次像素电极远离所述数据线的一侧，所述第三子分享线与所述第二主干电极对应设置。
进一步的，所述扫描线、所述第二公共线以及所述第二分享线同层设置。
进一步的，在所述主像素区内，所述第一主干电极层叠设置于所述第三子公共线远离所述基板的一侧；在所述次像素区内，所述第二主干电极层叠设置于所述第三子公共线远离所述基板的一侧；或者在所述主像素区内，所述第一主干电极层叠设置于所述第三子分享线远离所述基板的一侧；在所述次像素区内，所述第二主干电极层叠设置于所述第三子分享线远离所述基板的一侧。
为了解决上述问题，本发明提供了一种显示面板，其包括本发明所述的阵列基板、与所述阵列基板对应设置的彩膜基板以及设置于所述阵列基板与所述彩膜基板之间的液晶层。
 有益效果
本发明将第一公共线和第一分享线分别设置于扫描线的两侧，由此避免现有技术中的第一分享线纵穿所述主像素区和次像素区，进而提升像素单元的开口率和穿透率。将第一公共线、第一分享线以及扫描线同层设置，由此进一步提升像素单元的穿透率。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术的阵列基板的一个像素单元的平面示意图；
图2是图1的A-A截面图；
图3是本发明实施例1的阵列基板的平面示意图；
图4是本发明实施例1的阵列基板的一个像素单元的平面示意图；
图5是图4中的B-B截面图；
图6是本发明实施例1的阵列基板的两个像素单元的局部平面示意图；
图7是图4中的C-C截面图；
图8是图4中的D-D截面图；
图9是本发明实施例1的阵列基板的驱动电路图；
图10是本发明实施例2的阵列基板的一个像素单元的平面示意图；
图11是本发明实施例2的阵列基板的两个像素单元的局部平面示意图。
图12是图10中的E-E截面图；
图13是图10中的F-F截面图。
附图标记说明：
100、阵列基板；                   101、基板；
102、像素单元；
1021、主像素区；                  1022、次像素区；
1、扫描线；                       2、第一公共线；
3、第一分享线；                   4、数据线；
5、主像素电极；                   6、次像素电极；
7、主像素薄膜晶体管；             8、次像素薄膜晶体管；
9、分享薄膜晶体管；               10、第二公共线；
11、第二分享线；
110、第一子公共线；               120、第二子公共线；
130、第三子公共线；
111、第一子分享线；               112、第二子分享线；
113、第三子分享线；
51、第一主干电极；                61、第二主干电极。
 本发明的实施方式
以下结合说明书附图详细说明本发明的优选实施例，以向本领域中的技术人员完整介绍本发明的技术内容，以举例证明本发明可以实施，使得本发明公开的技术内容更加清楚，使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例，下文实施例的说明并非用来限制本发明的范围。
本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，本文所使用的方向用语是用来解释和说明本发明，而不是用来限定本发明的保护范围。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。此外，为了便于理解和描述，附图所示的每一组件的尺寸和厚度是任意示出的 ，本发明并没有限定每个组件的尺寸和厚度。
实施例1
本实施例提供了一种显示面板。所述显示面板包括阵列基板、与所述阵列基板对应设置的彩膜基板以及设置于所述阵列基板与所述彩膜基板之间的液晶层。
如图3所示，所述阵列基板100包括：基板101及阵列排布于所述基板101上的多个像素单元102。
其中，基板101的材质为玻璃、聚酰亚胺、聚碳酸酯、聚对苯二甲酸乙二醇酯以及聚萘二甲酸乙二醇酯中的一种或多种，由此基板101可具有较好的抗冲击能力，可以有效保护显示面板。
如图4所示，每一所述像素单元102均分为主像素区1021和次像素区1022。每一所述像素单元102均包括：扫描线1、第一公共线2、第一分享线3、数据线4、主像素电极5、次像素电极6、主像素薄膜晶体管7、次像素薄膜晶体管8、分享薄膜晶体管9以及第二公共线10。
如图4、图5及图6所示，扫描线1与所述数据线4交错设置于所述基板101上，且位于所述主像素区1021和所述次像素区1022之间。本实施例中，所述扫描线1的材质为金属。在其他实施例中，所述扫描线1的材质也可以是其他导电材料。例如：合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物、或是金属材料与其他导电材料的堆叠层或其他合适的材料。
如图4、图5及图6所示，第一公共线2设置于所述扫描线1靠近所述主像素区1021的一侧的所述基板101上。所述第一公共线2平行于所述扫描线1，且与所述扫描线1间隔设置。本实施例中，所述第一公共线2的材质为金属。在其他实施例中，所述第一公共线2的材质也可以是其他导电材料。例如：合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物、或是金属材料与其他导电材料的堆叠层或其他合适的材料。
如图4、图5及图6所示，第一分享线3间隔设置于所述扫描线1靠近所述次像素区1022的一侧的所述基板101上。所述第一分享线3平行于所述扫描线1，且与所述扫描线1间隔设置。本实施例中，所述第一分享线3的材质为金属。在其他实施例中，所述第一分享线3的材质也可以是其他导电材料。例如：合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物、或是金属材料与其他导电材料的堆叠层或其他合适的材料。
其中，所述扫描线1、所述第一公共线2以及所述第一分享线3同层设置。本实施例中，所述扫描线1、所述第一公共线2以及所述第一分享线3的材质相同，由此可以在一道工序内同时制备形成，进而可以节省工序，节约生产成本。
本实施例将第一公共线2和第一分享线3分别设置于扫描线1的两侧，由此避免现有技术中的第一分享线100’纵穿所述主像素区1021和次像素区1022，进而提升像素单元102的开口率和穿透率。将第一公共线2、第一分享线3以及扫描线1同层设置，由此进一步提升像素单元102的穿透率。
如图4、图6所示，数据线4设置于相邻所述像素单元102之间，且与所述扫描线1相互交错设置。换言之，所述数据线4的延伸方向和扫描线1的延伸方向不平行。本实施例中，所述数据线4的延伸方向与扫描线1的延伸方向相互垂直。本实施例中，所述数据线4的材质为金属。在其他实施例中，所述数据线4的材质也可以是其他导电材料。例如：合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物、或是金属材料与其他导电材料的堆叠层或其他合适的材料。
如图4、图6、图7所示，主像素电极5设置于所述主像素区1021内。主像素电极5包括平行于所述数据线4的第一主干电极51。
如图4、图6、图8所示，次像素电极6设置于所述次像素区1022内。次像素电极6包括平行于所述数据线4的第二主干电极61。
如图4、图6所示，第二公共线10的一端电连接至所述第一公共线2，另一端沿着所述数据线4的延伸方向由一所述像素单元102的主像素区1021延伸至相邻的所述像素单元102的次像素区1022。第二公共线10平行于所述数据线4，且与所述数据线4间隔设置。其中，所述第二公共线10与所述扫描线1、所述第一公共线2以及所述第一分享线3同层设置。
如图4、图6所示，所述第二公共线10包括相互间隔设置的第一子公共线110、第二子公共线120以及第三子公共线130。
如图4、图6、图7所示，在所述主像素区1021内，所述第一子公共线110设置于所述主像素电极5与所述数据线4之间，所述第二子公共线120设置于所述主像素电极5远离所述数据线4的一侧，所述第三子公共线130与所述第一主干电极51对应设置。在所述主像素区1021内，所述第一主干电极层51叠设置于所述第三子公共线130远离所述基板101的一侧。由此可以避免额外占用阵列基板100的透光面积，提升阵列基板100的开口率。
如图4、图6、图8所示，在所述次像素区1022内，所述第一子公共线110设置于所述次像素电极6与所述数据线4之间，所述第二子公共线120设置于所述次像素电极6远离所述数据线4的一侧，所述第三子公共线130与所述第二主干电极61对应设置。在所述次像素区1022内，所述第二主干电极层61叠设置于所述第三子公共线130远离所述基板101的一侧。由此可以避免额外占用阵列基板100的透光面积，提升阵列基板100的开口率。
如图4、图9所示，所述主像素薄膜晶体管7（即图9中的T1）的栅极电连接至所述扫描线1（即图9中的Gate）；所述主像素薄膜晶体管7（即图9中的T1）的源极电连接至所述数据线4（即图9中的Data），所述主像素薄膜晶体管7（即图9中的T1）的漏极电连接至所述主像素电极5。
如图4、图9所示，所述次像素薄膜晶体管8（即图9中的T2）的栅极电连接至所述扫描线1（即图9中的Gate）；所述次像素薄膜晶体管8（即图9中的T2）的源极电连接至所述数据线4（即图9中的Data），所述次像素薄膜晶体管8（即图9中的T2）的漏极电连接至所述次像素电极6。
如图4、图9所示，所述分享薄膜晶体管9（即图9中的T3）的栅极电连接至所述扫描线1（即图9中的Gate）；所述分享薄膜晶体管9（即图9中的T3）的源极电连接至所述次像素薄膜晶体管8（即图9中的T2）的漏极，所述分享薄膜晶体管9（即图9中的T3）的漏极电连接至所述第一分享线3。
其中，所述主像素薄膜晶体管7的栅极、所述次像素薄膜晶体管8的栅极和所述分享薄膜晶体管9的栅极电连接至同一所述扫描线1；所述主像素薄膜晶体管7的源极和所述次像素薄膜晶体管8的源极电连接至同一条所述数据线4。
实施例2
如图10-图13所示，实施例2包括了实施例1的大部分技术特征，实施例2与实施例1的区别在于：实施例2中去除了实施例1的第二公共线10，在实施例1的第二公共线10的位置处设置了第二分享线11。
如图10、图11所示，第二分享线11的一端电连接至所述第一分享线3，另一端沿着所述数据线4的延伸方向由一所述像素单元102的次像素区1022延伸至相邻的所述像素单元102的主像素区1021。第二分享线11平行于所述数据线，且与所述数据线4间隔设置。其中，第二分享线11与所述扫描线1、所述第一公共线2以及所述第一分享线3同层设置。
如图10、图11所示，所述第二分享线11包括相互间隔设置的第一子分享线111、第二子分享线112以及第三子分享线113。
如图10、图11、图12所示，在所述主像素区1021内，所述第一子分享线111设置于所述主像素电极5与所述数据线4之间，所述第二子分享线112设置于所述主像素电极5远离所述数据线4的一侧，所述第三子分享线113与所述第一主干电极51对应设置。在所述主像素区1021内，所述第一主干电极51层叠设置于所述第三子分享线113远离所述基板101的一侧。由此可以避免额外占用阵列基板100的透光面积，提升阵列基板100的开口率。
如图10、图11、图13所示，在所述次像素区1022内，所述第一子分享线111设置于所述次像素电极6与所述数据线4之间，所述第二子分享线112设置于所述次像素电极6远离所述数据线4的一侧，所述第三子分享线113与所述第二主干电极61对应设置。在所述次像素区1022内，所述第二主干电极61层叠设置于所述第三子分享线113远离所述基板101的一侧。由此可以避免额外占用阵列基板100的透光面积，提升阵列基板100的开口率。
本实施例将第一公共线2和第一分享线3分别设置于扫描线1的两侧，由此避免现有技术中的第一分享线100’纵穿所述主像素区1021和次像素区1022，进而提升像素单元102的开口率和穿透率。将第一公共线2、第一分享线3以及扫描线1同层设置，由此进一步提升像素单元102的穿透率。
以上对本申请所提供的一种阵列基板及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，包括基板及阵列排布于所述基板上的多个像素单元；每一所述像素单元均分为主像素区和次像素区；
    每一所述像素单元均包括：
    数据线，设置于相邻所述像素单元之间；
    扫描线，与所述数据线交错设置于所述基板上，且位于所述主像素区和所述次像素区之间；
    第一公共线，设置于所述扫描线靠近所述主像素区的一侧的所述基板上，且平行于所述扫描线；以及
    第一分享线，设置于所述扫描线靠近所述次像素区的一侧的所述基板上，且平行于所述扫描线。
  2. 根据权利要求1所述的阵列基板，所述第一公共线、所述第一分享线以及所述扫描线同层设置。
  3. 根据权利要求1所述的阵列基板，每一所述像素单元均还包括：
    主像素电极，设置于所述主像素区内，所述主像素电极包括平行于所述数据线的第一主干电极；
    次像素电极，设置于所述次像素区内，所述次像素电极包括平行于所述数据线的第二主干电极；
    主像素薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述数据线，其漏极电连接至所述主像素电极；
    次像素薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述数据线，其漏极电连接至所述次像素电极；以及
    分享薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述次像素薄膜晶体管的漏极，其漏极电连接至所述第一分享线。
  4. 根据权利要求3所述的阵列基板，每一所述像素单元均还包括：
    第二公共线，平行于所述数据线，其一端电连接至所述第一公共线，另一端沿着所述数据线的延伸方向由一所述像素单元的主像素区延伸至相邻的所述像素单元的次像素区。
  5. 根据权利要求4所述的阵列基板，所述第二公共线包括相互间隔设置的第一子公共线、第二子公共线以及第三子公共线；
    在所述主像素区内，所述第一子公共线设置于所述主像素电极与所述数据线之间，所述第二子公共线设置于所述主像素电极远离所述数据线的一侧，所述第三子公共线与所述第一主干电极对应设置；
    在所述次像素区内，所述第一子公共线设置于所述次像素电极与所述数据线之间，所述第二子公共线设置于所述次像素电极远离所述数据线的一侧，所述第三子公共线与所述第二主干电极对应设置。
  6. 根据权利要求3所述的阵列基板，每一所述像素单元均还包括：
    第二分享线，平行于所述数据线，其一端电连接至所述第一分享线，另一端沿着所述数据线的延伸方向由一所述像素单元的次像素区延伸至相邻的所述像素单元的主像素区。
  7. 根据权利要求6所述的阵列基板，所述第二分享线包括相互间隔设置的第一子分享线、第二子分享线以及第三子分享线；
    在所述主像素区内，所述第一子分享线设置于所述主像素电极与所述数据线之间，所述第二子分享线设置于所述主像素电极远离所述数据线的一侧，所述第三子分享线与所述第一主干电极对应设置；
    在所述次像素区内，所述第一子分享线设置于所述次像素电极与所述数据线之间，所述第二子分享线设置于所述次像素电极远离所述数据线的一侧，所述第三子分享线与所述第二主干电极对应设置。
  8. 根据权利要求4所述的阵列基板，所述扫描线与所述第二公共线同层设置。
  9. 根据权利要求6所述的阵列基板，所述扫描线与所述第二分享线同层设置。
  10. 根据权利要求5所述的阵列基板，在所述主像素区内，所述第一主干电极层叠设置于所述第三子公共线远离所述基板的一侧；在所述次像素区内，所述第二主干电极层叠设置于所述第三子公共线远离所述基板的一侧。
  11. 根据权利要求7所述的阵列基板，在所述主像素区内，所述第一主干电极层叠设置于所述第三子分享线远离所述基板的一侧；在所述次像素区内，所述第二主干电极层叠设置于所述第三子分享线远离所述基板的一侧。
  12. 一种显示面板，包括阵列基板、与所述阵列基板对应设置的彩膜基板以及设置于所述阵列基板与所述彩膜基板之间的液晶层；
    所述阵列基板包括基板及阵列排布于所述基板上的多个像素单元；每一所述像素单元均分为主像素区和次像素区；
    每一所述像素单元均包括：
    数据线，设置于相邻所述像素单元之间；
    扫描线，与所述数据线交错设置于所述基板上，且位于所述主像素区和所述次像素区之间；
    第一公共线，设置于所述扫描线靠近所述主像素区的一侧的所述基板上，且平行于所述扫描线；以及
    第一分享线，设置于所述扫描线靠近所述次像素区的一侧的所述基板上，且平行于所述扫描线。
  13. 根据权利要求12所述的显示面板，所述第一公共线、所述第一分享线以及所述扫描线同层设置。
  14. 根据权利要求12所述的显示面板，每一所述像素单元均还包括：
    主像素电极，设置于所述主像素区内，所述主像素电极包括平行于所述数据线的第一主干电极；
    次像素电极，设置于所述次像素区内，所述次像素电极包括平行于所述数据线的第二主干电极；
    主像素薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述数据线，其漏极电连接至所述主像素电极；
    次像素薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述数据线，其漏极电连接至所述次像素电极；以及
    分享薄膜晶体管，其栅极电连接至所述扫描线，其源极电连接至所述次像素薄膜晶体管的漏极，其漏极电连接至所述第一分享线。
  15. 根据权利要求14所述的显示面板，每一所述像素单元均还包括：
    第二公共线，平行于所述数据线，其一端电连接至所述第一公共线，另一端沿着所述数据线的延伸方向由一所述像素单元的主像素区延伸至相邻的所述像素单元的次像素区。
  16. 根据权利要求15所述的显示面板，所述第二公共线包括相互间隔设置的第一子公共线、第二子公共线以及第三子公共线；
    在所述主像素区内，所述第一子公共线设置于所述主像素电极与所述数据线之间，所述第二子公共线设置于所述主像素电极远离所述数据线的一侧，所述第三子公共线与所述第一主干电极对应设置；
    在所述次像素区内，所述第一子公共线设置于所述次像素电极与所述数据线之间，所述第二子公共线设置于所述次像素电极远离所述数据线的一侧，所述第三子公共线与所述第二主干电极对应设置。
  17. 根据权利要求14所述的显示面板，每一所述像素单元均还包括：
    第二分享线，平行于所述数据线，其一端电连接至所述第一分享线，另一端沿着所述数据线的延伸方向由一所述像素单元的次像素区延伸至相邻的所述像素单元的主像素区。
  18. 根据权利要求17所述的显示面板，所述第二分享线包括相互间隔设置的第一子分享线、第二子分享线以及第三子分享线；
    在所述主像素区内，所述第一子分享线设置于所述主像素电极与所述数据线之间，所述第二子分享线设置于所述主像素电极远离所述数据线的一侧，所述第三子分享线与所述第一主干电极对应设置；
    在所述次像素区内，所述第一子分享线设置于所述次像素电极与所述数据线之间，所述第二子分享线设置于所述次像素电极远离所述数据线的一侧，所述第三子分享线与所述第二主干电极对应设置。
  19. 根据权利要求16所述的显示面板，在所述主像素区内，所述第一主干电极层叠设置于所述第三子公共线远离所述基板的一侧；在所述次像素区内，所述第二主干电极层叠设置于所述第三子公共线远离所述基板的一侧。
  20. 根据权利要求18所述的显示面板，在所述主像素区内，所述第一主干电极层叠设置于所述第三子分享线远离所述基板的一侧；在所述次像素区内，所述第二主干电极层叠设置于所述第三子分享线远离所述基板的一侧。
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