WO2023221200A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2023221200A1
WO2023221200A1 PCT/CN2022/097661 CN2022097661W WO2023221200A1 WO 2023221200 A1 WO2023221200 A1 WO 2023221200A1 CN 2022097661 W CN2022097661 W CN 2022097661W WO 2023221200 A1 WO2023221200 A1 WO 2023221200A1
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WO
WIPO (PCT)
Prior art keywords
common electrode
display panel
electrode
pixel
data line
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PCT/CN2022/097661
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English (en)
French (fr)
Inventor
葛茹
胡晓斌
Original Assignee
广州华星光电半导体显示技术有限公司
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Application filed by 广州华星光电半导体显示技术有限公司 filed Critical 广州华星光电半导体显示技术有限公司
Publication of WO2023221200A1 publication Critical patent/WO2023221200A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present application relates to the field of display, and in particular to a display panel.
  • Fringe Field Switching (FFS) LCD panels have the advantages of high penetration and wide viewing angle, and have been widely used in small and medium-sized displays, especially mobile phone panels.
  • the so-called FFS type liquid crystal display panel uses the boundary electric field to rotate the liquid crystal (LC) molecules in the liquid crystal cell (Cell) in a plane parallel to the substrate, resulting in an optical path difference. Under the action of the upper and lower polarizers, the display effect is achieved.
  • Embodiments of the present application provide a display panel that can improve the problem of crosstalk risk in existing display panels.
  • An embodiment of the present application provides a display panel, which includes:
  • a plurality of data lines each of which is connected to one of the pixel electrodes
  • the first metal layer includes a common electrode line and a first common electrode.
  • the common electrode line at least partially overlaps the pixel electrode.
  • the first common electrode is disposed below the data line and connected to the first common electrode. Common electrode trace connection.
  • this application provides a display panel.
  • the display panel includes a plurality of pixel electrodes, a plurality of data lines, and a first metal layer. Each data line is connected to each pixel electrode.
  • the first metal layer includes Common electrode traces and at least one first common electrode, the common electrode traces are at least partially coupled to the pixel electrodes, and the first common electrode is disposed below the data line and connected to the common electrode traces.
  • FIG. 1 is a first structural schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a partial circuit structure of a pixel electrode provided by an embodiment of the present application.
  • FIG. 3 is a second structural schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of the first metal layer in the display panel shown in FIG. 1 .
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features.
  • features defined as “first” and “second” may explicitly or implicitly include one or more of the described features.
  • “plurality” means two or more than two, unless otherwise explicitly and specifically limited.
  • Fringe Field Switching (FFS) liquid crystal displays are widely used.
  • FFFS Fringe Field Switching
  • the sub-pixel (RGB Stripe) architecture can achieve a higher charging rate, but in the vertical display of the RGB Stripe architecture, due to the existence between the data line and the pixel Capacitive coupling leads to a greater risk of crosstalk.
  • this application proposes a display panel.
  • the present application will be further described below in conjunction with the accompanying drawings and embodiments.
  • Figure 1 is a first structural schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a partial circuit structure of a pixel electrode provided by an embodiment of the present application.
  • An embodiment of the present application provides a display panel 100.
  • the display panel 100 includes a plurality of pixel electrodes 10, a plurality of data lines 20, and a first metal layer, wherein each data line 20 is connected to each pixel electrode 10 for The data signal is transmitted to the corresponding pixel electrode 10 .
  • the first metal layer includes a common electrode trace 40 and at least one first common electrode 410.
  • the common electrode trace 40 at least partially overlaps the pixel electrode 10.
  • the first common electrode 410 is disposed below the data line 20 and is connected to the common electrode trace 410. Line 40 connection.
  • the capacitance of the data line 20 remains unchanged, thereby reducing the proportion of the capacitance of the data line 20 to the pixel electrode 10 in the overall pixel capacitance. Therefore, the pixel is more difficult to be affected by the voltage of the data line 20, thereby reducing the voltage of the data line 20. Capacitive coupling to pixels reduces the risk of crosstalk.
  • the orthographic projection of the first common electrode 410 is within the orthographic projection of the data line 20 .
  • the width of a first common electrode 410 may be less than or equal to the width of a data line 20. In other embodiments, in order to better reduce the risk of crosstalk, the width of a first common electrode 410 may be greater than
  • the width of the data line 20 and the width of the first common electrode 410 need to be set according to the actual situation, and are not specifically limited here.
  • the number of first common electrodes 410 is less than the number of data lines 20 . In other embodiments, in order to better reduce the crosstalk of the data lines 20 on the display panel 100 , each data line 20 can be First common electrodes 410 are provided below, that is, the number of first common electrodes 410 is equal to the number of data lines 20 .
  • the first metal layer further includes a gate line 50 , and the width of the gate line 50 is smaller than the width of the common electrode line 40 .
  • One end of each first common electrode is connected to the common electrode line, the other end of each first common electrode extends in a direction close to the gate line, and there is a gap between each common electrode and the gate line.
  • the first metal layer further includes at least a second common electrode.
  • the second common electrode is disposed below the pixel electrode 10 .
  • the second common electrode is connected to the pixel electrode 10 .
  • the common electrode traces 40 are arranged on the same layer and connected to the common electrode traces 40 .
  • the capacitance remains unchanged, thereby reducing the ratio of the capacitance of the data line 20 to the pixel electrode 10 in the total pixel capacitance. Therefore, the pixel is more difficult to be affected by the voltage of the data line 20, thereby reducing the ratio of the data line 20 to the pixel. Capacitive coupling reduces the risk of crosstalk.
  • the second common electrode in order to ensure the aperture ratio of the pixel electrode 10, can be disposed close to the edge of the pixel electrode 10. This arrangement can not only ensure the aperture ratio of the pixel electrode 10, but also make the pixel electrode 10 and the common electrode The capacitance between the traces 40 increases, reducing the capacitive coupling of the data lines 20 to the pixels.
  • the width of a first common electrode can be appropriately increased and the width of the corresponding second common electrode can be reduced, that is, the width of a first common electrode is greater than - the width of the second common electrode.
  • the second common electrode is arranged in parallel with the first common electrode.
  • each second common electrode is connected to the common electrode line, the other end of each second common electrode extends in a direction away from the common electrode line, and the other end of each second common electrode is connected to the gate line. There are gaps.
  • the first metal layer further includes at least a third common electrode and a gate line 50 .
  • the gate line 50 is disposed at an end of the data line 20 away from the common electrode trace 40 .
  • the third common electrode is connected to the common electrode trace 40 .
  • the lines 40 are connected, the third common electrode and the common electrode trace 40 are arranged on the same layer, and the third common electrode is arranged in a second direction opposite to the first direction, so that the width of the gate line 50 is smaller than the common electrode trace 40 width.
  • the pixel is more difficult to be affected by the voltage of the data line 20, thereby reducing the capacitance of the data line 20 to the pixel. coupling, reducing the risk of crosstalk.
  • the first direction is the direction in which the common electrode trace 40 faces the gate line 50
  • the second direction is the direction in which the gate line 50 faces the common electrode trace 40 .
  • the gate line 50 , the common electrode line 40 and the first common electrode 410 are formed in the same process.
  • the first common electrode 410 can be provided below the data line 20 , or the first common electrode 410 can be provided below the pixel electrode 10 , or the first common electrode 410 can be provided on the same layer as the common electrode trace 40
  • the specific selection of the common electrode 410 is based on the actual situation, and is not specifically limited here.
  • first common electrode 410 , the second common electrode and the third common electrode all belong to the same layer of metal as the common electrode wiring 40 , and the first common electrode 410 , the second common electrode and the third common electrode All are connected to the common electrode trace 40 . Therefore, when manufacturing the first common electrode 410 , the second common electrode or the third common electrode, they are all manufactured in the same process as the common electrode wiring 40 .
  • the material of the common electrode trace 40, the first common electrode 410, the second common electrode and the third common electrode is aluminum, molybdenum chromium or one of molybdenum, aluminum, molybdenum or sequentially stacked molybdenum, aluminum and molybdenum.
  • the material of the common electrode trace 40 , the material of the first common electrode 410 , the material of the second common electrode and the material of the third common electrode are set to be the same.
  • the material of the common electrode trace 40 , the material of the first common electrode 410 , the material of the second common electrode and the material of the third common electrode may also be different. It can be understood that the embodiments of the present application do not impose specific restrictions on this, and it can be set based on specific circumstances and actual conditions.
  • the first common electrode 410 can also be disposed elsewhere on the same layer as the common electrode trace 40. It only needs to be satisfied that the first common electrode 410 and the common electrode trace 40 are arranged on the same layer. And the first common electrode 410 only needs to be connected to the common electrode wiring 40, and the specific setting is based on the actual situation, and there is no specific limitation here.
  • the display panel 100 further includes a second metal layer 90 , and the second metal layer 90 forms the above-mentioned data line 20 .
  • FIG. 3 is a second structural schematic diagram of a display panel provided by an embodiment of the present application.
  • the display panel 100 further includes an indium tin oxide (ITO) layer.
  • the ITO layer includes a fifth common electrode 70 disposed above the common electrode trace 40 and between the fifth common electrode 70 and the common electrode trace 40 The layer is provided with a via hole 710, and the fifth common electrode 70 is electrically connected to the common electrode trace 40 through the wire in the via hole 710.
  • the display panel 100 also includes a gate line 50 and at least one thin film transistor 60.
  • the gate electrode of the thin film transistor 60 is connected to the gate line 50
  • the source electrode of the thin film transistor 60 is connected to a data line 20
  • the drain electrode of the thin film transistor 60 is connected to the data line 20.
  • the electrode is connected to a pixel electrode 10 .
  • a gate electrode of a thin film transistor 60 is formed by the first metal layer 30
  • a source electrode of a thin film transistor 60 and a drain electrode of the thin film transistor 60 are formed by the second metal layer 90 .
  • the display panel 100 further includes a gate insulation layer 80 disposed between the first metal layer 30 and the second metal layer 90 .
  • the display panel 100 When making the display panel 100, first make the first metal layer 30 and form the common electrode trace 40, then make the gate insulating layer 80 on the first metal layer 30, and then make the second metal layer on the gate insulating layer 80. layer 90 to form a plurality of data lines 20 . Then, the pixel electrode 10 is formed, and a flat layer is formed to form the fifth common electrode 70 .
  • the display panel 100 also includes a passivation layer 110 , which is disposed on the side of the pixel electrode 10 away from the gate insulating layer 80 .
  • the passivation layer 110 is made of silicon nitride, silicon oxide, or a combination of both.
  • the display panel 100 further includes an insulating overcoating (OC) layer 120 .
  • the insulating overcoating layer 120 is disposed on a side of the fifth common electrode 70 away from the pixel electrode 10 .
  • the material of the insulating overcoating layer 120 may be a gel coat resin.
  • the display panel 100 further includes a color filter 130 , which is disposed on a side of the insulating cover layer 120 away from the fifth common electrode 70 .
  • the display panel 100 further includes a substrate layer 140 , which is disposed on a side of the color filter 130 away from the insulating cover layer 120 .
  • the substrate layer 140 may include a glass substrate layer or a flexible substrate layer.
  • the display panel 100 also includes a support column 150 .
  • the display panel 100 also includes a light-shielding layer 160, and the material of the light-shielding layer 160 may be black ink.
  • FIG. 4 is a schematic structural diagram of the first metal layer in the display panel shown in FIG. 1 .
  • the first metal layer 30 includes a first portion 310 and a second portion 320 that are spaced apart.
  • the second portion 320 includes a plurality of first branches 321 arranged in a first direction.
  • the plurality of first branches 321 are arranged adjacent to each other.
  • the data line 20 is provided on the first branch 321.
  • the first part 310 is used to form the gate line 50
  • the second part 320 is used to form the common electrode trace 40 and the first common electrode 410 , wherein the first branch 321 forms the first common electrode 410 .
  • Each first branch 321 includes a first sub-branch 3211 and a second sub-branch 3212.
  • the first sub-branch 3211 and the second sub-branch 3212 are arranged to be bent relative to each other, so that between the common electrode trace 40 and the gate In the direction of the pole line 50, each first common electrode 410 includes a first part and a second part. There is an included angle greater than zero degrees between the first part and the second part. That is, the first part and the second part are bent relative to each other.
  • the bend setting can improve the viewing angle.
  • At least one first common electrode 410 is provided below the data line 20 .
  • the first common electrode 410 is arranged on the same layer as the common electrode trace 40 and is connected to the common electrode trace 40 , so that the pixel electrode 10 and the common electrode
  • the increase in capacitance between the traces 40 can increase the storage capacitance of the pixel, while the capacitance between the pixel electrode 10 and the data line 20 remains unchanged, thus causing the capacitance of the data line 20 to the pixel electrode 10 to be in the total pixel capacitance.
  • the ratio of pixels is reduced, so the pixels are more difficult to be affected by the voltage of the data line 20 , thereby reducing the capacitive coupling of the data line 20 to the pixels and reducing the risk of crosstalk.
  • a second common electrode can also be provided below the pixel electrode 10 or a third common electrode can be provided on the same layer as the common electrode trace 40 , further increasing the space between the pixel electrode 10 and the common electrode trace.
  • the capacitance between the lines 40 and thus the capacitance of the data line 20 to the pixel electrode 10 is reduced in the overall pixel ratio, thereby reducing the capacitive coupling of the data line 20 to the pixel and reducing the risk of crosstalk.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

一种显示面板（100），显示面板（100）包括：多个像素电极（10）；多条数据线（20），每一条数据线（20）与一个像素电极（10）连接；第一金属层（30）包括公共电极走线（40）和至少一第一公共电极（410），公共电极走线（40）与像素电极（10）至少部分重叠，第一公共电极（410）设置在数据线（20）的下方，且与公共电极走线（40）连接。

Description

显示面板 技术领域
本申请涉及显示领域，特别涉及一种显示面板。
 背景技术
边缘场开关（Fringe Field Switching, FFS）型液晶显示面板具有高穿透、广视角等优点，已被广泛应用于中小尺寸显示器，尤其以手机面板为主。所谓的FFS型液晶显示面板是利用边界电场使液晶盒(Cell)内的液晶(LC)分子在平行于基板的平面内旋转，产生光程差，在上下偏光片的作用下，达到显示效果。
 技术问题
然而，在现有的像素设计中，数据线与像素之间存在电容耦合，形成了串扰风险，从而影响了画面的显示效果。
 技术解决方案
本申请实施例提供一种显示面板，可以改善现有的显示面板存在串扰风险的问题。
本申请实施例提供一种显示面板，所述显示面板包括：
多个像素电极；
多条数据线，每一条所述数据线与一个所述像素电极连接；
第一金属层，包括公共电极走线和第一公共电极，所述公共电极走线与所述像素电极至少部分重叠，所述第一公共电极设置在所述数据线的下方，且与所述公共电极走线连接。
 有益效果
本申请的有益效果在于：本申请提供一种显示面板，该显示面板包括多个像素电极、多条数据线、第一金属层，每一条数据线与每一个像素电极连接，第一金属层包括公共电极走线和至少一第一公共电极，公共电极走线与像素电极至少部分耦合，第一公共电极设置在数据线的下方，且与公共电极走线连接。通过在数据线的下方设置第一公共电极，使得像素电极和公共电极走线之间的电容增大，可以使得像素的存储电容变大，而像素电极与数据线之间的电容不变，进而使得数据线对像素电极的电容在显示面板的总电容中的比例就减小了，因此，像素就更难被数据线的电压影响，以此减小了数据线对像素的电容耦合，减小了串扰风险。
 附图说明
图1为本申请实施例提供的显示面板的第一种结构示意图。
图2为本申请实施例提供的像素电极的部分电路结构示意图。
图3为本申请实施例提供的显示面板的第二种结构示意图。
图4为图1所示的显示面板中第一金属层的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的组件或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
边缘场开关（Fringe Field Switching, FFS）型液晶显示有着广泛的应用。在现有的像素设计中，一般采用像素翻转（Flip Pixel）的像素架构，在高刷新率高分辨率的应用中，子像素（RGB Stripe）架构可以做到更高的充电率，但是RGB Stripe架构的垂直显示中，由于数据线与像素之间存在电容耦合，导致串扰风险较大。
因此，为了解决上述问题，本申请提出了一种显示面板。下面结合附图和实施方式对本申请作进一步说明。
请参阅图1和图2，图1为本申请实施例提供的显示面板的第一种结构示意图。图2为本申请实施例提供的像素电极的部分电路结构示意图。本申请实施例提供一种显示面板100，该显示面板100包括多个像素电极10、多条数据线20、第一金属层，其中，每一条数据线20与每一个像素电极10连接，用于给相应的像素电极10传送数据信号。第一金属层包括公共电极走线40和至少一第一公共电极410，公共电极走线40与像素电极10至少部分重叠，第一公共电极410设置在数据线20的下方，且与公共电极走线40连接。通过在数据线20的下方设置第一公共电极410，使得像素电极10和公共电极走线40之间的电容增大，可以使得像素的存储电容变大，而像素电极10与数据线20之间的电容不变，进而使得数据线20对像素电极10的电容在整体的像素电容中比例就减小了，因此，像素就更难被数据线20的电压影响，以此减小了数据线20对像素的电容耦合，减小了串扰风险。
其中，第一公共电极410的正投影在数据线20的正投影内。示例性的，一第一公共电极410的宽度可以小于或等于一数据线20的宽度，在其他一些实施例中，为了更好的减小串扰风险，一第一公共电极410的宽度也会大于一数据线20的宽度，一第一公共电极410的宽度具体的需要根据实际情况进行设置，在此不作具体的限制。
在一些实施例中，第一公共电极410的数量小于数据线20的数量，在其他一些实施例中，为了更好的减小数据线20对显示面板100的串扰，可以在每条数据线20下方均设置第一公共电极410，即设置第一公共电极410的数目和数据线20的数目相等。
其中，第一金属层还包括栅极线50，栅极线50的宽度小于公共电极走线40的宽度。每一第一公共电极的一端与公共电极线连接，每一第一公共电极的另一端向靠近栅极线的方向延伸，且每一公共电极和与栅极线之间存在间隙。
请继续图2，在一些实施例中，在保证像素开口率的情况下，第一金属层还包括至少一第二公共电极，第二公共电极设置在像素电极10的下方，第二公共电极与公共电极走线40同层设置，且与公共电极走线40连接。通过在像素电极10的下方设置第二公共电极，使得像素电极10和公共电极走线40之间的电容增大，可以使得像素的存储电容变大，而像素电极10与数据线20之间的电容不变，进而使得数据线20对像素电极10的电容在总像素电容中的比例减小了，因此，像素就更难被数据线20的电压影响，以此减小了数据线20对像素的电容耦合，减小了串扰风险。
在一些实施例中，为了保证像素电极10的开口率，可以将第二公共电极靠近像素电极10的边缘设置，这样设置既可以保证像素电极10的开口率，还可以使得像素电极10和公共电极走线40之间的电容增大，减小数据线20对像素的电容耦合。
在其他一些实施例中，为了更好的保证像素电极10的开口率，可以适当增加一第一公共电极的宽度，减小对应的第二公共电极的宽度，即一第一公共电极的宽度大于一第二公共电极的宽度。
可以理解的是，第二公共电极与第一公共电极平行设置。
其中，每一第二公共电极的一端与公共电极线连接，每一第二公共电极的另一端向远离公共电极线的方向延伸，且每一第二公共电极的另一端与栅极线之间存在间隙。
在一些实施例中，第一金属层还包括至少一第三公共电极和栅极线50，栅极线50设置在数据线20远离公共电极走线40的一端，第三公共电极与公共电极走线40连接，第三公共电极和公共电极走线40同层设置，且第三公共电极设置在与第一方向相反的第二方向上，以此使得栅极线50的宽度小于公共电极走线40的宽度。通过增大公共电极走线40的面积，使得像素电极10和公共电极走线40之间的电容增大，可以使得像素的存储电容变大，而像素电极10与数据线20之间的电容不变，进而使得数据线20对像素电极10的电容在总像素电容中的比例减小了，因此，像素就更难被数据线20的电压影响，以此减小了数据线20对像素的电容耦合，减小了串扰风险。
其中，第一方向为公共电极走线40朝向栅极线50的方向，第二方向为栅极线50朝向公共电极走线40的方向。
需要说明的是，为了节约工序，栅极线50、公共电极走线40和第一公共电极410同一制程形成。
可以理解的是，减小了串扰风险，可以在数据线20下方设置第一公共电极410、或者在像素电极10下方设置第一公共电极410，又或者在公共电极走线40同层设置第一公共电极410，具体的选择根据实际情况进行选择，在此不作具体的限制。
需要说明的是，由于第一公共电极410、第二公共电极和第三公共电极均与公共电极走线40属于同层金属设置，且第一公共电极410、第二公共电极和第三公共电极均与公共电极走线40连接。因此，在制作第一公共电极410、第二公共电极或第三公共电极时，均与公共电极走线40同一工序制成。
公共电极走线40、第一公共电极410、第二公共电极和第三公共电极的材质为铝、钼铬或钼、铝、钼或依次层叠的钼、铝和钼中的一种。在一些实施例中，为了节约材料资源，设置公共电极走线40的材质、第一公共电极410的材质、第二公共电极的材质和第三公共电极的材质相同。在其他一些实施例中，也可以设置公共电极走线40的材质、第一公共电极410的材质、第二公共电极的材质和第三公共电极的材质不全相同。可以理解的是，本申请实施例对此不作具体限制，具体的根及实际情况进行设置即可。
从图2可知，为了进一步的减小串扰，第一公共电极410还可以设置在于公共电极走线40同层的其他地方，只需要满足第一公共电极410与公共电极走线40同层设置，且第一公共电极410与公共电极走线40连接即可，具体的根据实际情况进行设置，在此不作具体的限制。
显示面板100还包括第二金属层90，第二金属层90形成上述数据线20。
请继续参阅图3，图3为本申请实施例提供的显示面板的第二种结构示意图。显示面板100还包括氧化铟锡（ITO）层，ITO层包括第五公共电极70，第五公共电极70设置在公共电极走线40的上方，第五公共电极70和公共电极走线40之间的层设置有过孔710，第五公共电极70通过过孔710内的导线与公共电极走线40电连接。
显示面板100还包括栅极线50和至少一薄膜晶体管60，一薄膜晶体管60的栅极与栅极线50连接，一薄膜晶体管60的源极与一数据线20连接，一薄膜晶体管60的漏极与一像素电极10连接。
其中，一薄膜晶体管60的栅极由第一金属层30形成，一薄膜晶体管60的源极和一薄膜晶体管60的漏极由第二道金属90形成。
显示面板100还包括栅极绝缘层80，栅极绝缘层80设置在第一金属层30和第二金属层90之间。
在制作该显示面板100时，先制作第一金属层30，形成公共电极走线40，然后在第一金属层30上制作栅极绝缘层80，然后在栅极绝缘层80上制作第二金属层90，形成多条数据线20。然后再制作像素电极10，再制作平坦层，形成第五公共电极70。
显示面板100还包括钝化层110，钝化层110设置在像素电极10远离栅极绝缘层80的一侧，钝化层110的材料均为氮化硅、氧化硅或二者的组合。
显示面板100还包括绝缘覆盖(OverCoating，OC)层120，绝缘覆盖层120设置在第五公共电极70远离像素电极10的一侧，绝缘覆盖层120的材料可以为胶衣树脂。
显示面板100还包括彩膜130，彩膜130设置在绝缘覆盖层120远离第五公共电极70的一侧。
显示面板100还包括基板层140，基板层140设置在彩膜130远离绝缘覆盖层120的一侧，基板层140可以包括玻璃基板层或者柔性衬底层。
显示面板100还包括支撑柱150。
显示面板100还包括遮光层160，遮光层160的材料可以为黑色油墨。
请继续参阅图4，图4为图1所示的显示面板中第一金属层的结构示意图。第一金属层30包括间隔设置的第一部310和第二部320，第二部320包括在第一方向上设置的多个第一支干321，多个第一支干321设置于相邻的两组像素电极10的间隔区域，第一支干321上设置数据线20。第一部310用于形成栅极线50，第二部320用于形成公共电极走线40和第一公共电极410，其中，第一支干321形成第一公共电极410。
每一第一支干321包括第一子支干3211和第二子支干3212，第一子支干3211和第二子支干3212相对弯折设置，以使得在公共电极走线40至栅极线50的方向上，每一第一公共电极410包括第一部分和第二部分，第一部分和第二部分之间存在大于零度的夹角，即第一部分和第二部分相对弯折设置，通过弯折设置可以提高视角。
本申请实施例通过在数据线20下方设置至少一个第一公共电极410，第一公共电极410与公共电极走线40同层设置，且与公共电极走线40连接，使得像素电极10和公共电极走线40之间的电容增大，可以使得像素的存储电容变大，而像素电极10与数据线20之间的电容不变，进而使得数据线20对像素电极10的电容在总像素电容中的比例减小了，因此，像素就更难被数据线20的电压影响，以此减小了数据线20对像素的电容耦合，减小了串扰风险。并且在保证像素开口率的情况下，还可以在像素电极10的下方设置第二公共电极或在公共电极走线40同层设置第三公共电极，进一步的增大了像素电极10和公共电极走线40之间的电容，进而使得数据线20对像素电极10的电容在整体的像素比例中就减小了，以此减小了数据线20对像素的电容耦合，减小了串扰风险。
以上对本申请实施例提供的显示面板进行了详细介绍。本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括：
    多个像素电极；
    多条数据线，每一条所述数据线与一个所述像素电极连接；
    第一金属层，包括公共电极走线和至少一第一公共电极，所述公共电极走线与所述像素电极至少部分重叠，所述第一公共电极设置在所述数据线的下方，且与所述公共电极走线连接。
  2. 根据权利要求1所述的显示面板，其中，每一所述第一公共电极包括第一部分和第二部分，所述第一部分和所述第二部分之间存在夹角。
  3. 根据权利要求1所述的显示面板，其中，所述第一公共电极的正投影在所述数据线的正投影内。
  4. 根据权利要求1所述的显示面板，其中，所述第一金属层还包括：
    栅极线，所述栅极线的宽度小于所述公共电极走线的宽度。
  5. 根据权利要求4所述的显示面板，其中，每一所述第一公共电极的一端与所述公共电极走线连接，每一所述第一公共电极的另一端向靠近所述栅极线的方向延伸，且与所述栅极线之间存在间隙。
  6. 根据权利要求5所述的显示面板，其中，所述第一金属层还包括：
    至少一第二公共电极，所述第二公共电极设置在所述像素电极的下方，所述第二公共电极与所述公共电极走线连接。
  7. 根据权利要求6所述的显示面板，其中，所述第二公共电极靠近所述像素电极的边缘设置。
  8. 根据权利要求6所述的显示面板，其中，一所述第一公共电极的宽度大于一所述第二公共电极的宽度。
  9. 根据权利要求6所述的显示面板，其中，一所述第二公共电极的一端与所述公共电极走线连接，一所述第二公共电极的另一端向远离所述公共电极走线的方向延伸。
  10. 根据权利要求6所述的显示面板，其中，所述显示面板还包括至少一第三公共电极，所述第三公共电极设置在所述公共电极走线的上方，一所述第三公共电极与所述公共电极走线之间设置有过孔，一所述第三公共电极通过所述过孔内的导线与所述公共电极走线电连接。
  11. 根据权利要求10所述的显示面板，其中，所述公共电极走线的材质、所述第一公共电极的材质、第二公共电极的材质和第三公共电极的材质相同。
  12. 根据权利要求6所述的显示面板，其中，所述栅极线、所述第一公共电极和所述第二公共电极同一制程形成。
  13. 根据权利要求6所述的显示面板，其中，所述第二公共电极与所述第一公共电极平行设置。
  14. 根据权利要求6所述的显示面板，其中，所述第二公共电极的数量与所述数据线的数量相等。
  15. 根据权利要求6所述的显示面板，其中，一所述第二公共电极的宽度小于或等于一所述数据线的宽度。
  16. 根据权利要求6所述的显示面板，其中，所述显示面板还包括至少一薄膜晶体管，一所述薄膜晶体管的栅极与所述栅极线连接，一所述薄膜晶体管的源极与一所述数据线连接，一所述薄膜晶体管的漏极与一所述像素电极连接。
  17. 根据权利要求1所述的显示面板，其中，所述第一金属层包括间隔设置的第一部和第二部，所述第二部包括在第一方向上设置的多个第一支干，多个所述第一支干设置于相邻的两组像素电极的间隔区域，每一所述第一支干上设置有一所述数据线。
  18. 根据权利要求1所述的显示面板，其中，所述第一公共电极的数量小于或等于所述数据线的数量。
  19. 根据权利要求1所述的显示面板，其中，所述第一公共电极的材质为铝、钼、铬或依次层叠的钼、铝和钼中的一种。
  20. 根据权利要求1所述的显示面板，其中，所述显示面板还包括第二金属层，所述第二金属层用于形成所述数据线。
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