WO2019205467A1 - Tft阵列基板及显示装置 - Google Patents

Tft阵列基板及显示装置 Download PDF

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Publication number
WO2019205467A1
WO2019205467A1 PCT/CN2018/106330 CN2018106330W WO2019205467A1 WO 2019205467 A1 WO2019205467 A1 WO 2019205467A1 CN 2018106330 W CN2018106330 W CN 2018106330W WO 2019205467 A1 WO2019205467 A1 WO 2019205467A1
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Prior art keywords
fan
lines
line
metal layer
out line
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PCT/CN2018/106330
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English (en)
French (fr)
Inventor
崔珠峰
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武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/319,351 priority Critical patent/US11011553B2/en
Publication of WO2019205467A1 publication Critical patent/WO2019205467A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT array substrate and a display device.
  • a flat panel display device such as a liquid crystal display (LCD) has gradually replaced a cathode ray tube (CRT) display device.
  • the liquid crystal display device has many advantages such as thin body, power saving, no radiation, and the like, and has been widely used.
  • the liquid crystal display panel comprises a color filter (CF) substrate, a thin film transistor (TFT) array substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor array substrate, and a sealant.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • the TFT array substrate includes a substrate 100 and a data line metal layer 200 disposed above the substrate 100.
  • the TFT array substrate has an effective setting in sequence.
  • the display area (Active Area) 110 and the fanout area 120, the data line metal layer 200 includes a plurality of data lines 210 arranged in parallel and spaced apart in the effective display area 110 and disposed in the fan-out area 120, respectively.
  • the plurality of data lines 210 correspond to a plurality of fan-out lines 220 connected.
  • the fanout line 220 is used to connect the corresponding data line 210 with an external integrated chip (IC) to transmit a data signal to the data line 210.
  • IC integrated chip
  • each fan-out line 220 includes a first straight portion 221 , a diagonal portion 222 , and a second straight portion 223 that are sequentially connected, and one end of the first straight portion 221 of each fan-out line 220 corresponds to
  • the data lines 210 are connected, and the first straight portion 221 and the corresponding data line 210 extend in the same direction, and the second straight portions 223 of the plurality of fan-out lines 220 are parallel and spaced apart, and are parallel to the plurality of data lines 210, and multiple The distance between the outermost two data lines 210 in the data line 210 is greater than the distance between the outermost two second straight portions 223 of the second straight portions 223 of the plurality of fan-out lines 220, and the oblique lines of the plurality of fan-out lines 220.
  • a common practice in the prior art is to design a plurality of corners 2211 on the first straight portion 221 of the fan-out line 220 to increase the overall length and internal resistance of the plurality of fan-out lines 220, thereby reducing The difference in internal resistance between each fan-out line 220 ensures that there is no timing difference in the input of the data signal.
  • an exposure abnormality easily occurs at the corner 2211, resulting in a short circuit phenomenon at the corner 2211, and the internal resistance of the fan-out line 220 is reduced. It is difficult to effectively ensure a stable input of the data signal.
  • Another object of the present invention is to provide a display device capable of effectively reducing the internal resistance difference between fan-out lines corresponding to different data lines and realizing stable input of data signals.
  • the present invention firstly provides a TFT array substrate comprising a substrate, a first metal layer disposed on the substrate, and a second metal layer disposed above the first metal layer and insulated from the first metal layer;
  • the second metal layer includes a plurality of parallel and spaced data lines and a plurality of first fan-out lines respectively corresponding to the plurality of data lines, wherein the first fan-out line is spaced apart from the corresponding data line; the first metal layer includes a plurality of second fan outgoing lines respectively corresponding to the plurality of data lines;
  • the TFT array substrate has an effective display area and a fan-out area which are sequentially disposed, and a plurality of data lines are respectively located in the effective display area and have ends extending to the fan-out area, and the plurality of first fan-out lines and the second fan-out lines are located at a fan-out area; the projection of the data line extending to the end of the fan-out area in a vertical direction overlaps with a portion of the corresponding second fan-out line and is electrically connected to the second fan-out line via a corresponding first via hole The projection of the portion of the first fan-out line in the vertical direction overlaps with the portion of the second fan-out line corresponding to the corresponding data line and is electrically connected to the second fan-out line via a corresponding second via hole;
  • the surface resistivity of the first metal layer is greater than the surface resistivity of the second metal layer.
  • the projection of the data line extending to the end of the fan-out area in the vertical direction overlaps with the end of the corresponding second fan-out line near the effective display area and is effectively displayed by the corresponding first via hole and the second fan-out line.
  • the end of the area is electrically connected; the projection of the end of the first fan-out line near the effective display area in the vertical direction overlaps with the end of the second fan-out line corresponding to the corresponding data line away from the effective display area and corresponds to
  • the second via is electrically connected to the end of the second fan-out line away from the effective display area;
  • the second fan-out line has the same extension direction as the corresponding data line
  • the internal resistance of the plurality of second fan outlets is the same.
  • the first metal layer further includes a plurality of third fan-out lines respectively corresponding to the plurality of data lines; the plurality of third fan-out lines are all located in the fan-out area; and the second fan-out line and the third fan-out line corresponding to the same data line
  • the projection of the portion of the first fan-out line in the vertical direction overlaps with the portion of the third fan-out line corresponding to the corresponding data line and is electrically connected to the third fan-out line via a corresponding third via.
  • the three fan-out lines are electrically connected to the end of the effective display area; the third fan-out line extends away from the end of the effective display area to the edge of the substrate.
  • a plurality of third fan outgoing lines are parallel to the plurality of data lines
  • the internal resistance of the plurality of third fan outlets is the same.
  • the distance between the outermost two data lines of the plurality of data lines is greater than the distance between the outermost two third fan out lines of the plurality of third fan lines.
  • the first metal layer has a surface resistivity of 0.4 ⁇ / ⁇ to 0.5 ⁇ / ⁇ ; and the second metal layer has a surface resistivity of 0.05 ⁇ / ⁇ to 0.15 ⁇ / ⁇ .
  • the first metal layer further includes a plurality of parallel and spaced scan lines disposed in the effective display area;
  • the plurality of scan lines are perpendicular to the plurality of data lines.
  • the TFT array substrate further includes an interlayer insulating layer disposed between the first metal layer and the second metal layer, wherein the first via, the second via, and the third via penetrate through the interlayer Insulation.
  • the present invention also provides a display device comprising the above TFT array substrate.
  • the invention provides a TFT array substrate, wherein a plurality of second fan-out lines respectively corresponding to the plurality of data lines in the fan-out area are disposed on the first metal layer, and the fan-out areas are respectively separated.
  • a first fan-out line corresponding to the plurality of data lines is disposed on the second metal layer, and a connection between the data line and the second fan-out line and between the second fan-out line and the first fan-out line is through a via hole, the first metal layer
  • the surface resistivity is greater than the surface resistivity of the second metal layer, thereby increasing the internal resistance of the entire fan-out line corresponding to each data line, and reducing the internal resistance difference between the fan-out lines corresponding to different data lines, thereby utilizing the fan
  • the outgoing line provides data signals to multiple data lines, the data signals received by the data lines do not have timing differences, which effectively improves the quality of the product, and the manufacturing process is highly reliable, and there is no risk of a fan-out line short circuit.
  • 1 is a schematic structural view of a conventional TFT array substrate
  • FIG. 2 is a schematic view showing a corner formed on a first straight portion of a conventional fan-out line
  • FIG. 3 is a schematic structural view of a TFT array substrate of the present invention.
  • Figure 4 is a cross-sectional view taken along line A-A' of Figure 3;
  • Figure 5 is a cross-sectional view taken along line B-B' of Figure 3.
  • the TFT array substrate of the present invention comprises a substrate 10, a first metal layer 20 disposed on the substrate 10, an interlayer insulating layer 40 disposed on the first metal layer 20, and
  • the second metal layer 30 on the interlayer insulating layer 40 over the metal layer 20 is insulated from the second metal layer 30 by the presence of the interlayer insulating layer 40.
  • the second metal layer 30 includes a plurality of parallel and spaced data lines 31 and a plurality of first fan-out lines 32 respectively corresponding to the plurality of data lines 31 , and the first fan-out lines 32 and corresponding data thereof.
  • Line 31 is spaced.
  • the first metal layer 20 includes a plurality of second fan-out lines 21 corresponding to the plurality of data lines 31 and a plurality of third fan-out lines 22 respectively corresponding to the plurality of data lines 31.
  • the second fan-out line 21 and the third fan-out line 22 corresponding to the same data line 31 are spaced apart.
  • the TFT array substrate has an effective display area 101 and a fan-out area 102 which are sequentially disposed, and a plurality of data lines 31 are located in the effective display area 101 and have ends extending to the fan-out area 102, and a plurality of first fan-out lines 32, The second fanout line 21 and the third fanout line 22 are both located in the fanout zone 102.
  • the data line 31 extends to a portion of the fan-out region 102 in a vertical direction and partially overlaps the corresponding second fan-out line 21 and passes through a corresponding inter-layer insulating layer.
  • the first via 41 of the 40 is electrically connected to the second fan-out line 21.
  • the projection of the portion of the first fan-out line 32 in the vertical direction overlaps with the portion of the second fan-out line 21 corresponding to the corresponding data line 31 and passes through a corresponding second via 42 of the interlayer insulating layer 40.
  • the second fan-out line 21 is electrically connected.
  • the plurality of second fan-out lines 21 are equal in internal resistance of a portion between the corresponding first via hole 41 and the corresponding second via hole 42.
  • the projection of the portion of the first fan-out line 32 in the vertical direction overlaps with the portion of the third fan-out line 22 corresponding to the corresponding data line 31 and is insulated by a corresponding inter-layer.
  • the third via 43 of the layer 40 is electrically connected to the third fan-out line 22 .
  • the surface resistivity of the first metal layer 20 is greater than the surface resistivity of the second metal layer 30.
  • the via 42 is electrically connected to the end of the second fan-out line 21 away from the effective display area 101.
  • the second fan-out line 21 has the same extension direction as the corresponding data line 31.
  • the projection of the first fan-out line 32 away from the end of the effective display area 101 in the vertical direction and the third fan-out line 22 corresponding to the corresponding data line 31 are close to the end of the effective display area 101.
  • the portions overlap and are electrically connected to the end of the third fan-out line 22 adjacent to the effective display area 101 via the corresponding third via 43.
  • the third fan-out line 22 extends away from the end of the effective display area 101 to the edge of the substrate 10.
  • the internal resistances of the plurality of second fan-out lines 21 are the same, and the internal resistances of the plurality of third fan-out lines 22 are the same.
  • the second fan-out line 21 has the same extension direction as the corresponding data line 31.
  • a plurality of third fan outgoing lines 22 are parallel to the plurality of data lines 31. The distance between the outermost two data lines 31 of the plurality of data lines 31 is greater than the distance between the outermost two third fan-out lines 22 of the plurality of third fan-out lines 22, corresponding to the different data lines 31. The length of one outgoing line 31 is different.
  • the first metal layer 20 has a surface resistivity of 0.4 ⁇ / ⁇ to 0.5 ⁇ / ⁇ , preferably 0.45 ⁇ / ⁇ .
  • the surface resistivity of the second metal layer 30 is 0.05 ⁇ / ⁇ - 0.15 ⁇ / ⁇ , preferably 0.1 ⁇ / ⁇ .
  • the first metal layer 20 further includes a plurality of parallel and spaced scan lines 23 disposed in the effective display area 101.
  • the plurality of scan lines 23 are perpendicular to the plurality of data lines 31.
  • a plurality of second fan-out lines 21 corresponding to the plurality of data lines 31 in the fan-out area 102 are disposed on the first metal layer 20 to be in the fan-out area 102.
  • the first fan-out line 32 corresponding to the plurality of data lines 31 is disposed on the second metal layer 30, and the third fan-out line 22 corresponding to the plurality of data lines 31 in the fan-out area 102 is disposed on the first metal layer. 20 on.
  • the materials of the metal layer 20 and the second metal layer 30 are selected such that the surface resistivity of the first metal layer 20 is greater than the surface resistivity of the second metal layer 30, thereby comparing the fan corresponding to the same data line in the prior art.
  • the entire outgoing line is in the same layer as the data line. In the present invention, the sum of the internal resistances of the first fan-out line 32, the second fan-out line 21, and the third fan-out line 22 corresponding to the same data line 31 is greatly increased, and the surface resistivity is higher.
  • the internal resistance of the low first fan-out line 32 is smaller in the sum of the internal resistances of the first fan-out line 32, the second fan-out line 21, and the third fan-out line 22, so that the internal resistance of the first fan-out line 32 changes.
  • the influence of the sum of the internal resistances of the first fan-out line 32, the second fan-out line 21, and the third fan-out line 22 is small, so that even if the size of the TFT array substrate is increased, the first fan-out line 32 corresponding to the different data lines 31 is The length difference is large, corresponding to the first fan-out line 32 and the second of the different data lines 31.
  • the difference between the sum of the internal resistances of the outgoing line 21 and the third outgoing line 22 is still small, so that when the data signal is supplied to the plurality of data lines 31 by the fan-out line, the data lines 31 receive the data signals without timing.
  • the difference is effective to improve the quality of the product, and the corner is formed on the first straight portion of the fan-out line to increase the length of the fan-out line.
  • the manufacturing process of the present invention has high reliability and does not cause short-circuit of the fan-out line. risk.
  • the present invention further provides a display device including the above-described TFT array substrate, and the structure of the TFT array substrate will not be repeatedly described herein.
  • the display device of the present invention is a liquid crystal display device or other prior art display device that requires a TFT array substrate as a driving structure.
  • the above-mentioned TFT array substrate is used, and the same fan-out line corresponding to the same data line in the prior art is in the same layer as the data line, and the same data line in the present invention.
  • the sum of the internal resistances of the corresponding first fan-out line 32, the second fan-out line 21, and the third fan-out line 22 is greatly increased, and the internal resistance of the first fan-out line 32 having a lower surface resistivity is at the first fan-out line 32,
  • the ratio of the sum of the internal resistances of the second fan-out line 21 and the third fan-out line 22 is small, so that the internal resistance of the first fan-out line 32 changes to the first fan-out line 32, the second fan-out line 21, and the third fan-out line 22
  • the influence of the sum of the internal resistances is small, so even if the size of the display substrate is increased, the length difference between the first fan-out lines 32 corresponding to the different data lines 31 is large, and the first fan-out lines 32 corresponding to the different data lines 31,
  • the difference between the sum of the internal resistances of the two fan-out lines 21 and the third fan-out line 22 is still small, so that when the data signals are supplied to the plurality of data lines 31 by the fan-out
  • the corner is formed on the first straight portion of the fan-out line to increase the length of the fan-out line.
  • the manufacturing process of the present invention has high reliability and does not cause the risk of short-circuiting of the fan-out line.
  • the TFT array substrate of the present invention sets a plurality of second fan-out lines respectively corresponding to the plurality of data lines in the fan-out area on the first metal layer, and separates the plurality of data in the fan-out area.
  • a first fan-out line corresponding to the line is disposed on the second metal layer, and a connection between the data line and the second fan-out line and between the second fan-out line and the first fan-out line is through a via hole, and a surface resistivity of the first metal layer is greater than
  • the surface resistivity of the second metal layer increases the internal resistance of the entire fan-out line corresponding to each data line, and reduces the internal resistance difference between the fan-out lines corresponding to different data lines, thereby using the fan-out line to multiple strips
  • the data signal is provided on the data line, the data signals received by the data lines do not have timing differences, which effectively improves the quality of the product, and the manufacturing process is highly reliable, and there is no risk of a fan-out line short circuit.

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  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明提供一种TFT阵列基板及显示装置。该TFT阵列基板将扇出区内的分别与多条数据线对应的多条第二扇出线设置在第一金属层上，将扇出区内的分别与多条数据线对应的第一扇出线设置在第二金属层上，数据线与第二扇出线之间以及第二扇出线与第一扇出线之间通过过孔连接，第一金属层的表面电阻率大于第二金属层的表面电阻率，从而增大对应每一条数据线的扇出线整体的内阻，减少对应不同的数据线的扇出线之间的内阻差异性，从而在利用扇出线向多条数据线上提供数据信号时，各条数据线接收数据信号不会出现时序差异，有效提升产品的品质，且制作过程可靠性高，不会产生扇出线短路的风险。

Description

TFT阵列基板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板及显示装置。
背景技术
在显示技术领域，液晶显示装置(Liquid Crystal Display，LCD)等平板显示装置已经逐步取代阴极射线管(Cathode Ray Tube，CRT)显示装置。液晶显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括液晶显示面板及背光模组(backlight module)。通常液晶显示面板由彩膜(Color Filter，CF)基板、薄膜晶体管(Thin Film Transistor，TFT)阵列基板、夹于彩膜基板与薄膜晶体管阵列基板之间的液晶(Liquid Crystal，LC)及密封胶框(Sealant)组成。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
请参阅图1，为现有的一种TFT阵列基板的结构示意图，该TFT阵列基板包括衬底100及设于衬底100上方的数据线金属层200，所述TFT阵列基板具有依次设置的有效显示区(Active Area)110及扇出(fanout)区120，所述数据线金属层200包括于有效显示区110内平行且间隔设置的多条数据线210及设于扇出区120内分别与多条数据线210对应连接的多条扇出线220。扇出线220用于将对应的数据线210与外部的集成芯片(IC)进行连接从而向数据线210传输数据信号。如图1所示，每一扇出线220均包括依次连接的第一直线部221、斜线部222及第二直线部223，每一扇出线220的第一直线部221的一端与对应的数据线210连接，且第一直线部221与对应的数据线210延伸方向相同，多条扇出线220的第二直线部223平行且间隔设置，且与多条数据线210平行，多条数据线210中最外侧两条数据线210之间的距离大于多条扇出线220的第二直线部223中最外侧两个第二直线部223之间的距离，多条扇出线220的斜线部222之间的长度存在差异。随着显示技术不断发展，液晶显示装置的尺寸越来越大，相应地，对于如图1所示结构的TFT阵列基板，其多条扇出线220的斜线部222之间的长度差异也越来越大，导致各条扇出线220的内阻的差异越 来越大，进而在利用多条扇出线220向多条数据线210传输数据信号时，各条数据线210接收到数据信号存在时序差异，影响显示品质。为解决这一问题，请参阅图2，现有技术的通常做法是在扇出线220的第一直线部221设计多个拐角2211，以增大多条扇出线220整体的长度及内阻，减少各条扇出线220之间的内阻差异，保证数据信号的输入不出现时序差异。然而受制于现有的曝光制程的工艺，在制作图2所示的扇出线220时，容易在拐角2211处出现曝光异常，导致拐角2211处出现短路现象，反而减小了扇出线220的内阻，很难有效地保证数据信号的稳定输入。
发明内容
本发明的目的在于提供一种TFT阵列基板，能够有效降低对应不同数据线的扇出线之间的内阻差异性，实现数据信号的稳定输入。
本发明的另一目的在于提供一种显示装置，能够有效降低对应不同数据线的扇出线之间的内阻差异性，实现数据信号的稳定输入。
为实现上述目的，本发明首先提供一种TFT阵列基板，包括衬底、设于衬底上的第一金属层及设于第一金属层上方与第一金属层绝缘的第二金属层；
所述第二金属层包括多条平行且间隔的数据线及分别对应多条数据线的多条第一扇出线，所述第一扇出线与其对应的数据线间隔；所述第一金属层包括分别与多条数据线对应的多条第二扇出线；
所述TFT阵列基板具有依次设置的有效显示区及扇出区，多条数据线均位于有效显示区且具有延伸至扇出区的端部，多条第一扇出线及第二扇出线均位于扇出区；所述数据线延伸至扇出区的端部在竖直方向的投影与对应的第二扇出线的部分重叠并经一对应的第一过孔与该第二扇出线电性连接；所述第一扇出线的部分在竖直方向的投影与对应的数据线所对应的第二扇出线的部分重叠并经一对应的第二过孔与该第二扇出线电性连接；
所述第一金属层的表面电阻率大于第二金属层的表面电阻率。
所述数据线延伸至扇出区的端部在竖直方向的投影与对应的第二扇出线靠近有效显示区的端部重叠并经对应的第一过孔与该第二扇出线靠近有效显示区的端部电性连接；所述第一扇出线靠近有效显示区的端部在竖直方向的投影与对应的数据线所对应的第二扇出线远离有效显示区的端部重叠并经对应的第二过孔与该第二扇出线远离有效显示区的端部电性连接；
所述第二扇出线与对应的数据线的延伸方向相同；
多条第二扇出线的内阻相同。
所述第一金属层还包括分别与多条数据线对应的多条第三扇出线；多条第三扇出线均位于扇出区；对应同一数据线的第二扇出线及第三扇出线相间隔；所述第一扇出线的部分在竖直方向的投影与对应的数据线所对应的第三扇出线的部分重叠并经一对应的第三过孔与该第三扇出线电性连接。
所述第一扇出线远离有效显示区的端部在竖直方向的投影与对应的数据线所对应的第三扇出线靠近有效显示区的端部重叠并经对应的第三过孔与该第三扇出线靠近有效显示区的端部电性连接；所述第三扇出线远离有效显示区的端部延伸至衬底的边缘。
多条第三扇出线与多条数据线相平行；
多条第三扇出线的内阻相同。
多条数据线中最外侧的两条数据线之间的距离大于多条第三扇出线中最外侧的两条第三扇出线之间的距离。
所述第一金属层的表面电阻率为0.4Ω/□-0.5Ω/□；所述第二金属层的表面电阻率为0.05Ω/□-0.15Ω/□。
所述第一金属层还包括设置在有效显示区内的多条平行且间隔的扫描线；
所述多条扫描线与多条数据线垂直。
所述TFT阵列基板还包括设于所述第一金属层与第二金属层之间的层间绝缘层，所述第一过孔、第二过孔及第三过孔均贯穿所述层间绝缘层。
本发明还提供一种显示装置，包括上述TFT阵列基板。
本发明的有益效果：本发明提供的一种TFT阵列基板将扇出区内的分别与多条数据线对应的多条第二扇出线设置在第一金属层上，将扇出区内的分别与多条数据线对应的第一扇出线设置在第二金属层上，数据线与第二扇出线之间以及第二扇出线与第一扇出线之间通过过孔连接，第一金属层的表面电阻率大于第二金属层的表面电阻率，从而增大对应每一条数据线的扇出线整体的内阻，减少对应不同的数据线的扇出线之间的内阻差异性，从而在利用扇出线向多条数据线上提供数据信号时，各条数据线接收数据信号不会出现时序差异，有效提升产品的品质，且制作过程可靠性高，不会产生扇出线短路的风险。本发明提供的一种显示装置能够有效降低对应不同数据线的扇出线之间的内阻差异性，实现数据信号的稳定输入。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本 发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的一种TFT阵列基板的结构示意图；
图2为在现有的扇出线的第一直线部上制作拐角的示意图；
图3为本发明的TFT阵列基板的结构示意图；
图4为沿图3中的A-A’线的剖视示意图；
图5为沿图3中的B-B’线的剖视示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3至图5，本发明的TFT阵列基板包括衬底10、设于衬底10上的第一金属层20、设于第一金属层20上的层间绝缘层40及设于第一金属层20上方的层间绝缘层40上的第二金属层30，由于层间绝缘层40的存在，第一金属层20与第二金属层30绝缘。
请参阅图3，所述第二金属层30包括多条平行且间隔的数据线31及分别对应多条数据线31的多条第一扇出线32，所述第一扇出线32与其对应的数据线31间隔。所述第一金属层20包括分别与多条数据线31对应的多条第二扇出线21及分别与多条数据线31对应的多条第三扇出线22。对应同一数据线31的第二扇出线21及第三扇出线22相间隔。所述TFT阵列基板具有依次设置的有效显示区101及扇出区102，多条数据线31均位于有效显示区101且具有延伸至扇出区102的端部，多条第一扇出线32、第二扇出线21及第三扇出线22均位于扇出区102。
请参阅图3并结合图4，所述数据线31延伸至扇出区102的端部在竖直方向的投影与对应的第二扇出线21的部分重叠并经一对应的贯穿层间绝缘层40的第一过孔41与该第二扇出线21电性连接。所述第一扇出线32的部分在竖直方向的投影与对应的数据线31所对应的第二扇出线21的部分重叠并经一对应的贯穿层间绝缘层40的第二过孔42与该第二扇出线21电性连接。多条第二扇出线21位于对应的第一过孔41与对应的第二过孔42之间的部分的内阻相等。
请参阅图3并结合图5，所述第一扇出线32的部分在竖直方向的投影与对应的数据线31所对应的第三扇出线22的部分重叠并经一对应的贯穿层间绝缘层40的第三过孔43与该第三扇出线22电性连接。
值得重点注意的是，所述第一金属层20的表面电阻率大于第二金属层30的表面电阻率。
具体地，请参阅图3，所述数据线31延伸至扇出区102的端部在竖直方向的投影与对应的第二扇出线21靠近有效显示区101的端部重叠并经对应的第一过孔41与该第二扇出线21靠近有效显示区101的端部电性连接。所述第一扇出线32靠近有效显示区101的端部在竖直方向的投影与对应的数据线31所对应的第二扇出线21远离有效显示区101的端部重叠并经对应的第二过孔42与该第二扇出线21远离有效显示区101的端部电性连接。所述第二扇出线21与对应的数据线31的延伸方向相同。
具体地，请参阅图3，所述第一扇出线32远离有效显示区101的端部在竖直方向的投影与对应的数据线31所对应的第三扇出线22靠近有效显示区101的端部重叠并经对应的第三过孔43与该第三扇出线22靠近有效显示区101的端部电性连接。进一步地，所述第三扇出线22远离有效显示区101的端部延伸至衬底10的边缘。
具体地，所述多条第二扇出线21的内阻相同，所述多条第三扇出线22的内阻相同。
优选地，请参阅图3，所述第二扇出线21与对应的数据线31的延伸方向相同。多条第三扇出线22与多条数据线31相平行。多条数据线31中最外侧的两条数据线31之间的距离大于多条第三扇出线22中最外侧的两条第三扇出线22之间的距离，对应不同的数据线31的第一扇出线31的长度不同。
具体地，所述第一金属层20的表面电阻率为0.4Ω/□-0.5Ω/□，优选为0.45Ω/□。所述第二金属层30的表面电阻率为0.05Ω/□-0.15Ω/□，优选为0.1Ω/□。
具体地，请参阅图3，所述第一金属层20还包括设置在有效显示区101内的多条平行且间隔的扫描线23。所述多条扫描线23与多条数据线31垂直。
需要说明的是，本发明的TFT阵列基板将扇出区102内的分别与多条数据线31对应的多条第二扇出线21设置在第一金属层20上，将扇出区102内的分别与多条数据线31对应的第一扇出线32设置在第二金属层30上，将扇出区102内的分别与多条数据线31对应的第三扇出线22设置在第一金属层20上。数据线31与第二扇出线21之间、第二扇出线21与第一扇出线32之间以及第一扇出线32与第三扇出线22之间通过相应的过孔连接，通过对第一金属层20及第二金属层30的材料进行选择，使第一金属层20 的表面电阻率大于第二金属层30的表面电阻率，从而相较于现有技术中与同一数据线对应的扇出线整体均与数据线同层，本发明中与同一条数据线31对应的第一扇出线32、第二扇出线21及第三扇出线22的内阻的总和大大增加，且表面电阻率较低的第一扇出线32的内阻在第一扇出线32、第二扇出线21及第三扇出线22的内阻的总和中的比例较小，使得第一扇出线32的内阻变化对第一扇出线32、第二扇出线21及第三扇出线22的内阻总和的影响较小，因而即使TFT阵列基板的尺寸加大，对应不同数据线31的第一扇出线32之间的长度差异较大，对应不同数据线31的第一扇出线32、第二扇出线21及第三扇出线22的内阻总和之间的差异性依旧很小，从而在利用扇出线向多条数据线31上提供数据信号时，各条数据线31接收数据信号不会出现时序差异，有效提升产品的品质，且相较于现有技术在扇出线的第一直线部上制作拐角来增大扇出线的长度，本发明制作过程可靠性高，不会产生扇出线短路的风险。
基于同一发明构思，本发明还提供一种显示装置，包括上述的TFT阵列基板，在此不再对TFT阵列基板的结构进行重复性描述。
具体地，本发明的显示装置为液晶显示装置或其他现有技术中需要使用TFT阵列基板作为驱动结构的显示装置。
需要说明的是，本发明的显示装置由于采用了上述的TFT阵列基板，相较于现有技术中与同一数据线对应的扇出线整体均与数据线同层，本发明中与同一条数据线31对应的第一扇出线32、第二扇出线21及第三扇出线22的内阻的总和大大增加，且表面电阻率较低的第一扇出线32的内阻在第一扇出线32、第二扇出线21及第三扇出线22的内阻的总和中的比例较小，使得第一扇出线32的内阻变化对第一扇出线32、第二扇出线21及第三扇出线22的内阻总和的影响较小，因而即使显示基板的尺寸加大，对应不同数据线31的第一扇出线32之间的长度差异较大，对应不同数据线31的第一扇出线32、第二扇出线21及第三扇出线22的内阻总和之间的差异性依旧很小，从而在利用扇出线向多条数据线31上提供数据信号时，各条数据线31接收数据信号不会出现时序差异，有效提升产品的品质，且相较于现有技术在扇出线的第一直线部上制作拐角来增大扇出线的长度，本发明制作过程可靠性高，不会产生扇出线短路的风险。
综上所述，本发明的TFT阵列基板将扇出区内的分别与多条数据线对应的多条第二扇出线设置在第一金属层上，将扇出区内的分别与多条数据线对应的第一扇出线设置在第二金属层上，数据线与第二扇出线之间以及第二扇出线与第一扇出线之间通过过孔连接，第一金属层的表面电阻率大 于第二金属层的表面电阻率，从而增大对应每一条数据线的扇出线整体的内阻，减少对应不同的数据线的扇出线之间的内阻差异性，从而在利用扇出线向多条数据线上提供数据信号时，各条数据线接收数据信号不会出现时序差异，有效提升产品的品质，且制作过程可靠性高，不会产生扇出线短路的风险。本发明的显示装置能够有效降低对应不同数据线的扇出线之间的内阻差异性，实现数据信号的稳定输入。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种TFT阵列基板，包括衬底、设于衬底上的第一金属层及设于第一金属层上方与第一金属层绝缘的第二金属层；
    所述第二金属层包括多条平行且间隔的数据线及分别对应多条数据线的多条第一扇出线，所述第一扇出线与其对应的数据线间隔；所述第一金属层包括分别与多条数据线对应的多条第二扇出线；
    所述TFT阵列基板具有依次设置的有效显示区及扇出区，多条数据线均位于有效显示区且具有延伸至扇出区的端部，多条第一扇出线及第二扇出线均位于扇出区；所述数据线延伸至扇出区的端部在竖直方向的投影与对应的第二扇出线的部分重叠并经一对应的第一过孔与该第二扇出线电性连接；所述第一扇出线的部分在竖直方向的投影与对应的数据线所对应的第二扇出线的部分重叠并经一对应的第二过孔与该第二扇出线电性连接；多条第二扇出线位于对应的第一过孔与对应的第二过孔之间的部分的内阻相等；
    所述第一金属层的表面电阻率大于第二金属层的表面电阻率。
  2. 如权利要求1所述的TFT阵列基板，其中，所述数据线延伸至扇出区的端部在竖直方向的投影与对应的第二扇出线靠近有效显示区的端部重叠并经对应的第一过孔与该第二扇出线靠近有效显示区的端部电性连接；所述第一扇出线靠近有效显示区的端部在竖直方向的投影与对应的数据线所对应的第二扇出线远离有效显示区的端部重叠并经对应的第二过孔与该第二扇出线远离有效显示区的端部电性连接；
    所述第二扇出线与对应的数据线的延伸方向相同；
    多条第二扇出线的内阻相同。
  3. 如权利要求1所述的TFT阵列基板，其中，所述第一金属层还包括分别与多条数据线对应的多条第三扇出线；多条第三扇出线均位于扇出区；对应同一数据线的第二扇出线及第三扇出线相间隔；所述第一扇出线的部分在竖直方向的投影与对应的数据线所对应的第三扇出线的部分重叠并经一对应的第三过孔与该第三扇出线电性连接。
  4. 如权利要求3所述的TFT阵列基板，其中，所述第一扇出线远离有效显示区的端部在竖直方向的投影与对应的数据线所对应的第三扇出线靠近有效显示区的端部重叠并经对应的第三过孔与该第三扇出线靠近有效显示区的端部电性连接；所述第三扇出线远离有效显示区的端部延伸至衬底 的边缘。
  5. 如权利要求4所述的TFT阵列基板，其中，多条第三扇出线与多条数据线相平行；
    多条第三扇出线的内阻相同。
  6. 如权利要求5所述的TFT阵列基板，其中，多条数据线中最外侧的两条数据线之间的距离大于多条第三扇出线中最外侧的两条第三扇出线之间的距离。
  7. 如权利要求1所述的TFT阵列基板，其中，所述第一金属层的表面电阻率为0.4Ω/□-0.5Ω/□；所述第二金属层的表面电阻率为0.05Ω/□-0.15Ω/□。
  8. 如权利要求3所述的TFT阵列基板，还包括设于所述第一金属层与第二金属层之间的层间绝缘层，所述第一过孔、第二过孔及第三过孔均贯穿所述层间绝缘层。
  9. 如权利要求1所述的TFT阵列基板，其中，所述第一金属层还包括设置在有效显示区内的多条平行且间隔的扫描线；
    所述多条扫描线与多条数据线垂直。
  10. 一种显示装置，包括如权利要求1所述的TFT阵列基板。
PCT/CN2018/106330 2018-04-27 2018-09-18 Tft阵列基板及显示装置 WO2019205467A1 (zh)

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