WO2015096203A1 - 液晶面板 - Google Patents

液晶面板 Download PDF

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Publication number
WO2015096203A1
WO2015096203A1 PCT/CN2014/070203 CN2014070203W WO2015096203A1 WO 2015096203 A1 WO2015096203 A1 WO 2015096203A1 CN 2014070203 W CN2014070203 W CN 2014070203W WO 2015096203 A1 WO2015096203 A1 WO 2015096203A1
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WO
WIPO (PCT)
Prior art keywords
metal
metal circuit
circuit layer
layer
transparent conductive
Prior art date
Application number
PCT/CN2014/070203
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English (en)
French (fr)
Inventor
韩丙
王金杰
Original Assignee
深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/234,394 priority Critical patent/US9146436B2/en
Publication of WO2015096203A1 publication Critical patent/WO2015096203A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to a liquid crystal panel, and more particularly to a liquid crystal panel which improves the display quality of a panel.
  • the liquid crystal panel includes a thin film transistor array substrate (thin Film transistor array substrate, a color filter substrate (color filter a substrate) and a layer of liquid crystal molecules distributed between the array substrate and the color filter substrate.
  • the array substrate has a plurality of pixels defined by intersections of the data lines and the corresponding scan lines, and a pixel drive circuit configured to drive the pixels by a plurality of electronic components.
  • the color filter substrate is a transparent glass substrate on which a transparent conductive film layer formed of, for example, ITO or IZO material is sputtered.
  • the transparent conductive film layer is electrically connected to the common electrode power source, and generates a predetermined voltage together with the corresponding pixel electrode applied on the array substrate to control the twist of the liquid crystal.
  • a conventional liquid crystal panel includes a plurality of data lines 11 , a plurality of scan lines 12 , and a plurality of pixel driving circuits 13 , wherein FIG. 1 only shows two data lines 11 .
  • the data line 11 intersects with the corresponding scan line 12 and is located on an array substrate 14.
  • the pixel drive circuit 13 is disposed between the corresponding data line 11 and the scan line 12.
  • the metal lines of the data line 11 and the scan line 12 are generally single metal (Single Metal) Vertical alignment, because the resistance of the metal wire is inversely proportional to the thickness, and single metal (Single Metal) The resistance value is high, and the impedance of the scan line 12 is too large, so that the waveform signal of the gate is delayed as shown in FIG. 3, thereby generating mischarge, crosstalk, and fanout. Uneven (fan-out Mura) question.
  • the metal line width of the scanning line 12 is widened to lower the resistance value, the capacitance is also increased.
  • increasing the thickness of the metal line of the scan line 12 to lower the resistance value not only increases the difficulty of the process, but also wastes the metal wire material, so the fundamental problem cannot be completely solved.
  • the present invention provides a liquid crystal panel to solve the problem that the impedance of the scanning line existing in the prior art is too large to cause mischarge, crosstalk, and fan out.
  • a main object of the present invention is to provide a liquid crystal panel which can reduce the impedance of the scanning line by connecting a second metal wiring layer and a third metal wiring layer in parallel.
  • a secondary object of the present invention is to provide a liquid crystal panel which can be connected in parallel by a second metal wiring layer and a third metal wiring layer to improve the problems of mischarge, crosstalk, and fan out unevenness.
  • an embodiment of the present invention provides a liquid crystal panel, wherein the liquid crystal panel includes a plurality of data lines, a plurality of scan lines, and a plurality of display units, each of the data lines having a first a metal circuit layer, the scan line is vertically interlaced with the data line, wherein each of the scan lines has a second metal circuit layer, a third metal circuit layer and two transparent conductive lines, and the second metal circuit layer Interleaved in the first metal circuit layer, the third metal circuit layer is located above the second metal circuit layer, and the two transparent conductive lines are spaced apart and located in the second metal circuit layer and the third metal circuit layer One transparent conductive line is electrically connected to one front end of the second metal circuit layer and the third metal circuit layer, and another transparent conductive line is electrically connected to the second metal circuit layer and the first A rear end of the three metal circuit layer, each of the display units is electrically connected to the corresponding data line and the scan line.
  • each of the transparent conductive lines has an inner portion and an outer portion, the inner portion is away from the data line, the outer portion is adjacent to the data line, and the third metal The circuit layer is partially projected on the inner side portion.
  • the liquid crystal panel further includes a first insulating layer, a lower conductive via, a second insulating layer, and an upper conductive via, wherein the first insulating layer is formed in the second
  • the lower conductive via is formed in the first insulating layer and connects the second metal wiring layer to an outer portion of the transparent conductive line
  • the second insulating layer is formed on the metal wiring layer
  • the first insulating layer covers the transparent conductive line
  • the upper conductive via is formed in the second insulating layer and connects the inner portion of the transparent conductive line to the third metal circuit layer.
  • the first and third metal circuit layers are made of the same metal, and the second metal circuit layer is made of another different metal.
  • the first, second and third metal circuit layers are chromium, molybdenum or tungsten molybdenum alloy.
  • another embodiment of the present invention provides another liquid crystal panel, wherein the liquid crystal panel includes a plurality of data lines, a plurality of scan lines, and a plurality of display units, each of the data lines having a first metal circuit layer.
  • the scan line is vertically interlaced with the data line, wherein each of the scan lines has a second metal line layer, a third metal line layer and a single transparent conductive line, and the second metal line layer is interlaced a first metal circuit layer, the third metal circuit layer is located above the second metal circuit layer, the transparent conductive line is located between the second metal circuit layer and the third metal circuit layer, and the transparent One end of the conductive line is electrically connected to a front end of the second metal circuit layer and the third metal circuit layer, and the other end of the transparent conductive line is electrically connected to the second metal circuit layer and the third A rear end of the metal circuit layer, each of the display units is electrically connected to the corresponding data line and the scan line.
  • the length of the transparent conductive line is greater than the length of the third metal circuit layer.
  • the transparent conductive line has a front side portion and a rear side portion, and the front side portion and the rear side portion are respectively adjacent to two adjacent data lines, the front side portion and the rear side portion
  • Each of the side portions forms an upper conductive via and a lower conductive via, the upper conductive via is connected to the third metal wiring layer, and the lower conductive via is connected to the second metal wiring layer.
  • the liquid crystal panel further includes a first insulating layer, a pair of lower conductive vias, a second insulating layer and a pair of upper conductive vias, wherein the first insulating layer is formed in the On the second metal circuit layer, the lower conductive via is formed in the first insulating layer, and connects the second metal wiring layer to the front side and the rear side of the transparent conductive line, respectively.
  • a second insulating layer is formed on the first insulating layer and covers the transparent conductive line, and the upper conductive via is formed in the second insulating layer and respectively respectively front side of the transparent conductive line And a rear side portion is connected to the third metal circuit layer.
  • the first and third metal circuit layers are made of the same metal
  • the second metal circuit layer is made of another different metal
  • the first and second And the third metal circuit layer is a chromium, molybdenum or tungsten molybdenum alloy.
  • the third metal circuit layer is stacked on the second metal circuit layer and electrically connected, so that the second metal circuit layer and the third metal circuit layer are formed in parallel, thereby making the actual resistance value smaller and lower.
  • the impedance of the scan line further improves the problem of mischarge, crosstalk, and fan out unevenness to improve the display quality of the display panel.
  • a transparent layer is disposed between the second metal circuit layer and the third metal circuit layer. The conductive line can also avoid short circuits between the second metal circuit layer and the third metal circuit layer.
  • FIG. 1 is a schematic view of a conventional liquid crystal panel.
  • Fig. 2 is a cross-sectional view of the scanning line of Fig. 1.
  • FIG 3 is a schematic view of a gate waveform signal of a conventional liquid crystal panel.
  • Figure 4 is a schematic view of a liquid crystal panel according to a first embodiment of the present invention.
  • Fig. 5 is a cross-sectional view of the scanning line of Fig. 4;
  • Fig. 6 is a view showing a gate waveform signal of a liquid crystal panel according to a first embodiment of the present invention.
  • Figure 7 is a schematic view of a liquid crystal panel according to a second embodiment of the present invention.
  • Fig. 8 is a cross-sectional view of the scanning line of Fig. 7.
  • the liquid crystal panel 100 of the first embodiment of the present invention mainly includes an array substrate of a thin film transistor (TFT array).
  • Substrate) 20 a color filter substrate (CF) a substrate (not shown) and a liquid crystal material layer (not shown) interposed between the two substrates, wherein the array substrate 20 has a plurality of data on a surface (ie, an inner surface) adjacent to the liquid crystal material layer a line 21, a plurality of scanning lines 22, a plurality of display units 23, a first insulating layer 24, a second insulating layer 25, a third insulating layer 26, a plurality of lower conductive vias 27, and a plurality of upper conductive vias 28.
  • FIG. 4 is a view showing only two data lines 21 and one scanning line 22 on a partial area of the array substrate 20.
  • the present invention will be described in detail below with reference to FIGS. 4 to 6 for detailed construction of the above-mentioned components of the first embodiment. , assembly relationship and its operating principle.
  • the liquid crystal panel 100 of the present invention performs a photo-etching-process on the inner surface of the array substrate 20. PEP) to form the data line 21 and the scan line 22, wherein the array substrate 20 includes a plurality of pixel regions 201.
  • each data line 21 has a first metal circuit layer 211, and the scan lines 22 are vertically interlaced with the data lines 21, wherein each scan line 22 has a second metal.
  • a circuit layer 221, a third metal circuit layer 222 and two transparent conductive lines 223, 223' the second metal circuit layer 221 is interleaved with the first metal circuit layer 211, and the third metal circuit layer 222 is located at Above the second metal circuit layer 221, the two transparent conductive lines 223, 223' are spaced apart from each other, and the two transparent conductive lines 223, 223' are located at the second metal circuit layer 221 and the third metal circuit layer 222. between.
  • the first metal 211 and the third metal 222 layer are made of the same metal
  • the second metal circuit layer 221 is made of another different metal
  • the first metal The circuit layer 211, the second metal wiring layer 221, and the third metal wiring layer 222 are each selected from the group consisting of chromium, molybdenum, or tungsten-molybdenum alloy.
  • each of the transparent conductive lines 223, 223' has an inner portion 228 and an outer portion 229, the inner portion 228 being away from the data line 21, and the outer portion 229 is adjacent to the The data line 21, the third metal circuit layer 222 is partially projected on the inner portion 228, wherein a transparent conductive line 223 is electrically connected to the second metal circuit layer 221 and the third metal circuit layer 222.
  • the front end, another transparent conductive line 223' is electrically connected to the second metal circuit layer 221 and a rear end of the third metal circuit layer 222.
  • the transparent conductive lines 223, 223' Indium tin oxide (indium) Tin oxide, ITO) transparent conductive film,
  • the first insulating layer 24 is formed on the second metal wiring layer 221, and the lower conductive via 27 is formed in the first insulating layer 24, and is connected
  • the second metal circuit layer 221 is formed on the outer portion 229 of the transparent conductive lines 223, 223'.
  • the second insulating layer 25 is formed on the first insulating layer 24 and covers the transparent conductive lines 223, 223.
  • the upper conductive via 28 is formed in the second insulating layer 25 and connects the inner portion 228 of the transparent conductive traces 223, 223' to the third metal wiring layer 222.
  • each display unit 23 is electrically connected to the corresponding data line 21 and scan line 22, and the display unit 23, such as a pixel driving circuit and a pixel electrode, are disposed in corresponding pixels.
  • the display unit 23, such as a pixel driving circuit and a pixel electrode, are disposed in corresponding pixels.
  • area 201 In area 201.
  • the third metal circuit layer 222 is stacked on the second metal circuit layer 221, and the upper conductive via 28 and the lower conductive via are utilized.
  • the holes 27 electrically connect the two, and when the second metal circuit layer 221 and the third metal circuit layer 222 are energized, the second metal circuit layer 221 and the third metal circuit layer 222 can be connected in parallel (parallel) Connection), thus making the actual resistance value smaller, lowering the impedance of the scan line 22, so that the waveform signal of the gate eliminates the delay phenomenon as shown in FIG. 6, thereby improving the mischarge and crosstalk ( Crosstalk) and fanout out (fan-out Mura's problem to improve the display quality of the display panel.
  • the transparent conductive lines 223, 223' provided with indium tin oxide between the second metal circuit layer 221 and the third metal circuit layer 222 can also avoid the second metal circuit layer 221 and the third metal circuit layer. A short circuit occurred between 222.
  • the liquid crystal panel 100 of the second embodiment of the present invention is similar to the first embodiment of the present invention, and generally uses the same component names and drawings.
  • the second embodiment of the present invention is characterized by:
  • Each of the data lines 21 has a first metal circuit layer 211, and the scan lines 22 are vertically interleaved with the data lines 21, wherein each of the scan lines 22 has a second metal circuit layer 221 and a third metal circuit layer 222.
  • a single transparent conductive line 223, the second metal circuit layer 221 is staggered to the first metal circuit layer 211, and the third metal circuit layer 222 is located above the second metal circuit layer 221, the single transparent conductive The line 223 is located between the second metal circuit layer 221 and the third metal circuit layer 222, and one end of the transparent conductive line 223 is electrically connected to the second metal circuit layer 221 and the third metal circuit layer 222. The other end of the transparent conductive line 223 is electrically connected to a rear end of the second metal circuit layer 221 and the third metal circuit layer 222.
  • the transparent conductive line 223 has a front side portion 226 and a rear side portion 227, and the length of the transparent conductive line 223 is greater than the length of the third metal line layer 222.
  • the front side portion 226 and the rear side portion 227 are respectively adjacent to two adjacent data lines 21, wherein the front side portion 226 and the rear side portion 227 each form an upper conductive through hole 28 and a lower conductive through hole 27.
  • the conductive vias 28 are connected to the third metal wiring layer 222, and the lower conductive vias 27 are connected to the second metal wiring layer 221.
  • each display unit 23 is electrically connected to the corresponding data line 21 and scan line 22 .
  • the first metal circuit layer 211 and the third metal circuit layer 222 are also made of the same metal
  • the second metal circuit layer 221 is made of another different metal
  • the The one metal 211, the second metal 221, and the third metal wiring layer 222 are chromium, molybdenum or tungsten molybdenum alloy.
  • the liquid crystal panel 100 further includes a first insulating layer 24 , a pair of lower conductive vias 27 , a second insulating layer 25 , and a pair of upper conductive vias 28 .
  • An insulating layer 24 is formed on the second metal wiring layer 221, and the lower conductive vias 27 are formed in the first insulating layer 24, and respectively connect the second metal wiring layer 221 to the transparent conductive
  • the front side portion 226 and the rear side portion 227 of the line 223 are formed on the first insulating layer 24 and cover the transparent conductive line 223, and the upper conductive via hole 28 is formed in the
  • the front side portion 226 and the rear side portion 227 of the transparent conductive line 223 are respectively connected to the third metal line layer 222 in the second insulating layer 25.
  • the third metal wiring layer 222 is stacked on the second metal wiring layer 221, and the upper conductive via 28 and the lower conductive via are utilized. 27 electrically connecting the two, when the second metal circuit layer 221 and the third metal circuit layer 222 are energized, the second metal circuit layer 221 and the third metal circuit layer 222 can be connected in parallel, thus making the actual The resistance value becomes smaller, the impedance of the scan line 22 is lowered, thereby improving mischarge, crosstalk, and fan outout (fan-out) Mura's problem to improve the display quality of the display panel.
  • the transparent conductive line 223 provided with indium tin oxide between the second metal circuit layer 221 and the third metal circuit layer 222 can also avoid the between the second metal circuit layer 221 and the third metal circuit layer 222. A short circuit has occurred.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种液晶面板，包括多条数据线（21）、多条扫描线（22）及多个显示单元（23）。每一扫描线（22）具有一第二金属线路层（221）、第三金属线路层（222）及二透明导电线路（223、223'）。第三金属线路层（222）位于第二金属线路层（221）上方，两透明导电线路（223、223'）相间隔且位于第二金属线路层（221）和第三金属线路层（222）之间，通过第三金属线路层（222）与第二金属线路层（221）电性连接，使第二金属线路层（221）及第三金属线路层（222）形成并联，降低扫描线（22）的阻抗。

Description

液晶面板 技术领域
本发明是有关于一种液晶面板，特别是有关于一种改善面板显示质量的的液晶面板。
 背景技术
目前，随着半导体技术和制造工艺的发展，具有高质量、低功耗、无辐射和体积小等优越性能的薄膜晶体管液晶显示器(TFT-LCD)已经逐渐成为市场的主流。一般来说，液晶面板包括一薄膜晶体管阵列基板(thin film transistor array substrate)、一彩色滤光片基板(color filter substrate)和分布在阵列基板与彩色滤光片基板之间的的液晶分子层。具体而言，在阵列基板上具有由数据线与相应扫描线的交叉位置所定义的多个像素，以及由多个电子组件构成用来驱动所述像素的像素驱动电路。其中所述彩色滤光片基板是一透明的玻璃基板，在其上溅出例如ITO或IZO材料形成的透明导电膜层。所述透明导电膜层与公共电极电源电性连接，与加在阵列基板上的相应像素电极一起产生预定电压，以便控制液晶的扭转。
参阅图1及图2所示，其揭示一种现有的液晶面板，其包含多个数据线11、多个扫描线12及多个像素驱动电路13，其中图1仅绘示二数据线11及一扫描线12作说明，所述数据线11与相应的扫描线12交叉并位于一阵列基板14上，所述像素驱动电路13设置在相应的数据线11及扫描线12之间。所述数据线11及扫描线12的金属线一般采用单金属(Single Metal)垂直排列，由于金属线的阻值和厚度成反比，且单金属(Single Metal) 的阻值较高，所述扫描线12的阻抗过大而使得闸极(gate)的波形信号如图3所示发生延迟(delay)的现象，因而产生错充、串扰(Crosstalk)及扇出不匀(fan-out mura)的问题。欲解决上述的问题，倘若加宽所述扫描线12的金属线宽以降低阻值，会造成电容也变大。另外，增加所述扫描线12的金属线的厚度以降低阻值，不仅增加制程的难度，更浪费金属线材料，因此仍无法完全解决根本上问题。
 技术问题
有鉴于此，本发明提供一种液晶面板，以解决现有技术所存在的扫描线的阻抗过大而产生错充、串扰及扇出不匀的问题。
本发明的主要目的在于提供一种液晶面板，其可以通过第二金属线路层及第三金属线路层并联，降低所述扫描线的阻抗。
本发明的次要目的在于提供一种液晶面板，其可以通过第二金属线路层及第三金属线路层并联，改善错充、串扰及扇出不匀的问题。
 技术解决方案
为达成本发明的前述目的，本发明一实施例提供一种液晶面板，其中所述液晶面板包含多条数据线、多条扫描线及多个显示单元，每一所述数据线具有一第一金属线路层，所述扫描线与所述数据线垂直交错，其中每一所述扫描线具有一第二金属线路层、一第三金属线路层及二透明导电线路，所述第二金属线路层交错于所述第一金属线路层，所述第三金属线路层位于所述第二金属线路层上方，所述两透明导电线路相间隔且位于所述第二金属线路层及第三金属线路层之间，其中一透明导电线路电性连接所述第二金属线路层及所述第三金属线路层的一前端，另一透明导电线路电性连接于所述第二金属线路层及所述第三金属线路层的一后端，每一所述显示单元电性连接相应的所述数据线及扫描线。
在本发明的一实施例中，每一所述透明导电线路具有一内侧部及一外侧部，所述内侧部远离所述数据线，所述外侧部靠近所述数据线，所述第三金属线路层局部投影在所述内侧部上。
在本发明的一实施例中，所述液晶面板还包含一第一绝缘层、一下导电通孔、一第二绝缘层及一上导电通孔，所述第一绝缘层形成在所述第二金属线路层上，所述下导电通孔形成在所述第一绝缘层中，并连接所述第二金属线路层至所述透明导电线路的外侧部，所述第二绝缘层形成在所述第一绝缘层上，并覆盖所述透明导电线路，所述上导电通孔形成在所述第二绝缘层中并连接所述透明导电线路的内侧部至所述第三金属线路层。
在本发明的一实施例中，所述第一及第三金属线路层由同一种金属制成，所述第二金属线路层由另一种不同金属制成
在本发明的一实施例中，所述第一、第二及第三金属线路层为铬、钼或钨钼合金。
再者，本发明另一实施例提供另一种液晶面板，其中所述液晶面板包含多条数据线、多条扫描线及多个显示单元，每一所述数据线具有一第一金属线路层，所述扫描线与所述数据线垂直交错，其中每一所述扫描线具有一第二金属线路层、一第三金属线路层及单一透明导电线路，所述第二金属线路层交错于所述第一金属线路层，所述第三金属线路层位于所述第二金属线路层上方，所述透明导电线路位于所述第二金属线路层及第三金属线路层之间，且所述透明导电线路的一端电性连接所述第二金属线路层及所述第三金属线路层的一前端，所述透明导电线路的另一端电性连接于所述第二金属线路层及所述第三金属线路层的一后端，每一所述显示单元电性连接相应的所述数据线及扫描线。
在本发明的一实施例中，所述透明导电线路的长度大于所述第三金属线路层的长度。
在本发明的一实施例中，所述透明导电线路具有一前侧部及一后侧部，所述前侧部及后侧部分别靠近两相邻的数据线，所述前侧部及后侧部各自皆形成一上导电通孔及一下导电通孔，所述上导电通孔连接所述第三金属线路层，所述下导电通孔连接所述第二金属线路层。
在本发明的一实施例中，所述液晶面板还包含一第一绝缘层、一对下导电通孔、一第二绝缘层及一对上导电通孔，所述第一绝缘层形成在所述第二金属线路层上，所述下导电通孔形成在所述第一绝缘层中，并分别连接所述第二金属线路层至所述透明导电线路的前侧部及后侧部，所述第二绝缘层形成在所述第一绝缘层上，并覆盖所述透明导电线路，所述上导电通孔形成在所述第二绝缘层中并分别将所述透明导电线路的前侧部及后侧部连接至所述第三金属线路层。
在本发明的一实施例中，所述第一及第三金属线路层由同一种金属制成，所述第二金属线路层由另一种不同金属制成，且所述第一、第二及第三金属线路层为铬、钼或钨钼合金。
 有益效果
通过所述第三金属线路层叠放在所述第二金属线路层上并电性连接，使所述第二金属线路层及第三金属线路层形成并联，因此使得实际电阻阻值变小、降低所述扫描线的阻抗，进而改善错充、串扰及扇出不匀的问题，以提高显示面板的显示品质，再者，在所述第二金属线路层及第三金属线路层之间设置透明导电线路还可避免所述第二金属线路层及第三金属线路层之间出现短路。
 附图说明
图1是现有的液晶面板的示意图。
图2是图1的扫描线的剖视图。
图3是现有的液晶面板的闸极波形信号的示意图。
图4是本发明第一实施例液晶面板的示意图。
图5是图4的扫描线的剖视图。
图6是本发明第一实施例液晶面板的闸极波形信号的示意图。
图7是本发明第二实施例液晶面板的示意图。
图8是图7的扫描线的剖视图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参照图4及图5所示，本发明第一实施例的液晶面板100主要包含一薄膜晶体管的阵列基板(TFT array substrate)20、一彩色滤光片基板(CF substrate，未绘示)以及夹设在两基板之间的一液晶材料层(未绘示)，其中所述阵列基板20在靠近所述液晶材料层的表面(即内表面)上具有多条数据线21、多条扫描线22、多个显示单元23、一第一绝缘层24、一第二绝缘层25、一第三绝缘层26、多个下导电通孔27及多个上导电通孔28。其中图4仅绘示所述阵列基板20局部区域上的二数据线21及一扫描线22作说明，本发明将于下文利用图4至6逐一详细说明第一实施例上述各元件的细部构造、组装关系及其运作原理。
请参照图4及图5所示，本发明液晶面板100是在所述阵列基板20的内表面上进行光刻工艺(photo-etching-process, PEP)，以形成所述数据线21及扫描线22，其中所述阵列基板20包含数个像素区域201。
请参照图4及图5所示，每一数据线21具有一第一金属线路层211，而所述扫描线22与所述数据线21垂直交错，其中每一扫描线22具有一第二金属线路层221、一第三金属线路层222及二透明导电线路223、223’，所述第二金属线路层221交错于所述第一金属线路层211，所述第三金属线路层222位于所述第二金属线路层221上方，所述两透明导电线路223、223’彼此相间隔，且所述两透明导电线路223、223’位于所述第二金属线路层221及第三金属线路层222之间。在本实施例中，所述第一金属211及第三金属222层是由同一种金属制成，所述第二金属线路层221则由另一种不同金属制成，而且所述第一金属线路层211、第二金属线路层221及第三金属线路层222分别选自铬、钼或钨钼合金。
续参照图4及图5所示，每一透明导电线路223、223’具有一内侧部228及一外侧部229，所述内侧部228远离所述数据线21，所述外侧部229靠近所述数据线21，所述第三金属线路层222局部投影在所述内侧部上228，其中一透明导电线路223电性连接所述第二金属线路层221及所述第三金属线路层222的一前端，另一透明导电线路223’电性连接于所述第二金属线路层221及所述第三金属线路层222的一后端，在本实施例中，所述透明导电线路223、223’为铟锡氧化物(indium tin oxide, ITO)的透明导电膜，
续参照图4及图5所示，所述第一绝缘层24形成在所述第二金属线路层221上，所述下导电通孔27形成在所述第一绝缘层24中，并连接所述第二金属线路层221至所述透明导电线路223、223’的外侧部229，所述第二绝缘层25形成在所述第一绝缘层24上，并覆盖所述透明导电线路223、223’，所述上导电通孔28形成在所述第二绝缘层25中，并连接所述透明导电线路223、223’的内侧部228至所述第三金属线路层222。
续参照图4及图5所示，每一显示单元23电性连接相应的所述数据线21及扫描线22，且所述显示单元23，例如像素驱动电路及像素电极，设置在相应的像素区域201中。
续参照图4及图5所示，依据上述的设计，通过所述第三金属线路层222叠放在所述第二金属线路层221上，并利用所述上导电通孔28及下导电通孔27将两者电性连接，当所述第二金属线路层221及第三金属线路层222通电时，能够使所述第二金属线路层221及第三金属线路层222形成并联(parallel connection)，因此使得实际电阻阻值变小、降低所述扫描线22的阻抗，使得闸极(gate)的波形信号如图6所示消除延迟(delay)的现象，因而改善错充、串扰(Crosstalk)及扇出不匀(fan-out mura)的问题，以提高显示面板的显示品质。另外，在所述第二金属线路层221及第三金属线路层222之间设置铟锡氧化物的透明导电线路223、223’还可避免所述第二金属线路层221及第三金属线路层222之间出现短路。
请参照图7、8所示，本发明第二实施例的液晶面板100相似于本发明第一实施例，并大致沿用相同元件名称及图号，但本发明第二实施例的差异特征在于：每一数据线21具有一第一金属线路层211，所述扫描线22与所述数据线21垂直交错，其中每一扫描线22具有一第二金属线路层221、一第三金属线路层222及单一透明导电线路223，所述第二金属线路层221交错于所述第一金属线路层211，所述第三金属线路层222位于所述第二金属线路层221上方，所述单一透明导电线路223位于所述第二金属线路层221及第三金属线路层222之间，且所述透明导电线路223的一端电性连接所述第二金属线路层221及所述第三金属线路层222的一前端，所述透明导电线路223的另一端电性连接于所述第二金属线路层221及所述第三金属线路层222的一后端。
续请参照图7、8所示，所述透明导电线路223具有一前侧部226及一后侧部227，且所述透明导电线路223的长度大于所述第三金属线路层222的长度，所述前侧部226及后侧部227分别靠近两相邻的数据线21，其中所述前侧部226及后侧部227各自皆形成一上导电通孔28及一下导电通孔27，所述上导电通孔28连接所述第三金属线路层222，所述下导电通孔27连接所述第二金属线路层221。
续请参照图7、8所示，每一显示单元23电性连接相应的所述数据线21及扫描线22。在本实施例中，所述第一金属线路层211及第三金属线路层222同样由同一种金属制成，所述第二金属线路层221由另一种不同金属制成，且所述第一金属211、第二金属221及第三金属线路层222为铬、钼或钨钼合金。
续请参照图7、8所示，所述液晶面板100还包含一第一绝缘层24、一对下导电通孔27、一第二绝缘层25及一对上导电通孔28，所述第一绝缘层24形成在所述第二金属线路层221上，所述下导电通孔27形成在所述第一绝缘层24中，并分别连接所述第二金属线路层221至所述透明导电线路223的前侧部226及后侧部227，所述第二绝缘层25形成在所述第一绝缘层24上，并覆盖所述透明导电线路223，所述上导电通孔28形成在所述第二绝缘层25中并分别将所述透明导电线路223的前侧部226及后侧部227连接至所述第三金属线路层222。
续参照图7及图8所示，如上所述，通过所述第三金属线路层222叠放在所述第二金属线路层221上，并利用所述上导电通孔28及下导电通孔27将两者电性连接，当所述第二金属线路层221及第三金属线路层222通电时，能够使所述第二金属线路层221及第三金属线路层222形成并联，因此使得实际电阻阻值变小、降低所述扫描线22的阻抗，进而改善错充、串扰(Crosstalk)及扇出不匀(fan-out mura)的问题，以提高显示面板的显示品质。另外，在所述第二金属线路层221及第三金属线路层222之间设置铟锡氧化物的透明导电线路223还可避免所述第二金属线路层221及第三金属线路层222之间出现短路。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。
本发明的实施方式
工业实用性
序列表自由内容

Claims (14)

  1. 一种液晶面板，其特征在于：所述液晶面板包含一薄膜晶体管的阵列基板、一彩色滤光片基板以及夹设在所述阵列基板及彩色滤光片基板之间的一液晶材料层，其中所述阵列基板在靠近所述液晶材料层的一表面上且具有：
    多条数据线，每一所述数据线具有一第一金属线路层；
    多条扫描线，与所述数据线垂直交错，其中每一所述扫描线具有：一第二金属线路层，交错于所述第一金属线路层；一第三金属线路层，位于所述第二金属线路层上方；及二透明导电线路，所述两透明导电线路相间隔且位于所述第二金属线路层及第三金属线路层之间，其中一透明导电线路电性连接所述第二金属线路层及所述第三金属线路层的一前端，另一透明导电线路电性连接于所述第二金属线路层及所述第三金属线路层的一后端；及
    多个显示单元，每一所述显示单元电性连接相应的所述数据线及扫描线；
    其中所述第一及第三金属线路层由同一种金属制成，所述第二金属线路层由另一种不同金属制成。
  2. 如权利要求1所述的液晶面板，其特征在于：每一所述透明导电线路具有：一内侧部，远离所述数据线；及一外侧部，靠近所述数据线，所述第三金属线路层局部投影在所述内侧部上。
  3. 如权利要求2所述的液晶面板，其特征在于：所述液晶面板还包含：一第一绝缘层，形成在所述第二金属线路层上；一下导电通孔，形成在所述第一绝缘层中，并连接所述第二金属线路层至所述透明导电线路的外侧部；一第二绝缘层，形成在所述第一绝缘层上，并覆盖所述透明导电线路；及一上导电通孔，形成在所述第二绝缘层中并连接所述透明导电线路的内侧部至所述第三金属线路层。
  4. 如权利要求1所述的液晶面板，其特征在于：所述第一、第二及第三金属线路层分别选自铬、钼或钨钼合金。
  5. 一种液晶面板，其特征在于：所述液晶面板包含：
    多条数据线，每一所述数据线具有一第一金属线路层；
    多条扫描线，与所述数据线垂直交错，其中每一所述扫描线具有：一第二金属线路层，交错于所述第一金属线路层；一第三金属线路层，位于所述第二金属线路层上方；及二透明导电线路，所述两透明导电线路相间隔且位于所述第二金属线路层及第三金属线路层之间，其中一透明导电线路电性连接所述第二金属线路层及所述第三金属线路层的一前端，另一透明导电线路电性连接于所述第二金属线路层及所述第三金属线路层的一后端；及
    多个显示单元，每一所述显示单元电性连接相应的所述数据线及扫描线。
  6. 如权利要求5所述的液晶面板，其特征在于：每一所述透明导电线路具有：一内侧部，远离所述数据线；及一外侧部，靠近所述数据线，所述第三金属线路层局部投影在所述内侧部上。
  7. 如权利要求6所述的液晶面板，其特征在于：所述液晶面板还包含：一第一绝缘层，形成在所述第二金属线路层上；一下导电通孔，形成在所述第一绝缘层中，并连接所述第二金属线路层至所述透明导电线路的外侧部；一第二绝缘层，形成在所述第一绝缘层上，并覆盖所述透明导电线路；及一上导电通孔，形成在所述第二绝缘层中并连接所述透明导电线路的内侧部至所述第三金属线路层。
  8. 如权利要求5所述的液晶面板，其特征在于：所述第一及第三金属线路层由同一种金属制成，所述第二金属线路层由另一种不同金属制成。
  9. 如权利要求8所述的液晶面板，其特征在于：所述第一、第二及第三金属线路层分别选自铬、钼或钨钼合金。
  10. 一种液晶面板，其特征在于：所述液晶面板包含：
    多条数据线，每一所述数据线具有一第一金属线路层；
    多条扫描线，与所述数据线垂直交错，其中每一所述扫描线具有：一第二金属线路层，交错于所述第一金属线路层；一第三金属线路层，位于所述第二金属线路层上方；及单一透明导电线路，所述透明导电线路位于所述第二金属线路层及第三金属线路层之间，且所述透明导电线路的一端电性连接所述第二金属线路层及所述第三金属线路层的一前端，所述透明导电线路的另一端电性连接于所述第二金属线路层及所述第三金属线路层的一后端；及
    多个显示单元，每一所述显示单元电性连接相应的所述数据线及扫描线。
  11. 如权利要求10所述的液晶面板，其特征在于：所述透明导电线路的长度大于所述第三金属线路层的长度。
  12. 如权利要求10所述的液晶面板，其特征在于：所述透明导电线路具有一前侧部及一后侧部，所述前侧部及后侧部分别靠近两相邻的数据线，所述前侧部及后侧部各自皆形成一上导电通孔及一下导电通孔，所述上导电通孔连接所述第三金属线路层，所述下导电通孔连接所述第二金属线路层。
  13. 如权利要求12所述的液晶面板，其特征在于：所述液晶面板还包含：一第一绝缘层，形成在所述第二金属线路层上；一对下导电通孔，形成在所述第一绝缘层中，并分别连接所述第二金属线路层至所述透明导电线路的前侧部及后侧部；一第二绝缘层，形成在所述第一绝缘层上，并覆盖所述透明导电线路；及一对上导电通孔，形成在所述第二绝缘层中并分别将所述透明导电线路的前侧部及后侧部连接至所述第三金属线路层。
  14. 如权利要求10所述的液晶面板，其特征在于：所述第一及第三金属线路层由同一种金属制成，所述第二金属线路层由另一种不同金属制成。
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