WO2020206785A1 - 显示面板及显示模组 - Google Patents

显示面板及显示模组 Download PDF

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Publication number
WO2020206785A1
WO2020206785A1 PCT/CN2019/086106 CN2019086106W WO2020206785A1 WO 2020206785 A1 WO2020206785 A1 WO 2020206785A1 CN 2019086106 W CN2019086106 W CN 2019086106W WO 2020206785 A1 WO2020206785 A1 WO 2020206785A1
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WO
WIPO (PCT)
Prior art keywords
pixel unit
thin film
film transistor
pixel
electrode
Prior art date
Application number
PCT/CN2019/086106
Other languages
English (en)
French (fr)
Inventor
曹武
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/617,002 priority Critical patent/US11333946B2/en
Publication of WO2020206785A1 publication Critical patent/WO2020206785A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the application relates to the display field, and in particular to a display panel and a display module.
  • COA ColorFilter on Array
  • the display panel is to arrange the color filter layer on the array substrate, which avoids the alignment error caused by the conventional array substrate and the color filter substrate, and improves the alignment accuracy of the display panel.
  • the arrangement of the color resist layer results in poor surface flatness of the array substrate, resulting in poor alignment and dark border lines and other technical problems, which reduces the yield of products.
  • the present application provides a display panel and a display module to solve technical problems such as dark lines appearing on the border of the existing display panel.
  • the present application provides a display panel including at least two pixel units
  • the pixel unit includes a substrate, a thin film transistor on the substrate, and a pixel electrode on the thin film transistor;
  • the thin film transistor in the same pixel unit is insulated and connected to the pixel electrode in the pixel unit;
  • the thin film transistor in the pixel unit is electrically connected to a pixel electrode in another pixel unit arranged in parallel.
  • a first pixel electrode of a first pixel unit of at least two pixel units is electrically connected to a second thin film transistor of a second pixel unit of at least two pixel units;
  • the second pixel electrode of the second pixel unit is electrically connected to the first thin film transistor of the first pixel unit.
  • At least one first branch electrode of the first pixel electrode extends toward the second thin film transistor and is electrically connected to the second thin film transistor;
  • At least one second branch electrode of the second pixel electrode extends toward the first thin film transistor and is electrically connected to the first thin film transistor.
  • the first pixel unit and the second pixel unit are arranged side by side in a first direction or a second direction;
  • the first direction is perpendicular to the second direction.
  • the first branch electrode of the first pixel electrode straddles between the first pixel unit and the second pixel unit And extend to the second thin film transistor, and are electrically connected to the source/drain of the second thin film transistor through the second via hole of the second pixel unit;
  • the second branch electrode of the second pixel electrode crosses the data line between the first pixel unit and the second pixel unit, extends toward the first thin film transistor, and passes through the first pixel unit.
  • the first via hole of the pixel unit is electrically connected with the source/drain of the first thin film transistor.
  • the first branch electrode of the first pixel electrode straddles between the first pixel unit and the second pixel unit And extend to the second thin film transistor, and are electrically connected to the source/drain of the second thin film transistor through the second via hole of the second pixel unit;
  • the second branch electrode of the second pixel electrode crosses the scan line between the first pixel unit and the second pixel unit, extends toward the first thin film transistor, and passes through the first
  • the first via hole of the pixel unit is electrically connected with the source/drain of the first thin film transistor.
  • the first branch electrode of the first pixel electrode crosses the scan line and the data line between the first pixel unit and the second pixel unit, extends to the second thin film transistor, and passes through the first pixel unit.
  • the second via holes of the two pixel units are electrically connected to the source/drain of the second thin film transistor; or
  • the second branch electrode of the second pixel electrode crosses the scan line and the data line between the first pixel unit and the second pixel unit, and extends toward the first thin film transistor, and The first via hole of the first pixel unit is electrically connected to the source/drain of the first thin film transistor.
  • the first pixel unit includes a first color resist
  • the second pixel unit includes a second color resist
  • the first color resistance and the second color resistance are one of red color resistance, green color resistance, and blue color resistance.
  • the display panel includes a display area and a non-display area located at the periphery of the display area;
  • the first area of the non-display area is provided with a plurality of the thin film transistors arranged in parallel, the first area is arranged close to the display area, and the first area is parallel to the data line or the scan line of the display area ;
  • the thin film transistor in the first region is electrically connected to the pixel electrode in the adjacent pixel unit.
  • the display area includes a second area
  • the second area is arranged opposite to and parallel to the first area, and the second area is close to the non-display area and far away from the first area;
  • a plurality of the thin film transistors arranged in parallel are arranged in the second area;
  • the thin film transistors in the second region are non-driving thin film transistors.
  • This application also proposes a display module, including a display panel and a polarizer layer and a cover layer on the display panel, wherein:
  • the display panel includes at least two pixel units
  • the pixel unit includes a substrate, a thin film transistor on the substrate, and a pixel electrode on the thin film transistor;
  • the thin film transistor in the same pixel unit is insulated and connected to the pixel electrode in the pixel unit;
  • the thin film transistor in the pixel unit is electrically connected to a pixel electrode in another pixel unit arranged in parallel.
  • the first pixel electrode of the first pixel unit of the at least two pixel units is electrically connected to the second thin film transistor of the second pixel unit of the at least two pixel units;
  • the second pixel electrode of the second pixel unit is electrically connected to the first thin film transistor of the first pixel unit.
  • At least one first branch electrode of the first pixel electrode extends toward the second thin film transistor and is electrically connected to the second thin film transistor;
  • At least one second branch electrode of the second pixel electrode extends toward the first thin film transistor and is electrically connected to the first thin film transistor.
  • the first pixel unit and the second pixel unit are arranged side by side in a first direction or a second direction;
  • the first direction is perpendicular to the second direction.
  • the first branch electrode of the first pixel electrode straddles between the first pixel unit and the second pixel unit And extend to the second thin film transistor, and are electrically connected to the source/drain of the second thin film transistor through the second via hole of the second pixel unit;
  • the second branch electrode of the second pixel electrode crosses the data line between the first pixel unit and the second pixel unit, extends toward the first thin film transistor, and passes through the first pixel unit.
  • the first via hole of the pixel unit is electrically connected with the source/drain of the first thin film transistor.
  • the first branch electrode of the first pixel electrode straddles between the first pixel unit and the second pixel unit And extend to the second thin film transistor, and are electrically connected to the source/drain of the second thin film transistor through the second via hole of the second pixel unit;
  • the second branch electrode of the second pixel electrode crosses the scan line between the first pixel unit and the second pixel unit, extends toward the first thin film transistor, and passes through the first
  • the first via hole of the pixel unit is electrically connected with the source/drain of the first thin film transistor.
  • the first branch electrode of the first pixel electrode crosses the scan line and the data line between the first pixel unit and the second pixel unit, extends to the second thin film transistor, and passes through the first pixel unit.
  • the second via holes of the two pixel units are electrically connected to the source/drain of the second thin film transistor; or
  • the second branch electrode of the second pixel electrode crosses the scan line and the data line between the first pixel unit and the second pixel unit, and extends toward the first thin film transistor, and The first via hole of the first pixel unit is electrically connected to the source/drain of the first thin film transistor.
  • the first pixel unit includes a first color resist
  • the second pixel unit includes a second color resist
  • the first color resistance and the second color resistance are one of red color resistance, green color resistance, and blue color resistance.
  • the display panel includes a display area and a non-display area located at the periphery of the display area;
  • the first area of the non-display area is provided with a plurality of the thin film transistors arranged in parallel, the first area is arranged close to the display area, and the first area is parallel to the data line or the scan line of the display area ;
  • the thin film transistor in the first region is electrically connected to the pixel electrode in the adjacent pixel unit.
  • the display area includes a second area
  • the second area is arranged opposite to and parallel to the first area, and the second area is close to the non-display area and far away from the first area;
  • a plurality of the thin film transistors arranged in parallel are arranged in the second area;
  • the thin film transistors in the second region are non-driving thin film transistors.
  • the present application improves the alignment accuracy of the display panel by extending the pixel electrode in a pixel unit through a region with higher flatness to the thin film transistor in the adjacent pixel unit, thereby eliminating the dark lines on the border of the display panel, and improving the display panel Quality.
  • FIG. 1 is a first enlarged view of a pixel unit of a display panel of this application
  • FIG. 2 is a structural diagram of an array substrate in a display panel of this application.
  • FIG. 3 is a second enlarged view of the pixel unit of the display panel of this application.
  • FIG. 4 is a third enlarged view of the pixel unit of the display panel of this application.
  • FIG. 5 is a fourth enlarged view of the pixel unit of the display panel of this application.
  • FIG. 6 is a top view of the display panel of this application.
  • FIG. 7 is a fifth enlarged view of the pixel unit of the display panel of this application.
  • the embodiment of the present application takes the COA display panel 100 as an example for description.
  • the display panel 100 includes a first substrate, a second substrate, and a liquid crystal layer located between the first substrate and the second substrate.
  • the first substrate is an array substrate
  • the color filter layer is located on the array substrate.
  • FIG. 1 is a first enlarged view of a pixel unit of a display panel of the present application.
  • the display panel 100 includes at least two pixel units 10.
  • each pixel unit 10 includes a substrate 20, a thin film transistor 30 on the substrate 20, and a pixel electrode 40 on the thin film transistor 30.
  • the thin film transistor 30 in the same pixel unit 10 is insulated and connected to the pixel electrode 40 in the pixel unit 10.
  • the thin film transistor 30 in the pixel unit 10 is electrically connected to the pixel electrode 40 in another pixel unit 10 arranged in parallel.
  • FIG. 2 is a structural diagram of an array substrate in a display panel of the present application.
  • the display panel 100 includes at least a first pixel unit 11 and a second pixel unit 12.
  • the first pixel unit 11 and the second pixel unit 12 are arranged adjacent to each other.
  • the first pixel electrode 41 of the first pixel unit 11 in at least two pixel units 10 is electrically connected to the second thin film transistor 32 of the second pixel unit 12 in at least two pixel units 10;
  • the second pixel electrode 42 of the second pixel unit 12 is electrically connected to the first thin film transistor 31 of the first pixel unit 11.
  • the first pixel unit 11 includes a substrate 20, a first thin film transistor 31 on the substrate 20, and a first pixel electrode 41 on the first thin film transistor 31.
  • the second pixel unit 12 includes a substrate 20, a second thin film transistor 32 on the substrate 20, and a second pixel electrode 42 on the second thin film transistor 32.
  • the raw material of the substrate 20 may be one of a glass substrate, a quartz substrate, and a resin substrate.
  • the material of the flexible substrate may be PI (polyimide).
  • the type of the substrate 20 is not specifically limited in this application.
  • the first thin film transistor and the second thin film transistor may be an etch stop layer type, a back channel etch type, a bottom gate thin film transistor type, or a top gate thin film transistor type, etc., which is not specifically limited in this embodiment.
  • the thin film transistor 30 in one pixel unit 10 is electrically connected to the pixel electrode 40 in the adjacent pixel unit 10.
  • the pixel electrode 40 in one pixel unit 10 is electrically connected to the thin film transistor 30 in the adjacent pixel unit 10.
  • At least one first branch electrode 411 of the first pixel electrode 41 extends toward the second thin film transistor 32 and is electrically connected to the second thin film transistor 32;
  • At least one second branch electrode of the second pixel electrode 42 extends toward the first thin film transistor 41 and is electrically connected to the first thin film transistor 41.
  • the first pixel unit 11 and the second pixel unit 12 are arranged side by side in the first direction or the second direction.
  • the first direction is perpendicular to the second direction.
  • FIG. 2 Please refer to FIG. 2.
  • This application takes the bottom gate thin film transistor type as an example for description
  • the first thin film transistor 31 includes a first gate layer 311 formed on the substrate 20, a gate insulating layer 312 formed on the first gate layer 311, and a first gate layer 312 formed on the gate insulating layer 312.
  • the source-drain layer 313 is located on the first source-drain layer 313 to form a first passivation layer 314.
  • the first pixel unit 11 further includes a first color resist unit 315 formed on the first passivation layer 314, and a second passivation unit 315 is formed on the first color resist unit 315.
  • the second thin film transistor 32 includes a second gate layer 411 formed on the substrate 20, a gate insulating layer 312 formed on the second gate layer 411, and a second gate layer 312 formed on the gate insulating layer 312.
  • the source-drain layer 413 is located on the second source-drain layer 413 to form a first passivation layer 314.
  • the second pixel unit 12 further includes a second color resist unit 415 formed on the first passivation layer 314, and a second color resist unit 415 is formed on the second color resist unit 415.
  • the first pixel electrode 41 and the second pixel electrode 42 are formed in the same photomask process, and the first pixel electrode 41 and the second pixel electrode 42 may be transparent electrode layers.
  • the material of the first pixel electrode 41 and the second pixel electrode 42 may be indium tin oxide (ITO).
  • the first thin film transistor 31 is electrically connected to the second pixel electrode 42 of the second thin film transistor 32.
  • the first source and drain layer 313 of the first thin film transistor 31 is electrically connected to the second pixel electrode 42.
  • the second source and drain layer 413 of the second thin film transistor 32 is electrically connected to the first pixel electrode 41.
  • This embodiment is a schematic diagram in this application.
  • the first branch electrode 411 of the first pixel electrode 41 straddles the The data line 50 between the first pixel unit 11 and the second pixel unit 12 extends to the second thin film transistor 32, and passes through the second via 417 of the second thin film transistor 32 and the first The source/drain of the two thin film transistors 32 are electrically connected.
  • the first direction is parallel to the scan line 60.
  • the second branch electrode of the second pixel electrode 42 may cross the data line 50 between the first pixel unit 11 and the second pixel unit 12, and extend toward the The first thin film transistor 31 extends and is electrically connected to the source/drain of the first thin film transistor 31 through the first via 317 of the first thin film transistor 31.
  • FIG. 3 is a second enlarged view of the pixel unit of the display panel of the present application.
  • the first branch electrode 411 of the first pixel electrode 41 straddles the first pixel unit 11 and the The scan line 60 between the second pixel units 12 extends to the second thin film transistor 32, and passes through the second via 417 of the second thin film transistor 32 and the source of the second thin film transistor 32/ The drain is electrically connected.
  • the second direction is parallel to the data line 50.
  • the second branch electrode of the second pixel electrode 42 may cross the scan line 60 between the first pixel unit 11 and the second pixel unit 12 and be directed toward the
  • the first thin film transistor 31 extends and is electrically connected to the source/drain of the first thin film transistor 31 through the first via 317 of the first thin film transistor 31.
  • FIG. 4 is a third enlarged view of the pixel unit of the display panel of the present application.
  • the first branch electrode 411 of the first pixel electrode 41 crosses the scan line 60 and the data line 50 between the first pixel unit 11 and the second pixel unit 12, and connects to the second thin film transistor 32. Extends and is electrically connected to the source/drain of the second thin film transistor 32 through the second via 417 of the second thin film transistor 32.
  • the second branch electrode of the second pixel electrode 42 may cross the scan line 60 and the data line between the first pixel unit 11 and the second pixel unit 12. 50, and extend to the first thin film transistor 31, and are electrically connected to the source/drain of the first thin film transistor 31 through the first via 317 of the first thin film transistor 31.
  • FIG. 5 is a fourth enlarged view of the pixel unit of the display panel of the present application.
  • the first source and drain layer of the first thin film transistor 31 is electrically connected to the second pixel electrode 42.
  • the second source and drain layer of the second thin film transistor 32 is electrically connected to the first pixel electrode 41.
  • At least one other pixel unit 10 can be spaced between the first pixel unit 11 and the second pixel unit 12, which is not specifically limited in this application.
  • the first pixel unit 11 further includes a first color resist unit 315
  • the second pixel unit 12 further includes a second color resist unit 415 .
  • the first color resistance unit 315 and the second color resistance unit 415 are one of red color resistance, green color resistance or blue color resistance.
  • the color resistance units of the first pixel unit 11 and the second pixel unit 12 in FIG. 1 and FIG. 4 are different, as shown in FIG.
  • the color resistance units of the first pixel unit 11 and the second pixel unit 12 have the same color.
  • FIG. 6 is a top view of the display panel of this application.
  • FIG. 7 is a fifth enlarged view of the pixel unit of the display panel of the present application.
  • the display panel 100 includes a display area 300 and a non-display area 200 located at the periphery of the display area 300.
  • the non-display area 200 includes a first area 201 located close to the display area 300.
  • a plurality of the thin film transistors 30 arranged side by side are arranged in the first area 201, and the first area 201 may be parallel to the data line 50 or the scan line 60 of the display area 300.
  • the first area 201 is parallel to the data line 50 of the display area 300 as an example for description.
  • the thin film transistor 30 in the first region 201 is electrically connected to the pixel electrode 40 in the adjacent pixel unit 10.
  • the display area 300 includes a second area 301 located close to the non-display area 200.
  • the second area 301 is opposite to the first area 201 and arranged in parallel, and the second area 301 is far away from the first area 201.
  • a plurality of the thin film transistors 30 arranged in parallel are arranged in the second region 301.
  • the thin film transistor 30 in the second region 301 is a non-driving thin film transistor 30.
  • the thin film transistor 30 in the first region 201 in this embodiment is used to drive and electrically connect with the pixel electrode 40 in the row/column pixel unit 10 of the display region 300, that is, the thin film transistor in the first region 201 30 is used to drive the TFT. Therefore, the thin film transistor 30 in the second region 301 opposite to it is not electrically connected to the pixel electrode 40 of the corresponding pixel unit 10, and the thin film transistor in the second region 301 is an invalid TFT.
  • This application extends the electrode lead of the pixel electrode in a certain pixel unit to the adjacent pixel unit, and is electrically connected to the corresponding thin film transistor across the routing area of the flat data line or scan line, thereby improving the alignment of the display panel
  • the accuracy eliminates the dark lines on the border of the display panel and improves the quality of the display panel.
  • This application also proposes a display module, which includes the above-mentioned display panel and a polarizer layer and a cover layer on the display panel.
  • the working principle of the display module is the same or similar to that of the display panel, and will not be repeated in this application.
  • the present application provides a display panel and a display module.
  • the display panel includes at least two pixel units.
  • the pixel units include a substrate, a thin film transistor on the substrate, and a pixel on the thin film transistor. Electrode; the thin film transistor in the same pixel unit is insulated and connected to the pixel electrode in the pixel unit; the thin film transistor in the pixel unit is electrically connected to the pixel electrode in another pixel unit arranged in parallel sexual connection.
  • the present application improves the alignment accuracy of the display panel by extending the pixel electrode in a pixel unit through a region with higher flatness to the thin film transistor in the adjacent pixel unit, thereby eliminating the dark lines on the border of the display panel, and improving the display panel Quality.

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Abstract

一种显示面板（100）及显示模组，该显示面板（100）包括至少两像素单元（10），该像素单元（10）包括衬底（20）、位于该衬底（20）上的薄膜晶体管（30）、及位于该薄膜晶体管（30）上的像素电极（40）；同一该像素单元（10）内的该薄膜晶体管（30）与该像素单元（10）内的该像素电极（40）绝缘连接；该像素单元（10）内的该薄膜晶体管（30）与并列设置的另一像素单元（10）内的像素电极（40）电性连接。

Description

显示面板及显示模组 技术领域
本申请涉及显示领域，特别涉及一种显示面板及显示模组。
 背景技术
现有技术中，COA（ColorFilter on Array）显示面板为将彩色滤光层设置于阵列基板上，避免了常规阵列基板与彩膜基板产生的对位误差，提高了显示面板的对位精度。但是，色阻层的设置导致阵列基板的表面平坦度较差，导致配向不良而出现边界暗纹等技术问题，降低产品的良率。
因此，目前亟需一种显示面板以解决上述技术问题。
 技术问题
本申请提供了一种显示面板及显示模组，以解决现有显示面板边界出现暗纹等技术问题。
 技术解决方案
本申请提供一种显示面板，其包括至少两像素单元；
所述像素单元包括衬底、位于所述衬底上的薄膜晶体管、及位于所述薄膜晶体管上的像素电极；
其中，同一所述像素单元内的所述薄膜晶体管与所述像素单元内的所述像素电极绝缘连接；
所述像素单元内的所述薄膜晶体管与并列设置的另一像素单元内的像素电极电性连接。
在本申请的显示面板中，至少两所述像素单元中的第一像素单元的第一像素电极与至少两所述像素单元中的第二像素单元的第二薄膜晶体管电连接；或者
所述第二像素单元的第二像素电极与所述第一像素单元的第一薄膜晶体管电连接。
在本申请的显示面板中，
所述第一像素电极的至少一第一分支电极朝向所述第二薄膜晶体管延伸并与所述第二薄膜晶体管电连接；或者
所述第二像素电极的至少一第二分支电极朝向所述第一薄膜晶体管延伸并与所述第一薄膜晶体管电连接。
在本申请的显示面板中，
所述第一像素单元与所述第二像素单元在第一方向或第二方向上并列设置；
其中，所述第一方向与所述第二方向垂直。
在本申请的显示面板中，
当所述第一像素单元与所述第二像素单元在第一方向上并列设置时，所述第一像素电极的第一分支电极跨过所述第一像素单元与所述第二像素单元之间的数据线，并向所述第二薄膜晶体管延伸，以及通过所述第二像素单元的第二过孔与所述第二薄膜晶体管的源极/漏极电连接；或者
所述第二像素电极的第二分支电极跨过所述第一像素单元与所述第二像素单元之间的所述数据线，并向所述第一薄膜晶体管延伸，以及通过所述第一像素单元的第一过孔与所述第一薄膜晶体管的源极/漏极电连接。
在本申请的显示面板中，
当所述第一像素单元与所述第二像素单元在第二方向上并列设置时，所述第一像素电极的第一分支电极跨过所述第一像素单元与所述第二像素单元之间的扫描线，并向所述第二薄膜晶体管延伸，以及通过所述第二像素单元的第二过孔与所述第二薄膜晶体管的源极/漏极电连接；或者
所述第二像素电极的第二分支电极跨过所述第一像素单元与所述第二像素单元之间的所述扫描线，并向所述第一薄膜晶体管延伸，以及通过所述第一像素单元的第一过孔与所述第一薄膜晶体管的源极/漏极电连接。
在本申请的显示面板中，
所述第一像素电极的第一分支电极跨过所述第一像素单元与所述第二像素单元之间的扫描线及数据线，并向所述第二薄膜晶体管延伸，以及通过所述第二像素单元的第二过孔与所述第二薄膜晶体管的源极/漏极电连接；或者
所述第二像素电极的第二分支电极跨过所述第一像素单元与所述第二像素单元之间的所述扫描线及所述数据线，并向所述第一薄膜晶体管延伸，以及通过所述第一像素单元的第一过孔与所述第一薄膜晶体管的源极/漏极电连接。
在本申请的显示面板中，
所述第一像素单元包括第一色阻；
所述第二像素单元包括第二色阻；
所述第一色阻与所述第二色阻为红色色阻、绿色色阻、蓝色色阻中的一种。
在本申请的显示面板中，所述显示面板包括显示区域和位于所述显示区域外围的非显示区域；
所述非显示区域的第一区设置有多个并列设置的所述薄膜晶体管，所述第一区靠近所述显示区域设置，所述第一区与所述显示区域的数据线或扫描线平行；
所述第一区内的所述薄膜晶体管与相邻所述像素单元中的所述像素电极电连接。
在本申请的显示面板中，所述显示区域包括第二区；
所述第二区与所述第一区相对且平行设置，所述第二区靠近所述非显示区域且远离所述第一区；
所述第二区内设置有多个并列设置的所述薄膜晶体管；
所述第二区内的所述薄膜晶体管为非驱动薄膜晶体管。
本申请还提出了一种显示模组，包括显示面板及位于所述显示面板上的偏光片层及盖板层，其中，
所述显示面板包括至少两像素单元；
所述像素单元包括衬底、位于所述衬底上的薄膜晶体管、及位于所述薄膜晶体管上的像素电极；
其中，同一所述像素单元内的所述薄膜晶体管与所述像素单元内的所述像素电极绝缘连接；
所述像素单元内的所述薄膜晶体管与并列设置的另一像素单元内的像素电极电性连接。
在本申请的显示模组中，至少两所述像素单元中的第一像素单元的第一像素电极与至少两所述像素单元中的第二像素单元的第二薄膜晶体管电连接；或者
所述第二像素单元的第二像素电极与所述第一像素单元的第一薄膜晶体管电连接。
在本申请的显示模组中，
所述第一像素电极的至少一第一分支电极朝向所述第二薄膜晶体管延伸并与所述第二薄膜晶体管电连接；或者
所述第二像素电极的至少一第二分支电极朝向所述第一薄膜晶体管延伸并与所述第一薄膜晶体管电连接。
在本申请的显示模组中，
所述第一像素单元与所述第二像素单元在第一方向或第二方向上并列设置；
其中，所述第一方向与所述第二方向垂直。
在本申请的显示模组中，
当所述第一像素单元与所述第二像素单元在第一方向上并列设置时，所述第一像素电极的第一分支电极跨过所述第一像素单元与所述第二像素单元之间的数据线，并向所述第二薄膜晶体管延伸，以及通过所述第二像素单元的第二过孔与所述第二薄膜晶体管的源极/漏极电连接；或者
所述第二像素电极的第二分支电极跨过所述第一像素单元与所述第二像素单元之间的所述数据线，并向所述第一薄膜晶体管延伸，以及通过所述第一像素单元的第一过孔与所述第一薄膜晶体管的源极/漏极电连接。
在本申请的显示模组中，
当所述第一像素单元与所述第二像素单元在第二方向上并列设置时，所述第一像素电极的第一分支电极跨过所述第一像素单元与所述第二像素单元之间的扫描线，并向所述第二薄膜晶体管延伸，以及通过所述第二像素单元的第二过孔与所述第二薄膜晶体管的源极/漏极电连接；或者
所述第二像素电极的第二分支电极跨过所述第一像素单元与所述第二像素单元之间的所述扫描线，并向所述第一薄膜晶体管延伸，以及通过所述第一像素单元的第一过孔与所述第一薄膜晶体管的源极/漏极电连接。
在本申请的显示模组中，
所述第一像素电极的第一分支电极跨过所述第一像素单元与所述第二像素单元之间的扫描线及数据线，并向所述第二薄膜晶体管延伸，以及通过所述第二像素单元的第二过孔与所述第二薄膜晶体管的源极/漏极电连接；或者
所述第二像素电极的第二分支电极跨过所述第一像素单元与所述第二像素单元之间的所述扫描线及所述数据线，并向所述第一薄膜晶体管延伸，以及通过所述第一像素单元的第一过孔与所述第一薄膜晶体管的源极/漏极电连接。
在本申请的显示模组中，
所述第一像素单元包括第一色阻；
所述第二像素单元包括第二色阻；
所述第一色阻与所述第二色阻为红色色阻、绿色色阻、蓝色色阻中的一种。
在本申请的显示模组中，所述显示面板包括显示区域和位于所述显示区域外围的非显示区域；
所述非显示区域的第一区设置有多个并列设置的所述薄膜晶体管，所述第一区靠近所述显示区域设置，所述第一区与所述显示区域的数据线或扫描线平行；
所述第一区内的所述薄膜晶体管与相邻所述像素单元中的所述像素电极电连接。
在本申请的显示模组中，
所述显示区域包括第二区；
所述第二区与所述第一区相对且平行设置，所述第二区靠近所述非显示区域且远离所述第一区；
所述第二区内设置有多个并列设置的所述薄膜晶体管；
所述第二区内的所述薄膜晶体管为非驱动薄膜晶体管。
 有益效果
本申请通过将一像素单元内的像素电极经过平坦度较高的区域延伸至相邻像素单元内的薄膜晶体管，改善了显示面板的配向准确度，消除了显示面板边界暗纹，提高了显示面板的品质。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请显示面板像素单元的第一种放大图；
图2为本申请显示面板中阵列基板的结构图；
图3为本申请显示面板像素单元的第二种放大图；
图4为本申请显示面板像素单元的第三种放大图；
图5为本申请显示面板像素单元的第四种放大图；
图6为本申请显示面板的俯视图；
图7为本申请显示面板像素单元的第五种放大图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请的实施例以COA显示面板100为例进行说明。
所述显示面板100包括第一基板、第二基板、及位于所述第一基板与所述第二基板之间的液晶层。
在本实施例中，所述第一基板为阵列基板，所述彩膜层位于所述阵列基板上。
请参阅图1，图1为本申请显示面板像素单元的第一种放大图。
所述显示面板100包括至少两像素单元10。
在本实施例中，每一所述像素单元10包括衬底20、位于所述衬底20上的薄膜晶体管30、及位于所述薄膜晶体管30上的像素电极40。
其中，同一像素单元10内的所述薄膜晶体管30与所述像素单元10内的所述像素电极40绝缘连接。所述像素单元10内的所述薄膜晶体管30与并列设置的另一像素单元10内的像素电极40电性连接。
请参阅图2，图2为本申请显示面板中阵列基板的结构图。
所述显示面板100至少包括第一像素单元11和第二像素单元12。
在本实施例中，所述第一像素单元11与所述第二像素单元12相邻设置。
在本实施例中，至少两所述像素单元10中的第一像素单元11的第一像素电极41与至少两所述像素单元10中的第二像素单元12的第二薄膜晶体管32电连接；或者
所述第二像素单元12的第二像素电极42与所述第一像素单元11的第一薄膜晶体管31电连接。
请参阅图2，所述第一像素单元11包括衬底20、位于所述衬底20上的第一薄膜晶体管31、位于所述第一薄膜晶体管31上的第一像素电极41。所述第二像素单元12包括衬底20、位于所述衬底20上的第二薄膜晶体管32、位于所述第二薄膜晶体管32上的第二像素电极42。
在本实施例中，所述衬底20的原材料可以为玻璃基板、石英基板、树脂基板等中的一种。当所述衬底20为柔性基板时，所述柔性基板的材料可以为PI（聚酰亚胺）。所述衬底20的类型本申请不作具体的限制。
所述第一薄膜晶体管及所述第二薄膜晶体管可以为蚀刻阻挡层型、背沟道蚀刻型、底栅薄膜晶体管型或顶栅薄膜晶体管型等，本实施例具体没有限制。
在本实施例中，一所述像素单元10内的所述薄膜晶体管30与其相邻所述像素单元10内的像素电极40电连接。或者，一所述像素单元10内的所述像素电极40与其相邻所述像素单元10内的薄膜晶体管30电连接。
在本实施例中，所述第一像素电极41的至少一第一分支电极411朝向所述第二薄膜晶体管32延伸并与所述第二薄膜晶体管32电连接；或者
所述第二像素电极42的至少一第二分支电极朝向所述第一薄膜晶体管41延伸并与所述第一薄膜晶体管41电连接。
在本实施例中，所述第一像素单元11与所述第二像素单元12在第一方向或第二方向上并列设置。
其中，所述第一方向与所述第二方向垂直。
请参阅图2，本申请以底栅薄膜晶体管型为例进行说明
所述第一薄膜晶体管31包括位于所述衬底20上形成第一栅极层311、位于所述第一栅极层311上形成栅绝缘层312、位于所述栅绝缘层312上形成第一源漏极层313、位于所述第一源漏极层313上形成第一钝化层314。
由于所述阵列基板为COA基板，所述第一像素单元11还包括位于所述第一钝化层314上形成第一色阻单元315、位于所述第一色阻单元315上形成第二钝化层316、位于所述第二钝化层316上的第一像素电极41。
所述第二薄膜晶体管32包括位于所述衬底20上形成第二栅极层411、位于所述第二栅极层411上形成栅绝缘层312、位于所述栅绝缘层312上形成第二源漏极层413、位于所述第二源漏极层413上形成第一钝化层314。
由于所述阵列基板为COA基板，所述第二像素单元12还包括位于所述第一钝化层314上形成第二色阻单元415、位于所述第二色阻单元415上形成第二钝化层316、位于所述第二钝化层316上的第二像素电极42。
在本实施例中，所述第一像素电极41及所述第二像素电极42在同一道光罩工艺中形成，所述第一像素电极41及所述第二像素电极42可以为透明电极层。所述第一像素电极41及所述第二像素电极42的材料可以为氧化铟锡（ITO）。
在本实施例中，所述第一薄膜晶体管31与所述第二薄膜晶体管32的所述第二像素电极42电连接。
请参阅图2，所述第一薄膜晶体管31的第一源漏极层313与所述第二像素电极42电连接。
或者，所述第二薄膜晶体管32的第二源漏极层413与所述第一像素电极41电连接，此实施例本申请为作示意图。
请参阅图1和图2，当所述第一像素单元11与所述第二像素单元12在第一方向上并列设置时，所述第一像素电极41的第一分支电极411跨过所述第一像素单元11与所述第二像素单元12之间的数据线50，并向所述第二薄膜晶体管32延伸，以及通过所述第二薄膜晶体管32的第二过孔417与所述第二薄膜晶体管32的源极/漏极电连接。
在本实施例中，所述第一方向与扫描线60平行。
另外，本实施例还可以为所述第二像素电极42的第二分支电极跨过所述第一像素单元11与所述第二像素单元12之间的所述数据线50，并向所述第一薄膜晶体管31延伸，以及通过所述第一薄膜晶体管31的第一过孔317与所述第一薄膜晶体管31的源极/漏极电连接。
请参阅图3，图3为本申请显示面板像素单元的第二种放大图。
当所述第一像素单元11与所述第二像素单元12在第二方向上并列设置时，所述第一像素电极41的第一分支电极411跨过所述第一像素单元11与所述第二像素单元12之间的扫描线60，并向所述第二薄膜晶体管32延伸，以及通过所述第二薄膜晶体管32的第二过孔417与所述第二薄膜晶体管32的源极/漏极电连接。
在本实施例中，所述第二方向与数据线50平行。
另外，本实施例还可以为所述第二像素电极42的第二分支电极跨过所述第一像素单元11与所述第二像素单元12之间的所述扫描线60，并向所述第一薄膜晶体管31延伸，以及通过所述第一薄膜晶体管31的第一过孔317与所述第一薄膜晶体管31的源极/漏极电连接。
请参阅图4，图4为本申请显示面板像素单元的第三种放大图。
所述第一像素电极41的第一分支电极411跨过所述第一像素单元11与所述第二像素单元12之间的扫描线60及数据线50，并向所述第二薄膜晶体管32延伸，以及通过所述第二薄膜晶体管32的第二过孔417与所述第二薄膜晶体管32的源极/漏极电连接。
另外，本实施例还可以为所述第二像素电极42的第二分支电极跨过所述第一像素单元11与所述第二像素单元12之间的所述扫描线60及所述数据线50，并向所述第一薄膜晶体管31延伸，以及通过所述第一薄膜晶体管31的第一过孔317与所述第一薄膜晶体管31的源极/漏极电连接。
请参阅图5，图5为本申请显示面板像素单元的第四种放大图。
在本实施例中，所述第一薄膜晶体管31的第一源漏极层与所述第二像素电极42电连接。或者所述第二薄膜晶体管32的第二源漏极层与所述第一像素电极41电连接。
所述第一像素单元11与所述第二像素单元12之间可以间隔至少一个其他像素单元10，本申请不作具体的限制。
在上述实施例中，由于所述显示面板100为COA显示面板100，因此所述第一像素单元11还包括第一色阻单元315，所述第二像素单元12还包括第二色阻单元415。所述第一色阻单元315与所述第二色阻415单元为红色色阻、绿色色阻或蓝色色阻中的一种。
例如，若上述实施例显示面板100的像素排列为标准的RGB排列，则图1和图4中所述第一像素单元11和所述第二像素单元12的色阻单元颜色不同，图3中的所述第一像素单元11和所述第二像素单元12的色阻单元颜色相同。
请参阅图6，图6为本申请显示面板的俯视图。
请参阅图7，图7为本申请显示面板像素单元的第五种放大图。
所述显示面板100包括显示区域300和位于所述显示区域300外围的非显示区域200。
所述非显示区域200包括靠近所述显示区域300设置的第一区201。
所述第一区201内设置有多个并列设置的所述薄膜晶体管30，所述第一区201可以与所述显示区域300的数据线50或扫描线60平行。
在本实施例以所述第一区201与所述显示区域300的数据线50平行为例进行说明。
所述第一区201内的所述薄膜晶体管30与相邻的所述像素单元10中的所述像素电极40电连接。
所述显示区域300包括靠近所述非显示区域200设置的第二区301。
所述第二区301与所述第一区201相对且平行设置，所述第二区301远离所述第一区201。
所述第二区301内设置有多个并列设置的所述薄膜晶体管30。
在本实施例中，所述第二区301内的所述薄膜晶体管30为非驱动薄膜晶体管30。
由于本实施例中的所述第一区201内的薄膜晶体管30用于驱动与显示区域300的一行/列像素单元10中的像素电极40电连接，即所述第一区201内的薄膜晶体管30用于驱动TFT。因此与之相对的所述第二区301内的薄膜晶体管30未与相应的像素单元10的像素电极40电连接，所述第二区301内的薄膜晶体管为无效TFT。
本申请将某一像素单元中的像素电极的电极引线向与之相邻像素单元延伸，跨过平坦的数据线或扫描线的走线区与对应的薄膜晶体管电连接，改善了显示面板的配向准确度，消除了显示面板边界暗纹，提高了显示面板的品质。
本申请仅以COA面板为例进行说明，本申请的技术方案适用于任意液晶显示面板。
本申请还提出了一种显示模组，所述显示模组包括上述显示面板及位于所述显示面板上的偏光片层及盖板层。所述显示模组的工作原理与所述显示面板的相同或相似，本申请不在赘述。
本申请提供了一种显示面板及显示模组，所述显示面板包括至少两像素单元，所述像素单元包括衬底、位于所述衬底上的薄膜晶体管、及位于所述薄膜晶体管上的像素电极；同一所述像素单元内的所述薄膜晶体管与所述像素单元内的所述像素电极绝缘连接；所述像素单元内的所述薄膜晶体管与并列设置的另一像素单元内的像素电极电性连接。本申请通过将一像素单元内的像素电极经过平坦度较高的区域延伸至相邻像素单元内的薄膜晶体管，改善了显示面板的配向准确度，消除了显示面板边界暗纹，提高了显示面板的品质。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其包括至少两像素单元；
    所述像素单元包括衬底、位于所述衬底上的薄膜晶体管、及位于所述薄膜晶体管上的像素电极；
    其中，同一所述像素单元内的所述薄膜晶体管与所述像素单元内的所述像素电极绝缘连接；
    所述像素单元内的所述薄膜晶体管与并列设置的另一像素单元内的像素电极电性连接。
  2. 根据权利要求1所述的显示面板，其中，至少两所述像素单元中的第一像素单元的第一像素电极与至少两所述像素单元中的第二像素单元的第二薄膜晶体管电连接；或者
    所述第二像素单元的第二像素电极与所述第一像素单元的第一薄膜晶体管电连接。
  3. 根据权利要求2所述的显示面板，其中，
    所述第一像素电极的至少一第一分支电极朝向所述第二薄膜晶体管延伸并与所述第二薄膜晶体管电连接；或者
    所述第二像素电极的至少一第二分支电极朝向所述第一薄膜晶体管延伸并与所述第一薄膜晶体管电连接。
  4. 根据权利要求3所述的显示面板，其中，
    所述第一像素单元与所述第二像素单元在第一方向或第二方向上并列设置；
    其中，所述第一方向与所述第二方向垂直。
  5. 根据权利要求4所述的显示面板，其中，
    当所述第一像素单元与所述第二像素单元在第一方向上并列设置时，所述第一像素电极的第一分支电极跨过所述第一像素单元与所述第二像素单元之间的数据线，并向所述第二薄膜晶体管延伸，以及通过所述第二像素单元的第二过孔与所述第二薄膜晶体管的源极/漏极电连接；或者
    所述第二像素电极的第二分支电极跨过所述第一像素单元与所述第二像素单元之间的所述数据线，并向所述第一薄膜晶体管延伸，以及通过所述第一像素单元的第一过孔与所述第一薄膜晶体管的源极/漏极电连接。
  6. 根据权利要求3所述的显示面板，其中，
    当所述第一像素单元与所述第二像素单元在第二方向上并列设置时，所述第一像素电极的第一分支电极跨过所述第一像素单元与所述第二像素单元之间的扫描线，并向所述第二薄膜晶体管延伸，以及通过所述第二像素单元的第二过孔与所述第二薄膜晶体管的源极/漏极电连接；或者
    所述第二像素电极的第二分支电极跨过所述第一像素单元与所述第二像素单元之间的所述扫描线，并向所述第一薄膜晶体管延伸，以及通过所述第一像素单元的第一过孔与所述第一薄膜晶体管的源极/漏极电连接。
  7. 根据权利要求3所述的显示面板，其中，
    所述第一像素电极的第一分支电极跨过所述第一像素单元与所述第二像素单元之间的扫描线及数据线，并向所述第二薄膜晶体管延伸，以及通过所述第二像素单元的第二过孔与所述第二薄膜晶体管的源极/漏极电连接；或者
    所述第二像素电极的第二分支电极跨过所述第一像素单元与所述第二像素单元之间的所述扫描线及所述数据线，并向所述第一薄膜晶体管延伸，以及通过所述第一像素单元的第一过孔与所述第一薄膜晶体管的源极/漏极电连接。
  8. 根据权利要求3所述的显示面板，其中，
    所述第一像素单元包括第一色阻；
    所述第二像素单元包括第二色阻；
    所述第一色阻与所述第二色阻为红色色阻、绿色色阻、蓝色色阻中的一种。
  9. 根据权利要求1所述的显示面板，其中，所述显示面板包括显示区域和位于所述显示区域外围的非显示区域；
    所述非显示区域的第一区设置有多个并列设置的所述薄膜晶体管，所述第一区靠近所述显示区域设置，所述第一区与所述显示区域的数据线或扫描线平行；
    所述第一区内的所述薄膜晶体管与相邻所述像素单元中的所述像素电极电连接。
  10. 根据权利要求9所述的显示面板，其中，
    所述显示区域包括第二区；
    所述第二区与所述第一区相对且平行设置，所述第二区靠近所述非显示区域且远离所述第一区；
    所述第二区内设置有多个并列设置的所述薄膜晶体管；
    所述第二区内的所述薄膜晶体管为非驱动薄膜晶体管。
  11. 一种显示模组，包括显示面板及位于所述显示面板上的偏光片层及盖板层，其中，
    所述显示面板包括至少两像素单元；
    所述像素单元包括衬底、位于所述衬底上的薄膜晶体管、及位于所述薄膜晶体管上的像素电极；
    其中，同一所述像素单元内的所述薄膜晶体管与所述像素单元内的所述像素电极绝缘连接；
    所述像素单元内的所述薄膜晶体管与并列设置的另一像素单元内的像素电极电性连接。
  12. 根据权利要求11所述的显示模组，其中，至少两所述像素单元中的第一像素单元的第一像素电极与至少两所述像素单元中的第二像素单元的第二薄膜晶体管电连接；或者
    所述第二像素单元的第二像素电极与所述第一像素单元的第一薄膜晶体管电连接。
  13. 根据权利要求12所述的显示模组，其中，
    所述第一像素电极的至少一第一分支电极朝向所述第二薄膜晶体管延伸并与所述第二薄膜晶体管电连接；或者
    所述第二像素电极的至少一第二分支电极朝向所述第一薄膜晶体管延伸并与所述第一薄膜晶体管电连接。
  14. 根据权利要1求3所述的显示模组，其中，
    所述第一像素单元与所述第二像素单元在第一方向或第二方向上并列设置；
    其中，所述第一方向与所述第二方向垂直。
  15. 根据权利要求14所述的显示模组，其中，
    当所述第一像素单元与所述第二像素单元在第一方向上并列设置时，所述第一像素电极的第一分支电极跨过所述第一像素单元与所述第二像素单元之间的数据线，并向所述第二薄膜晶体管延伸，以及通过所述第二像素单元的第二过孔与所述第二薄膜晶体管的源极/漏极电连接；或者
    所述第二像素电极的第二分支电极跨过所述第一像素单元与所述第二像素单元之间的所述数据线，并向所述第一薄膜晶体管延伸，以及通过所述第一像素单元的第一过孔与所述第一薄膜晶体管的源极/漏极电连接。
  16. 根据权利要求13所述的显示模组，其中，
    当所述第一像素单元与所述第二像素单元在第二方向上并列设置时，所述第一像素电极的第一分支电极跨过所述第一像素单元与所述第二像素单元之间的扫描线，并向所述第二薄膜晶体管延伸，以及通过所述第二像素单元的第二过孔与所述第二薄膜晶体管的源极/漏极电连接；或者
    所述第二像素电极的第二分支电极跨过所述第一像素单元与所述第二像素单元之间的所述扫描线，并向所述第一薄膜晶体管延伸，以及通过所述第一像素单元的第一过孔与所述第一薄膜晶体管的源极/漏极电连接。
  17. 根据权利要求13所述的显示模组，其中，
    所述第一像素电极的第一分支电极跨过所述第一像素单元与所述第二像素单元之间的扫描线及数据线，并向所述第二薄膜晶体管延伸，以及通过所述第二像素单元的第二过孔与所述第二薄膜晶体管的源极/漏极电连接；或者
    所述第二像素电极的第二分支电极跨过所述第一像素单元与所述第二像素单元之间的所述扫描线及所述数据线，并向所述第一薄膜晶体管延伸，以及通过所述第一像素单元的第一过孔与所述第一薄膜晶体管的源极/漏极电连接。
  18. 根据权利要求13所述的显示模组，其中，
    所述第一像素单元包括第一色阻；
    所述第二像素单元包括第二色阻；
    所述第一色阻与所述第二色阻为红色色阻、绿色色阻、蓝色色阻中的一种。
  19. 根据权利要求11所述的显示模组，其中，所述显示面板包括显示区域和位于所述显示区域外围的非显示区域；
    所述非显示区域的第一区设置有多个并列设置的所述薄膜晶体管，所述第一区靠近所述显示区域设置，所述第一区与所述显示区域的数据线或扫描线平行；
    所述第一区内的所述薄膜晶体管与相邻所述像素单元中的所述像素电极电连接。
  20. 根据权利要求19所述的显示模组，其中，
    所述显示区域包括第二区；
    所述第二区与所述第一区相对且平行设置，所述第二区靠近所述非显示区域且远离所述第一区；
    所述第二区内设置有多个并列设置的所述薄膜晶体管；
    所述第二区内的所述薄膜晶体管为非驱动薄膜晶体管。
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