WO2003096426A1 - Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods - Google Patents
Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods Download PDFInfo
- Publication number
- WO2003096426A1 WO2003096426A1 PCT/JP2003/005783 JP0305783W WO03096426A1 WO 2003096426 A1 WO2003096426 A1 WO 2003096426A1 JP 0305783 W JP0305783 W JP 0305783W WO 03096426 A1 WO03096426 A1 WO 03096426A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- manufacturing
- semiconductor substrate
- semiconductor device
- semiconductor
- substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 7
- 238000004519 manufacturing process Methods 0.000 title abstract 6
- 239000000758 substrate Substances 0.000 title abstract 6
- 238000000034 method Methods 0.000 title abstract 3
- 150000002500 ions Chemical class 0.000 abstract 2
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 239000011800 void material Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/513,507 US7605443B2 (en) | 2002-05-08 | 2003-05-08 | Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods |
AU2003235902A AU2003235902A1 (en) | 2002-05-08 | 2003-05-08 | Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods |
EP03721079A EP1513198A4 (en) | 2002-05-08 | 2003-05-08 | METHODS OF MANUFACTURING A SUBSTRATE AND A SEMICONDUCTOR DEVICE, SUBSTRATE, AND SEMICONDUCTOR DEVICE PRODUCED USING THE SAME |
KR1020047018010A KR100712572B1 (ko) | 2002-05-08 | 2003-05-08 | 반도체 기판의 제조 방법 및 반도체 장치의 제조 방법과그 방법에 의해 제조된 반도체 기판 및 반도체 장치 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002133090A JP4277481B2 (ja) | 2002-05-08 | 2002-05-08 | 半導体基板の製造方法、半導体装置の製造方法 |
JP2002-133090 | 2002-05-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003096426A1 true WO2003096426A1 (en) | 2003-11-20 |
Family
ID=29416659
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/005783 WO2003096426A1 (en) | 2002-05-08 | 2003-05-08 | Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods |
Country Status (7)
Country | Link |
---|---|
US (1) | US7605443B2 (ja) |
EP (1) | EP1513198A4 (ja) |
JP (1) | JP4277481B2 (ja) |
KR (1) | KR100712572B1 (ja) |
CN (1) | CN100355076C (ja) |
AU (1) | AU2003235902A1 (ja) |
WO (1) | WO2003096426A1 (ja) |
Cited By (2)
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US7309640B2 (en) | 2004-04-21 | 2007-12-18 | Stmicroelectronics Sa | Method of fabricating an integrated circuit including hollow isolating trenches and corresponding integrated circuit |
US10950726B2 (en) | 2016-04-25 | 2021-03-16 | Sony Corporation | Semiconductor device, CMOS circuit, and electronic apparatus with stress in channel region |
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JP4031329B2 (ja) | 2002-09-19 | 2008-01-09 | 株式会社東芝 | 半導体装置及びその製造方法 |
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KR100925136B1 (ko) * | 2004-02-19 | 2009-11-05 | 인터내셔널 비지네스 머신즈 코포레이션 | 다공성 Si 엔지니어링에 의한 패터닝된실리콘-온-인슐레이터(SOI)/실리콘-온-낫싱 (SON)복합 구조물의 형성 |
WO2005083775A1 (en) * | 2004-02-19 | 2005-09-09 | International Business Machines Corporation | FORMATION OF PATTERNED SILICON-ON-INSULATOR (SOI)/SILICON-ON-NOTHING (SON) COMPOSITE STRUCTURE BY POROUS Si ENGINEERING |
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FR2887074A1 (fr) * | 2005-06-09 | 2006-12-15 | St Microelectronics Crolles 2 | Formation d'un masque sur un circuit electronique integre |
FR2887075B1 (fr) * | 2005-06-09 | 2007-10-12 | St Microelectronics Crolles 2 | Realisation de deux elements superposes au sein d'un circuit electronique integre |
JP2007027232A (ja) | 2005-07-13 | 2007-02-01 | Seiko Epson Corp | 半導体装置及びその製造方法 |
WO2008051216A2 (en) * | 2005-10-25 | 2008-05-02 | The Curators Of The University Of Missouri | Micro-scale power source |
DE102006025673B9 (de) | 2005-10-28 | 2010-12-16 | Infineon Technologies Ag | Rechenwerk zum Reduzieren einer Eingabe-Zahl bezüglich eines Moduls |
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US7557002B2 (en) * | 2006-08-18 | 2009-07-07 | Micron Technology, Inc. | Methods of forming transistor devices |
US7989322B2 (en) * | 2007-02-07 | 2011-08-02 | Micron Technology, Inc. | Methods of forming transistors |
US20080203484A1 (en) * | 2007-02-23 | 2008-08-28 | Infineon Technologies Ag | Field effect transistor arrangement and method of producing a field effect transistor arrangement |
JP4455618B2 (ja) * | 2007-06-26 | 2010-04-21 | 株式会社東芝 | 半導体装置の製造方法 |
US8106468B2 (en) * | 2008-06-20 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for fabricating silicon-on-nothing MOSFETs |
US7999300B2 (en) * | 2009-01-28 | 2011-08-16 | Globalfoundries Singapore Pte. Ltd. | Memory cell structure and method for fabrication thereof |
FR2942073B1 (fr) * | 2009-02-10 | 2011-04-29 | Soitec Silicon On Insulator | Procede de realisation d'une couche de cavites |
CN102339754B (zh) * | 2010-07-22 | 2014-08-20 | 中国科学院上海微系统与信息技术研究所 | 一种son结构mosfet的制备方法 |
US8674472B2 (en) * | 2010-08-10 | 2014-03-18 | International Business Machines Corporation | Low harmonic RF switch in SOI |
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Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61128542A (ja) * | 1984-11-27 | 1986-06-16 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
WO1987004860A1 (en) * | 1986-02-07 | 1987-08-13 | Motorola, Inc. | Partially dielectrically isolated semiconductor devices |
JPS63278375A (ja) * | 1987-05-11 | 1988-11-16 | Nec Corp | 半導体集積回路装置 |
JPH07169830A (ja) * | 1993-12-14 | 1995-07-04 | Oki Electric Ind Co Ltd | 誘電体分離基板の製造方法 |
JPH11260751A (ja) * | 1998-03-11 | 1999-09-24 | Seiko Epson Corp | 半導体装置およびその製造方法 |
FR2797347A1 (fr) | 1999-08-04 | 2001-02-09 | Commissariat Energie Atomique | Procede de transfert d'une couche mince comportant une etape de surfragililisation |
JP2001144276A (ja) | 1999-08-31 | 2001-05-25 | Toshiba Corp | 半導体基板およびその製造方法 |
JP2001252555A (ja) * | 2000-03-09 | 2001-09-18 | Hitachi Ltd | 薄膜生成システム |
US6383924B1 (en) * | 2000-12-13 | 2002-05-07 | Micron Technology, Inc. | Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB8725497D0 (en) * | 1987-10-30 | 1987-12-02 | Atomic Energy Authority Uk | Isolation of silicon |
NL8800847A (nl) * | 1988-04-05 | 1989-11-01 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een soi-struktuur. |
US5204282A (en) * | 1988-09-30 | 1993-04-20 | Nippon Soken, Inc. | Semiconductor circuit structure and method for making the same |
JPH04304653A (ja) | 1991-04-02 | 1992-10-28 | Fujitsu Ltd | 半導体装置及びその製造方法 |
DE69430913D1 (de) * | 1994-07-25 | 2002-08-08 | Cons Ric Microelettronica | Verfahren zur lokalen Reduzierung der Ladungsträgerlebensdauer |
JP3062013B2 (ja) * | 1994-08-30 | 2000-07-10 | サンクス株式会社 | 回路接続構造及びデータ伝送装置 |
FR2738671B1 (fr) * | 1995-09-13 | 1997-10-10 | Commissariat Energie Atomique | Procede de fabrication de films minces a materiau semiconducteur |
FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
FR2756973B1 (fr) * | 1996-12-09 | 1999-01-08 | Commissariat Energie Atomique | Procede d'introduction d'une phase gazeuse dans une cavite fermee |
FR2758907B1 (fr) * | 1997-01-27 | 1999-05-07 | Commissariat Energie Atomique | Procede d'obtention d'un film mince, notamment semiconducteur, comportant une zone protegee des ions, et impliquant une etape d'implantation ionique |
FR2767416B1 (fr) * | 1997-08-12 | 1999-10-01 | Commissariat Energie Atomique | Procede de fabrication d'un film mince de materiau solide |
FR2767604B1 (fr) * | 1997-08-19 | 2000-12-01 | Commissariat Energie Atomique | Procede de traitement pour le collage moleculaire et le decollage de deux structures |
FR2773261B1 (fr) * | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2774510B1 (fr) * | 1998-02-02 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats, notamment semi-conducteurs |
JPH11233449A (ja) * | 1998-02-13 | 1999-08-27 | Denso Corp | 半導体基板の製造方法 |
JP3358544B2 (ja) | 1998-07-01 | 2002-12-24 | 日本電気株式会社 | 電界効果型トランジスタの製造方法 |
FR2784795B1 (fr) * | 1998-10-16 | 2000-12-01 | Commissariat Energie Atomique | Structure comportant une couche mince de materiau composee de zones conductrices et de zones isolantes et procede de fabrication d'une telle structure |
EP1043769A1 (en) * | 1999-04-07 | 2000-10-11 | STMicroelectronics S.r.l. | Process for manufacturing a semiconductor material wafer comprising single-crystal regions separated by insulating material regions, in particular for manufacturing intergrated power devices, and wafer thus obtained |
JP4379943B2 (ja) * | 1999-04-07 | 2009-12-09 | 株式会社デンソー | 半導体基板の製造方法および半導体基板製造装置 |
FR2795865B1 (fr) * | 1999-06-30 | 2001-08-17 | Commissariat Energie Atomique | Procede de realisation d'un film mince utilisant une mise sous pression |
FR2809867B1 (fr) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
US7294536B2 (en) * | 2000-07-25 | 2007-11-13 | Stmicroelectronics S.R.L. | Process for manufacturing an SOI wafer by annealing and oxidation of buried channels |
FR2816445B1 (fr) * | 2000-11-06 | 2003-07-25 | Commissariat Energie Atomique | Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible |
EP1244142A1 (en) * | 2001-03-23 | 2002-09-25 | Universite Catholique De Louvain | Fabrication method of SOI semiconductor devices |
DE10131249A1 (de) * | 2001-06-28 | 2002-05-23 | Wacker Siltronic Halbleitermat | Verfahren zur Herstellung eines Films oder einer Schicht aus halbleitendem Material |
JP2003179148A (ja) * | 2001-10-04 | 2003-06-27 | Denso Corp | 半導体基板およびその製造方法 |
US6784076B2 (en) * | 2002-04-08 | 2004-08-31 | Micron Technology, Inc. | Process for making a silicon-on-insulator ledge by implanting ions from silicon source |
JP4277481B2 (ja) * | 2002-05-08 | 2009-06-10 | 日本電気株式会社 | 半導体基板の製造方法、半導体装置の製造方法 |
US6828632B2 (en) * | 2002-07-18 | 2004-12-07 | Micron Technology, Inc. | Stable PD-SOI devices and methods |
JP2004103613A (ja) * | 2002-09-04 | 2004-04-02 | Toshiba Corp | 半導体装置とその製造方法 |
FR2845518B1 (fr) * | 2002-10-07 | 2005-10-14 | Commissariat Energie Atomique | Realisation d'un substrat semiconducteur demontable et obtention d'un element semiconducteur |
EP2280412A3 (en) * | 2002-11-29 | 2011-02-16 | STMicroelectronics S.r.l. | Semiconductor substrate comprising at least a buried insulating cavity |
US6929984B2 (en) * | 2003-07-21 | 2005-08-16 | Micron Technology Inc. | Gettering using voids formed by surface transformation |
JP4004448B2 (ja) * | 2003-09-24 | 2007-11-07 | 富士通株式会社 | 半導体装置およびその製造方法 |
EP1732121A1 (en) * | 2005-06-06 | 2006-12-13 | STMicroelectronics S.r.l. | Process for manufacturing a high-quality SOI wafer |
JP2007165677A (ja) * | 2005-12-15 | 2007-06-28 | Seiko Epson Corp | 半導体基板の製造方法及び半導体装置 |
-
2002
- 2002-05-08 JP JP2002133090A patent/JP4277481B2/ja not_active Expired - Fee Related
-
2003
- 2003-05-08 AU AU2003235902A patent/AU2003235902A1/en not_active Abandoned
- 2003-05-08 WO PCT/JP2003/005783 patent/WO2003096426A1/ja active Application Filing
- 2003-05-08 CN CNB038163977A patent/CN100355076C/zh not_active Expired - Fee Related
- 2003-05-08 EP EP03721079A patent/EP1513198A4/en not_active Withdrawn
- 2003-05-08 US US10/513,507 patent/US7605443B2/en not_active Expired - Fee Related
- 2003-05-08 KR KR1020047018010A patent/KR100712572B1/ko not_active IP Right Cessation
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61128542A (ja) * | 1984-11-27 | 1986-06-16 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
WO1987004860A1 (en) * | 1986-02-07 | 1987-08-13 | Motorola, Inc. | Partially dielectrically isolated semiconductor devices |
JPS63278375A (ja) * | 1987-05-11 | 1988-11-16 | Nec Corp | 半導体集積回路装置 |
JPH07169830A (ja) * | 1993-12-14 | 1995-07-04 | Oki Electric Ind Co Ltd | 誘電体分離基板の製造方法 |
JPH11260751A (ja) * | 1998-03-11 | 1999-09-24 | Seiko Epson Corp | 半導体装置およびその製造方法 |
FR2797347A1 (fr) | 1999-08-04 | 2001-02-09 | Commissariat Energie Atomique | Procede de transfert d'une couche mince comportant une etape de surfragililisation |
JP2001144276A (ja) | 1999-08-31 | 2001-05-25 | Toshiba Corp | 半導体基板およびその製造方法 |
JP2001252555A (ja) * | 2000-03-09 | 2001-09-18 | Hitachi Ltd | 薄膜生成システム |
US6383924B1 (en) * | 2000-12-13 | 2002-05-07 | Micron Technology, Inc. | Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials |
Non-Patent Citations (2)
Title |
---|
ATSUSHI OGURA ET AL.: "Formation of buried oxide layer in Si substrates by oxygen precipitation at implantation damage of light ions", JPN. J. APPL. PHYS., vol. 40, no. 10B, PART 2, 15 October 2001 (2001-10-15), pages L1075 - L1077, XP001111213 * |
See also references of EP1513198A4 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7309640B2 (en) | 2004-04-21 | 2007-12-18 | Stmicroelectronics Sa | Method of fabricating an integrated circuit including hollow isolating trenches and corresponding integrated circuit |
US10950726B2 (en) | 2016-04-25 | 2021-03-16 | Sony Corporation | Semiconductor device, CMOS circuit, and electronic apparatus with stress in channel region |
Also Published As
Publication number | Publication date |
---|---|
US20050176222A1 (en) | 2005-08-11 |
CN1669148A (zh) | 2005-09-14 |
KR20040102223A (ko) | 2004-12-03 |
US7605443B2 (en) | 2009-10-20 |
EP1513198A4 (en) | 2010-02-24 |
AU2003235902A1 (en) | 2003-11-11 |
JP4277481B2 (ja) | 2009-06-10 |
EP1513198A1 (en) | 2005-03-09 |
KR100712572B1 (ko) | 2007-05-02 |
CN100355076C (zh) | 2007-12-12 |
JP2003332540A (ja) | 2003-11-21 |
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