US20120228700A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
US20120228700A1
US20120228700A1 US13/237,309 US201113237309A US2012228700A1 US 20120228700 A1 US20120228700 A1 US 20120228700A1 US 201113237309 A US201113237309 A US 201113237309A US 2012228700 A1 US2012228700 A1 US 2012228700A1
Authority
US
United States
Prior art keywords
type
layer
anode
semiconductor device
impurity concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/237,309
Other languages
English (en)
Inventor
Akito Nishii
Katsumi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Assigned to MITSUBISHI ELECTRIC CORPORATION reassignment MITSUBISHI ELECTRIC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NAKAMURA, KATSUMI, NISHII, AKITO
Publication of US20120228700A1 publication Critical patent/US20120228700A1/en
Priority to US14/336,800 priority Critical patent/US9202936B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Definitions

  • the present invention relates to a diode, which is one of semiconductor devices making up a high withstand voltage power module of 600 V or higher, and more particularly, to a semiconductor device capable of improving oscillation resistance or recovery resistance and suppressing a snap-off phenomenon, and a method for manufacturing the same.
  • FIG. 30 is a diagram illustrating a relationship between an ON voltage VF and a recovery loss Erec of a diode. There is a trade-off relationship between the two. Arbitrary points on the trade-off curve are used depending on the product applied. To obtain a diode having characteristics at arbitrary points on the trade-off curve, lifetime has been conventionally controlled by controlling impurity concentration of a P-type anode layer or through electron beam radiation.
  • a depletion layer extends toward both sides of the anode and cathode.
  • the impurity concentration of the P-type anode layer is lowered, the depletion layer is likely to extend toward the anode side when a high voltage is applied thereto, which causes a reach-through of the electric field on the anode side, resulting in a problem of leading to a drop in the withstand voltage.
  • lowering the impurity concentration of the P-type anode layer makes it possible to reduce a reverse recovery current Irr during recovery operation and thereby reduce recovery loss.
  • the impurity concentration of the P-type anode layer is conventionally reduced within a range in which the withstand voltage can be maintained and the lifetime is controlled to obtain arbitrary characteristics on the trade-off curve.
  • a diode with a trench formed on the anode side has been proposed so far for the purpose of realizing low leakage current and low Irr (e.g., see Japanese Patent Laid-Open No. 11-97715).
  • examples of destruction due to recovery operation include voltage destruction and thermal destruction.
  • thermal destruction residual carriers in the termination region concentrate on the anode termination section during recovery operation, which causes the temperature at the concentration location to rise and leads to thermal destruction. Therefore, the structure in which carriers concentrate on the anode termination section has a problem that recovery resistance is small.
  • a first object of the present invention is to provide a semiconductor device and a method for manufacturing the same which can control ON voltage through the impurity concentration of the P-type anode layer and control ON voltage-recovery loss trade-off characteristics while maintaining the withstand voltage independently of the impurity concentration of the P-type anode layer without controlling lifetime, and suppress snap-off phenomenon.
  • a second object of the present invention is to provide a semiconductor device which can improve recovery resistance.
  • a semiconductor device includes: an N-type drift layer; a P-type anode layer on the N-type drift layer; a trench penetrating the P-type anode layer; a conductive substance embedded in the trench via an insulating film; and an N-type buffer layer between the N-type drift layer and the P-type anode layer and having impurity concentration which is higher than that of the N-type drift layer.
  • a semiconductor device includes: an N-type drift layer; a P-type anode layer on a part of the N-type drift layer; an anode electrode connected to the P-type anode layer; and an insulating film between an outer end of the P-type anode layer and the anode electrode, wherein a length between the outer end of the P-type anode layer and an inner end of the insulating film is 100 ⁇ m or above.
  • the first present invention makes it possible to control ON voltage through the impurity concentration of the P-type anode layer and control ON voltage-recovery loss trade-off characteristics while maintaining the withstand voltage independently of the impurity concentration of the P-type anode layer without controlling lifetime, and suppress snap-off phenomenon.
  • the second present invention makes it possible to improve recovery resistance.
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention.
  • FIGS. 2 and 3 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a diagram illustrating an electric field strength distribution in the anode section when a trench is present or not.
  • FIG. 6 is a cross-sectional view illustrating a conventional semiconductor device.
  • FIG. 8 is a diagram illustrating a relationship between the impurity concentration of the N-type buffer layer and withstand voltage BVrrm when a trench is present or not.
  • FIG. 9 is a diagram illustrating a relationship between an ON voltage VF and cross points.
  • FIG. 10 is a diagram illustrating a relationship between the depth of the trench and the withstand voltage BVrrm.
  • FIG. 12 is a diagram illustrating a relationship between the impurity concentration of the N-type buffer layer 6 and ON voltage VF.
  • FIG. 14 is a diagram illustrating a relationship between the impurity concentration of the P-type anode layer and ON voltage when the P + -type contact layer 8 is present or not.
  • FIG. 15 is a diagram illustrating the circuit used for the simulations in FIG. 11 and FIG. 13 and the parameters of the circuit.
  • FIG. 17 is a top view illustrating a semiconductor device according to a comparative example 1.
  • FIGS. 18 and 19 are cross-sectional views illustrating the method of manufacturing a semiconductor device according to the comparative example 2.
  • FIG. 25 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention.
  • FIG. 27 is a diagram illustrating the circuit used for the simulation in FIG. 26 and parameters of the circuit.
  • FIG. 29 is a cross-sectional view illustrating a modification example of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 30 is a diagram illustrating a relationship between an ON voltage VF and a recovery loss Erec of a diode.
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention.
  • a P-type anode layer 2 is provided on an N ⁇ -type drift layer 1 .
  • a trench 3 is provided so as to penetrate the P-type anode layer.
  • a conductive substance 5 is embedded in the trench 3 via an insulating film 4 .
  • an N-type buffer layer 6 is provided between the N ⁇ -type drift layer 1 and the P-type anode layer 2 to reduce a reverse recovery current Irr during recovery operation by suppressing hole injection in an ON state.
  • the N-type buffer layer 6 has impurity concentration, which is lower than that of the P-type anode layer 2 and higher than that of the N ⁇ -type drift layer 1 .
  • the conductive substance 5 in the trench 3 is connected to an anode electrode 7 and has the same potential as that of the anode electrode 7 .
  • this causes the trench 3 to become GND, making it possible to suppress an increase in the electric field in the PN junction between the P-type anode layer 2 and N-type buffer layer 6 through a field plate effect.
  • a P + -type contact layer 8 having higher concentration ( ⁇ 1 ⁇ 10 19 cm ⁇ 3 ) than that of the P-type anode layer 2 is provided between the P-type anode layer 2 and the anode electrode 7 .
  • N + -type cathode layer 9 and a P-type cathode layer 10 are provided on the underside of the N ⁇ -type drift layer 1 .
  • the P-type cathode layer 10 is designed to have appropriate concentration so as to have desired electric characteristics.
  • N-type layers 11 and 12 are formed right above the N + -type cathode layer 9 and the P-type cathode layer 10 respectively.
  • the N-type layers 11 and 12 can make carrier injection easier when a forward bias is applied, can prevent punch-through when a reverse bias is applied and can control hole injection during recovery operation.
  • the impurity concentration of the respective layers is set to: N-type layer 12 ⁇ N-type layer 11 ⁇ P-type cathode layer 10 ⁇ N + -type cathode layer 9 .
  • FIGS. 2 and 3 are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
  • the P-type anode layer 2 or the like is formed on the top surface of the N ⁇ -type drift layer 1 .
  • the N + -type cathode layer 9 is selectively formed in a first region of the underside of the N ⁇ -type drift layer 1 using a mask 13 .
  • the P-type cathode layer 10 is selectively formed in a second region which is different from the first region of the underside of the N ⁇ -type drift layer 1 using a mask 14 .
  • FIG. 4 is a diagram illustrating an electric field strength distribution in the anode section when a trench is present or not.
  • the electric field of the PN junction is extended toward the N ⁇ -type drift layer 1 side through the field plate effect of the trench 3 . This makes it possible to suppress increases in the electric field strength of the PN junction.
  • FIG. 5 is a diagram illustrating a relationship between the impurity concentration of the P-type anode layer, ON voltage VF and withstand voltage BVrrm. Since the amount of hole injection when a forward bias is applied varies depending on the impurity concentration of the P-type anode layer, the ON voltage changes. When the impurity concentration of the P-type anode layer decreases, the withstand voltage decreases in the conventional structure shown in FIG. 6 as described above, whereas the withstand voltage can be maintained in the structure of the first embodiment.
  • FIG. 7 is a diagram illustrating differences in VF-Erec trade-off characteristics using the respective trade-off control methods of the prior art and the present invention.
  • the conventional control method using lifetime control can control trade-off characteristics only in a high VF range determined by the impurity concentration of the P-type anode layer.
  • the control method of the present invention using impurity concentration of the P-type anode layer using the trench structure can maintain the withstand voltage even when the P-type impurity concentration is lowered. For this reason, it is possible to control VF through the impurity concentration of the P-type anode layer and control trade-off characteristics while maintaining the withstand voltage independently of the impurity concentration of the P-type anode layer.
  • FIG. 8 is a diagram illustrating a relationship between the impurity concentration of the N-type buffer layer and withstand voltage BVrrm when a trench is present or not.
  • the impurity concentration of the N-type buffer layer 6 increases, the electric field of the PN junction is more likely to increase and the withstand voltage decreases.
  • the increase in the electric field of the PN junction is relaxed, and therefore the withstand voltage is maintained even when the N-type buffer layer 6 is provided.
  • the impurity concentration of the N-type buffer layer 6 increases, the impurity concentration of the P-type anode layer 2 relatively decreases.
  • FIG. 9 is a diagram illustrating a relationship between an ON voltage VF and cross points.
  • changing the ON voltage VF through the impurity concentration control of the P-type anode layer 2 can suppress increases of cross points.
  • the chip of a power module mounted with a diode is operated in parallel, and therefore when a chip with cross points having a higher current density than the rated one is mounted, currents are concentrated on the chip and it is more difficult to control the parallel operation. Therefore, the diode of the present embodiment capable of suppressing increases in cross points is effective.
  • FIG. 10 to FIG. 14 show results of simulating influences of respective design parameters of the anode side on electric characteristics.
  • FIG. 15 is a diagram illustrating the circuit used for the simulations in FIG. 11 and FIG. 13 and the parameters of the circuit.
  • FIG. 10 is a diagram illustrating a relationship between the depth of the trench and the withstand voltage BVrrm.
  • FIG. 11 is a diagram illustrating a relationship between the anode width, trench width and snap-off voltage Vsnap-off.
  • the anode width is (pitch of the trench 3 ) ⁇ (width of the trench 3 ⁇ 2).
  • the contact area of the anode electrode 7 decreases. Therefore, the carrier path is narrowed, and many carriers exist in the trench 3 even upon termination of recovery operation (immediately before the current becomes 0) and the current variation increases compared to a case where the width of the trench 3 is small.
  • the snap-off voltage Vsnap-off increases depending on the rate of change of current, and therefore oscillation characteristics deteriorate. Therefore, the width of the trench 3 needs to be equal to or below 1.2 ⁇ m.
  • the anode width has no effect on oscillation characteristics, and therefore the anode width can be designed to an arbitrary value.
  • FIG. 12 is a diagram illustrating a relationship between the impurity concentration of the N-type buffer layer 6 and ON voltage VF.
  • FIG. 13 is a diagram illustrating a relationship between the impurity concentration of the N-type buffer layer 6 and snap-off voltage Vsnap-off.
  • the impurity concentration of the N-type buffer layer 6 needs to be equal to or below 1 ⁇ 10 17 cm ⁇ 3 .
  • the N-type buffer layer 6 has the effect of controlling recoupling of carriers in the N-type buffer layer 6 and reducing reverse recovery current 1 rr during recovery operation. The higher the impurity concentration of the N-type buffer layer 6 , the greater the effect thereof.
  • FIG. 14 is a diagram illustrating a relationship between the impurity concentration of the P-type anode layer and ON voltage when the P + -type contact layer 8 is present or not. Since the diode of the present embodiment is provided with the trench 3 , the area of contact with the anode electrode 7 is small. Therefore, when the P + -type contact layer 8 is not present, the ON voltage VF increases, and therefore the P + -type contact layer 8 needs to be provided.
  • FIG. 16 is a top view illustrating a semiconductor device according to the first embodiment of the present invention.
  • FIG. 17 is a top view illustrating a semiconductor device according to a comparative example 1.
  • the comparative example 1 when the P + -type contact layer 8 is formed over the entire region of the contact section, hole injection from the anode electrode 7 is determined by the impurity concentration of the P + -type contact layer 8 and it is not possible to control VF-Erec trade-off characteristics through the impurity concentration of the P-type anode layer 2 . Therefore, the width of the P + -type contact layer 8 needs to be designed appropriately as in the case of the present embodiment.
  • the present embodiment provides the P-type cathode layer 10 on the cathode side of the diode. During recovery operation, this causes holes to be injected from the P-type cathode layer 10 , suppresses a drastic drop in carrier density of the cathode and can reduce the snap-off voltage Vsnap-off. Therefore, the oscillation resistance can be improved.
  • FIGS. 18 and 19 are cross-sectional views illustrating the method of manufacturing a semiconductor device according to the comparative example 2.
  • the P-type cathode layer 10 is formed on the entire underside of the N ⁇ -type drift layer 1 .
  • the N + -type cathode layer 9 is selectively formed in a partial region of the underside of the N ⁇ -type drift layer 1 using the mask 13 .
  • FIG. 20 to FIG. 22 show results of measuring a relationship between the formation process of the P-type cathode layer 10 , impurity concentration and electric characteristics.
  • measuring conditions in FIG. 21 and FIG. 22 are: power supply voltage Vcc is 2500 V, current density Jc is 0.7 ⁇ rated current density, floating inductance Ls is 4.6 ⁇ H, and the rate of change of current density dj/dt at the time of recovery operation start is 1350 A/ ⁇ sec ⁇ cm ⁇ 2 .
  • FIG. 20 is a diagram illustrating a leakage current density Jrrm of the diode manufactured using the manufacturing methods according to the first embodiment of the present invention and the comparative example 2.
  • the leakage current increases and the withstand voltage decreases. Therefore, it is necessary to selectively form the P-type cathode layer 10 and N + -type cathode layer 9 to prevent influences from each other as in the case of the first embodiment.
  • FIG. 21 is a diagram illustrating a relationship between the dose of the P-type cathode layer and the snap-off voltage Vsnap-off.
  • FIG. 22 is a diagram illustrating a relationship between the dose of the P-type cathode layer and OFF time trr during recovery operation.
  • the higher the dose of the P-type cathode layer 10 the greater the snap-off voltage V snap-off suppression effect.
  • the dose of the P-type cathode layer 10 needs to fall within a range of 1 ⁇ 10 13 to 1 ⁇ 10 14 cm ⁇ 3 .
  • FIG. 23 is a cross-sectional view illustrating a modification example of the semiconductor device according to the first embodiment of the present invention. In this way, even when the P-type cathode layer 10 is not provided, effects of the above described trench structure can be obtained.
  • FIG. 24 is a cross-sectional view illustrating a modification example of the semiconductor device according to the first embodiment of the present invention. In this way, even when the N buffer layer on the cathode side has uniform concentration, it is possible to obtain an effect of suppressing the snap-off voltage Vsnap-off by the aforementioned P-type cathode layer.
  • withstand voltage class device of 3300 V class or higher has been described in the present embodiment as an example, similar effects can also be obtained with a withstand voltage class of less than 3300 V.
  • FIG. 25 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention.
  • a termination region is provided outside an effective region of a diode.
  • P-type anode layers 2 and 15 are provided on a part of an N ⁇ -type drift layer 1 in the effective region.
  • An anode electrode 7 is connected to the P-type anode layer 2 .
  • An insulating film 16 is provided between outer ends of the P-type anode layers 2 and 15 and the anode electrode 7 .
  • a channel stopper 17 is provided at an outer end of the N + -type drift layer 1 .
  • An insulating film 18 is provided in the termination region.
  • FIG. 26 is a diagram illustrating results of simulating a relationship between a length Labr and a maximum in-chip temperature.
  • FIG. 27 is a diagram illustrating the circuit used for the simulation in FIG. 26 and parameters of the circuit.
  • the length Labr is a length between the outer end of the P-type anode layer 2 and an inner end of the insulating film 16 . By extending the insulating film 16 toward the effective region side, a resistance component is formed at an end of the anode effective region.
  • the present embodiment sets the length Labr between the outer end of the P-type anode layer 2 and the inner end of the insulating film 16 to 100 ⁇ m or above. This prevents heat from scattering through the resistance component producing a temperature rise.
  • FIG. 28 is a diagram illustrating a recovery SOA (Safety Operation Area) of the diode.
  • the recovery SOA shows a relationship between a power supply voltage Vcc that guarantees operation of the diode and a current density Jc.
  • FIG. 29 is a cross-sectional view illustrating a modification example of the semiconductor device according to the second embodiment of the present invention.
  • a P-type cathode layer 10 is provided in the termination region.
  • effects of the present invention can be obtained, too. Without being limited to this, effects of the present invention can be obtained no matter what structure the anode effective region, cathode effective region or cathode termination region has.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
US13/237,309 2011-03-09 2011-09-20 Semiconductor device and method for manufacturing the same Abandoned US20120228700A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/336,800 US9202936B2 (en) 2011-03-09 2014-07-21 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011050995A JP2012190873A (ja) 2011-03-09 2011-03-09 半導体装置及びその製造方法
JP2011-050995 2011-03-09

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/336,800 Division US9202936B2 (en) 2011-03-09 2014-07-21 Semiconductor device

Publications (1)

Publication Number Publication Date
US20120228700A1 true US20120228700A1 (en) 2012-09-13

Family

ID=46705499

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/237,309 Abandoned US20120228700A1 (en) 2011-03-09 2011-09-20 Semiconductor device and method for manufacturing the same
US14/336,800 Active US9202936B2 (en) 2011-03-09 2014-07-21 Semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/336,800 Active US9202936B2 (en) 2011-03-09 2014-07-21 Semiconductor device

Country Status (5)

Country Link
US (2) US20120228700A1 (zh)
JP (1) JP2012190873A (zh)
KR (1) KR101329613B1 (zh)
CN (1) CN102683427B (zh)
DE (1) DE102011089452B4 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8710585B1 (en) * 2013-02-25 2014-04-29 Alpha And Omega Semiconductor Incorporated High voltage fast recovery trench diode
US20150249082A1 (en) * 2012-09-04 2015-09-03 Infineon Technologies Austria Ag Field-Effect Semiconductor Device
US9634128B2 (en) 2014-03-17 2017-04-25 Kabushiki Kaisha Toshiba Semiconductor device
US20220181473A1 (en) * 2019-04-02 2022-06-09 Abb Power Grids Switzerland Ag Segmented Power Diode Structure with Improved Reverse Recovery

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014154849A (ja) * 2013-02-13 2014-08-25 Toshiba Corp 半導体装置
JP6266480B2 (ja) * 2014-09-12 2018-01-24 株式会社東芝 半導体装置
JP6319057B2 (ja) * 2014-11-21 2018-05-09 三菱電機株式会社 逆導通型半導体装置
JP6293688B2 (ja) * 2015-03-02 2018-03-14 株式会社豊田中央研究所 ダイオード及びそのダイオードを内蔵する逆導通ｉｇｂｔ
JP7077648B2 (ja) * 2017-02-16 2022-05-31 富士電機株式会社 半導体装置
JP6643382B2 (ja) 2017-03-20 2020-02-12 インフィニオン テクノロジーズ オーストリア アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｕｓｔｒｉａ ＡＧ パワー半導体デバイス
DE202017006860U1 (de) 2017-03-20 2018-08-09 Infineon Technologies Austria Ag Überspannungsschutzleistungshalbleitervorrichtung

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5859446A (en) * 1996-02-28 1999-01-12 Hitachi, Ltd. Diode and power converting apparatus

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969400A (en) * 1995-03-15 1999-10-19 Kabushiki Kaisha Toshiba High withstand voltage semiconductor device
JP3409503B2 (ja) 1995-05-22 2003-05-26 株式会社日立製作所 ダイオード及びダイオードの駆動方法並びに半導体回路
JPH1093113A (ja) 1996-09-19 1998-04-10 Hitachi Ltd ダイオード
JP4351745B2 (ja) 1997-09-19 2009-10-28 株式会社東芝 半導体装置
JP4017258B2 (ja) * 1998-07-29 2007-12-05 三菱電機株式会社 半導体装置
JP2000299476A (ja) 1999-04-15 2000-10-24 Toshiba Corp 半導体装置
JP3968912B2 (ja) 1999-05-10 2007-08-29 富士電機デバイステクノロジー株式会社 ダイオード
JP4678077B2 (ja) 1999-07-21 2011-04-27 株式会社豊田中央研究所 ダイオード
GB0102734D0 (en) * 2001-02-03 2001-03-21 Koninkl Philips Electronics Nv Bipolar diode
JP4047153B2 (ja) * 2002-12-03 2008-02-13 株式会社東芝 半導体装置
US7638841B2 (en) * 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
JP2006210667A (ja) * 2005-01-28 2006-08-10 Mitsubishi Electric Corp 半導体装置
JP5617175B2 (ja) * 2008-04-17 2014-11-05 富士電機株式会社 ワイドバンドギャップ半導体装置とその製造方法
JP4743447B2 (ja) * 2008-05-23 2011-08-10 三菱電機株式会社 半導体装置
JP5003598B2 (ja) 2008-06-05 2012-08-15 富士電機株式会社 半導体装置
JP2010283132A (ja) 2009-06-04 2010-12-16 Mitsubishi Electric Corp 半導体装置
JP5607720B2 (ja) * 2010-02-23 2014-10-15 良孝 菅原 半導体装置
JP5434961B2 (ja) * 2010-08-04 2014-03-05 株式会社デンソー 横型ダイオードを有する半導体装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5859446A (en) * 1996-02-28 1999-01-12 Hitachi, Ltd. Diode and power converting apparatus

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150249082A1 (en) * 2012-09-04 2015-09-03 Infineon Technologies Austria Ag Field-Effect Semiconductor Device
US10032767B2 (en) * 2012-09-04 2018-07-24 Infineon Technologies Austria Ag Field-effect semiconductor device
US20180323189A1 (en) * 2012-09-04 2018-11-08 Infineon Technologies Austria Ag Field-Effect Semiconductor Device Having a Heterojunction Contact
US10461074B2 (en) * 2012-09-04 2019-10-29 Infineon Technologies Austria Ag Field-effect semiconductor device having a heterojunction contact
US8710585B1 (en) * 2013-02-25 2014-04-29 Alpha And Omega Semiconductor Incorporated High voltage fast recovery trench diode
CN104009068A (zh) * 2013-02-25 2014-08-27 万国半导体股份有限公司 高压快速恢复沟槽二极管
US8907414B2 (en) 2013-02-25 2014-12-09 Alpha And Omega Semiconductor Incorporated High voltage fast recovery trench diode
US9634128B2 (en) 2014-03-17 2017-04-25 Kabushiki Kaisha Toshiba Semiconductor device
US10141455B2 (en) 2014-03-17 2018-11-27 Kabushiki Kaisha Toshiba Semiconductor device
US20220181473A1 (en) * 2019-04-02 2022-06-09 Abb Power Grids Switzerland Ag Segmented Power Diode Structure with Improved Reverse Recovery
US11967638B2 (en) * 2019-04-02 2024-04-23 Hitachi Energy Ltd Segmented power diode structure with improved reverse recovery

Also Published As

Publication number Publication date
CN102683427A (zh) 2012-09-19
US9202936B2 (en) 2015-12-01
DE102011089452B4 (de) 2022-05-25
DE102011089452A1 (de) 2012-09-13
US20140327072A1 (en) 2014-11-06
CN102683427B (zh) 2015-08-05
KR101329613B1 (ko) 2013-11-15
JP2012190873A (ja) 2012-10-04
KR20120103459A (ko) 2012-09-19

Similar Documents

Publication Publication Date Title
US9202936B2 (en) Semiconductor device
US9601485B2 (en) Reverse-conducting IGBT with buffer layer and separation layer for reducing snapback
US8686469B2 (en) Semiconductor device
US9786796B2 (en) Semiconductor device having first and second layers with opposite conductivity types
CN105679835B (zh) 半导体器件
KR100895057B1 (ko) 반도체 장치
WO2014199465A1 (ja) 半導体装置
JP6237915B2 (ja) 半導体装置および半導体装置の製造方法
JP5256357B2 (ja) 半導体装置
JP5345596B2 (ja) ソフトリカバリ挙動をもつサージ電流耐性半導体ダイオードおよび半導体ダイオードを製造する方法
US10411093B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP2017135339A (ja) 半導体装置
US9054152B2 (en) Semiconductor device
WO2014087543A1 (ja) 半導体装置の製造方法
JP2016195271A (ja) 半導体装置
JP6750668B2 (ja) 半導体装置
JP7246983B2 (ja) 半導体装置
US7511353B2 (en) Semiconductor diode and production method suitable therefor
JP6065035B2 (ja) 半導体装置
CN104916690A (zh) 半导体装置
JP2018029150A (ja) 半導体装置

Legal Events

Date Code Title Description
AS Assignment

Owner name: MITSUBISHI ELECTRIC CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NISHII, AKITO;NAKAMURA, KATSUMI;REEL/FRAME:026935/0605

Effective date: 20110826

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION