US20070075437A1 - Relay board and semiconductor device having the relay board - Google Patents

Relay board and semiconductor device having the relay board Download PDF

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Publication number
US20070075437A1
US20070075437A1 US11/295,472 US29547205A US2007075437A1 US 20070075437 A1 US20070075437 A1 US 20070075437A1 US 29547205 A US29547205 A US 29547205A US 2007075437 A1 US2007075437 A1 US 2007075437A1
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Prior art keywords
terminal
bonding
relay board
wiring
bonding pad
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Abandoned
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US11/295,472
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English (en)
Inventor
Takao Nishimura
Kouichi Nakamura
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Fujitsu Semiconductor Ltd
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Fujitsu Ltd
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Assigned to FUJITSU LIMITED reassignment FUJITSU LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NAKAMURA, KOUICHI, NISHIMURA, TAKAO
Publication of US20070075437A1 publication Critical patent/US20070075437A1/en
Assigned to FUJITSU MICROELECTRONICS LIMITED reassignment FUJITSU MICROELECTRONICS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU LIMITED
Priority to US12/824,117 priority Critical patent/US8404980B2/en
Assigned to FUJITSU SEMICONDUCTOR LIMITED reassignment FUJITSU SEMICONDUCTOR LIMITED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU MICROELECTRONICS LIMITED
Abandoned legal-status Critical Current

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    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Definitions

  • the present invention generally relates to relay boards and semiconductor devices having the relay boards, and more specifically, to a relay board used for wiring the semiconductor chips to each other, or the semiconductor chip to and a wiring board or a lead frame, and the semiconductor device having the relay board.
  • a semiconductor device having a structure where at least one semiconductor chip (semiconductor element) and a wiring substrate or a lead frame are connected by a bonding wire is known.
  • semiconductor device depending on arrangements of electrode pads of the semiconductor chip and bonding pads of the wiring substrate or a bonding lead of the lead frame, crossing or superposing of the bonding wires happens, a length of the bonding wire is too long, or the like so that wire-bonding may be hard to accomplish.
  • FIG. 1 a structure where a relay board for relaying wiring by bonding wires is provided in a semiconductor device has been suggested.
  • FIG. 1 is a cross-sectional view of a related art semiconductor device having the relay board.
  • FIG. 1 -(A) is a cross-sectional view taken along a line X-X′ of FIG. 1 -(B) which is a plan view of this related art semiconductor device.
  • a semiconductor device 10 has a structure where a first semiconductor chip 6 is mounted on a wiring board 4 having a lower surface where plural bumps 2 are formed.
  • a second semiconductor chip 8 and a relay board 20 are provided on the first semiconductor chip 6 .
  • a bonding pad 1 a of the wiring board 4 is connected to an electrode pad 7 of a first semiconductor chip 6 by a bonding wire 3 .
  • a bonding pad 1 b of the wiring board 4 is connected to a first electrode pad 11 of the second semiconductor chip 8 by a bonding wire 5 .
  • a bonding pad 13 of the second semiconductor chip 8 is connected to a first bonding pad 22 of the relay board 20 by a bonding wire 23 .
  • a second bonding pad 24 of the relay board 20 is connected to another bonding pad 1 b of the wiring board 4 by a bonding wire 25 .
  • the first bonding pad 22 and the second bonding pad 24 of the relay board 20 faces each other.
  • a wiring 26 connects the first bonding pad 22 and the second bonding pad 24 in a straight line state.
  • first semiconductor chip 6 , the second semiconductor chip 8 , the relay board 20 , and the bonding wires 3 , 5 , 23 and 25 are sealed by sealing resin 9 so that the semiconductor 10 is made packaged.
  • the relay board 20 is provided between the second electrode pad 13 of the second semiconductor chip 8 and the bonding pad 1 b of the wiring board 4 and the second semiconductor chip 8 and the relay board 20 are wire-bonded so that the second semiconductor chip 8 and the wiring board 4 are electrically connected.
  • the second electrode pad 13 of the second semiconductor chip 8 is greatly separated from the bonding pad 1 b of the wiring board 4 .
  • a bonding wire having a long wiring length is necessary.
  • the wiring length can be shortened.
  • FIG. 2 and FIG. 3 a relay board having an arrangement of bonding pads different from the example shown in FIG. 1 has been suggested.
  • FIG. 2 is a plan view of a related art relay board having an arrangement of bonding pads different from the example shown in FIG. 1 .
  • the arrangement direction of a first bonding pad group 31 A through 31 F is perpendicular to the arrangement direction of a second bonding pad group 32 A through 32 F.
  • Pads corresponding to each other of the first bonding pad group 31 A through 31 F and the second bonding pad group 32 A through 32 F are connected by wiring 33 A through 33 F extending in an L-shape.
  • this structure is effective in a case where the angle between a connecting direction of a bonding wire from a bonding pad and another connecting direction of another bonding wire from another bonding pad is approximately 90 degrees.
  • FIG. 3 is a plan view of another related art relay board having an arrangement of bonding pads different from the examples shown in FIG. 1 and FIG. 2 .
  • wirings 43 A through 43 D for connecting first bonding pads 41 A through 41 D and second bonding pads 42 A through 42 D are provided so as to be bent on the way plural times (bent line state). Thus, change of the arrangement of the bonding pads is realized.
  • first bonding pads 41 A through 41 D are provided in the vicinity of and along a side (upper side) of the relay board 40 .
  • the second bonding pads 42 A through 42 D are provided in the vicinity of and along a side (lower side) of the relay board 40 .
  • the first bonding pad 41 A and the second bonding pad 42 A can be electrically connected by the wiring 43 A bent on the way plural times.
  • the first bonding pad 41 B and the second bonding pad 42 B can be electrically connected by the wiring 43 B bent on the way plural times.
  • the first bonding pad 41 C and the second bonding pad 42 C can be electrically connected by the wiring 43 C bent on the way plural times.
  • the first bonding pad 41 D and the second bonding pad 42 D can be electrically connected by the wiring 43 D bent on the way plural times.
  • a semiconductor device having a structure where a relay board and a semiconductor chip are arranged to be substantially coplanar and connected by wiring-bonding See Japan Laid-Open Patent Application Publications No. 2-109344 and No. 2-216839
  • a semiconductor device having a structure where a relay board smaller than a semiconductor chip is mounted on the semiconductor chip See Japan Laid-Open Patent Application Publications No. 5-13490 and No. 2004-153295
  • a semiconductor device having a structure where a relay board is provided under a semiconductor chip See Japan Laid-Open Patent Application Publication No.
  • the size of the semiconductor chip or the wiring board, and the number and the way of arrangement of electrode pads formed on the semiconductor chip or bonding pads formed on the wiring board vary. Therefore, a relay board suitable for a certain semiconductor device is not always suitable for other semiconductor device.
  • the way of mounting a semiconductor chip on a semiconductor device, the arrangement of electrode pads of a semiconductor chip, or the connection structure between a semiconductor chip and a wiring board or a lead frame may need to be changed.
  • positions of the bonding pads of the relay board may need to be changed.
  • the related art relay boards do not correspond to these structures and it is necessary to newly provide a relay board having a different structure.
  • Another and more specific object of the present invention is to provide a relay board applied to a semiconductor device, whereby plural bonding pads arranged on the relay board can be optionally selected and/or a connection way of a wiring connecting the bonding pads or a bonding wire can be optionally selected so that the relay board can be applied to semiconductor device having different function or structure.
  • a relay board provided in a semiconductor device including:
  • wiring connecting to the first terminal is split on the way so that the wiring connects to each of the second terminals.
  • a relay board provided in a semiconductor device including:
  • connection part is formed by at least one of an end part of a first terminal wire connected to the first terminal and an end part of a second terminal wire connected to the second terminal;
  • the first terminal and the second terminal are connected by forming a connection member at the connection part.
  • a semiconductor device including:
  • the relay board includes a first terminal and a second terminal
  • connection part is formed by at least one of an end part of a first terminal wire connected to the first terminal and an end part of a second terminal wire connected to the second terminal;
  • the first terminal and the second terminal are connected by forming a connection member at the connection part.
  • the relay board can be applied to different kinds of semiconductor devices. Hence, it is possible to reduce manufacturing cost of the relay board and the semiconductor device having the relay board.
  • relay board can improve the degree of freedom of selecting combinations of semiconductor elements mounted on the wiring board or lead frame.
  • FIG. 1 is a cross-sectional view of a related art semiconductor device having a relay board
  • FIG. 2 is a plan view of a related art relay board having an arrangement of bonding pads different from the example shown in FIG. 1 ;
  • FIG. 3 is a plan view of another related art relay board having an arrangement of bonding pads different from examples shown in FIG. 1 and FIG. 2 ;
  • FIG. 4 is a plan view showing a first schematic structure of a relay board of an embodiment of the present invention.
  • FIG. 5 is a plan view showing a second schematic structure of a relay board of an embodiment of the present invention.
  • FIG. 6 is a view showing a structure of a bonding wire connection part
  • FIG. 7 is a plan view showing a configuration of an end part of a wiring in another example of the bonding wire connection part
  • FIG. 8 is a plan view showing a configuration of an end part of a wiring in another example of the bonding wire connection part
  • FIG. 9 is a view showing a structure of a bump bonding connection part
  • FIG. 10 is a plan view showing a configuration of an end part of a wiring in another example of the bump bonding connection part
  • FIG. 11 is a plan view showing a configuration of an end part of a wiring in another example of the bump bonding connection part
  • FIG. 12 is a plan view showing a configuration of an end part of a wiring in another example of the bump bonding connection part
  • FIG. 13 is a plan view showing a configuration of an end part of a wiring in another example of the bump bonding connection part
  • FIG. 14 is a plan view showing a configuration of an end part of a wiring in another example of the bump bonding connection part
  • FIG. 15 is a plan view showing a configuration of an end part of a wiring in another example of the bump bonding connection part
  • FIG. 16 is a cross-sectional view showing an arrangement structure of a stud bump and the bump connection part
  • FIG. 17 is a cross-sectional view showing another arrangement structure of a stud bump and the bump connection part
  • FIG. 18 is a view showing a connection structure of a bonding wire to a second bonding pad
  • FIG. 19 is a first plan view of a schematic structure of a first modified example of the relay board of the embodiment of the present invention.
  • FIG. 20 is a second plan view of a schematic structure of a first modified example of the relay board of the embodiment of the present invention.
  • FIG. 21 is a plan view of a schematic structure of a second modified example of the relay board of the embodiment of the present invention.
  • FIG. 22 is a first plan view of a schematic structure of a third modified example of the relay board of the embodiment of the present invention.
  • FIG. 23 is a second plan view of a schematic structure of a third modified example of the relay board of the embodiment of the present invention.
  • FIG. 24 is a third plan view of a schematic structure of a third modified example of the relay board of the embodiment of the present invention.
  • FIG. 25 is a first plan view of a schematic structure of a fourth modified example of the relay board of the embodiment of the present invention.
  • FIG. 26 is a second plan view of a schematic structure of a fourth modified example of the relay board of the embodiment of the present invention.
  • FIG. 27 is a third plan view of a schematic structure of a fourth modified example of the relay board of the embodiment of the present invention.
  • FIG. 28 is a first plan view of a schematic structure of a fifth modified example of the relay board of the embodiment of the present invention.
  • FIG. 29 is a second plan view of a schematic structure of a sixth modified example of the relay board of the embodiment of the present invention.
  • FIG. 30 is a view showing a first example of a semiconductor device having a relay board of the embodiment of the present invention.
  • FIG. 31 is a view showing a second example of a semiconductor device having a relay board of the embodiment of the present invention.
  • FIG. 32 is a view showing a third example of a semiconductor device having a relay board of the embodiment of the present invention.
  • FIG. 33 is a view showing a fourth example of a semiconductor device having a relay board of the embodiment of the present invention.
  • FIG. 34 is a view showing a fifth example of a semiconductor device having a relay board of the embodiment of the present invention.
  • FIG. 35 is a view showing a sixth example of a semiconductor device having a relay board of the embodiment of the present invention.
  • FIG. 36 is a view showing a seventh example of a semiconductor device having a relay board of the embodiment of the present invention.
  • FIG. 37 is a view showing an eighth example of a semiconductor device having a relay board of the embodiment of the present invention.
  • FIG. 38 is a view showing an eighth example of a semiconductor device having a relay board of the embodiment of the present invention.
  • a terminal chip of the embodiment of the present invention is discussed with reference to FIG. 4 through FIG. 29 , and then a semiconductor device of the embodiment of the present invention is discussed with reference to FIG. 30 through FIG. 38 .
  • a terminal chip of the present invention is provided in the semiconductor device and functions as a relay board of a semiconductor chip provided in the semiconductor device.
  • a relay board of the present invention is a board provided in a semiconductor device, the board being configured to relay wiring such as a bonding wire for connecting a semiconductor chip (semiconductor element), to another semiconductor chip, a wiring substrate or a lead frame.
  • a first bonding pad corresponds to “a first terminal” of claims
  • a second bonding pad corresponds to “a second terminal” of claims
  • a first bonding pad corresponds to “a first terminal” of claims
  • a wiring connected to the first bonding pad corresponds to “a first terminal wiring” of claims
  • a wiring connected to the second bonding pad corresponds to “a second terminal wiring” of claims.
  • FIG. 4 is a plan view showing a first schematic structure of a relay board 50 of an embodiment of the present invention.
  • first bonding pads 51 A through 51 E are provided along an upper side of the relay board 50 whose main surface has a substantially rectangular configuration. Bonding wires 53 for electrically connecting to electrode pads of a semiconductor chip (not shown) are connected to the first bonding pads 51 A through 51 E.
  • Second bonding pads 52 A through 52 E, 52 A′, 52 B′ and 52 E′ are provided along a lower side facing the upper side of the relay board 50 .
  • Bonding wires 54 for electrically connecting to another semiconductor chip, a wiring board, or a lead frame (not shown) are connected to the second bonding pads 52 A through 52 E.
  • the bonding wire 54 is not connected to the second bonding pad 52 A′ provided between the second bonding pads 52 A and 52 B and therefore the second bonding pad 52 A′ functions as a preliminary bonding pad.
  • the bonding wire 54 is not connected to the second bonding pad 52 B′ provided between the second bonding pads 52 D and 52 E and therefore the second bonding pad 52 B′ functions as a preliminary bonding pad.
  • the bonding wire 54 is not connected to the second bonding pad 52 E′ provided at a right side of the second bonding pad 52 E and therefore the second bonding pad 52 E′ functions as a preliminary bonding pad.
  • first bonding pad 51 A is connected by a first wiring 55 .
  • the first wiring 55 splits (forms multiple paths) on the way so that wiring parts 55 A and 55 A′ are formed.
  • the wiring part 55 A connects to the second bonding pad 52 A.
  • the wiring part 55 A′ connects to the second bonding pad 52 A′.
  • first bonding pad 51 A and the second bonding pads 52 A and 52 A′ connected to the first bonding pad 51 A by the split first wiring 55 are provided, so that a connection of the bonding wire 54 to either of second bonding pads 52 A and 52 A′ can be selected.
  • either of second bonding pad 52 A or 52 A′ having the same electric potential can be selected and the bonding wire 54 can be connected to either of second bonding pads 52 A and 52 A′.
  • the second bonding pad 52 A is selected so that the bonding wire 54 is connected to the second bonding pad 52 A.
  • the bonding pad 52 A′ is not selected and functions as a preliminary bonding pad.
  • a second wiring 56 is connected to the first bonding pad 51 B.
  • a third wiring 57 is connected to the second bonding pad 52 B.
  • a fourth wiring 58 is connected to the second bonding pad 52 B′ separated from the second bonding pad 52 B.
  • Bonding wire connection parts 60 are formed at end parts of the wirings 56 through 58 . A detailed structure of the bonding wire connection part 60 is discussed below.
  • a bonding wire connection part 60 a is formed at an end part of the second wiring 56 connected to the first bonding pad 51 B.
  • a bonding wire connection part 60 b is formed at an end part of the third wiring 57 connected to the second bonding pad 52 B.
  • a bonding wire connection part 60 d is formed at an end part of the fourth wiring 58 connected to the second bonding pad 52 B′.
  • the bonding wire connection part 60 a and the bonding wire connection part 60 b or the bonding wire connection part 60 d can be selectively connected by a bonding wire as a connection member.
  • either of second bonding pads 52 B and 52 B′ having same electric potential can be selected so as to be capable of being connected to the first bonding pad 51 B.
  • the bonding wire connection part 60 b formed at an end part of the third wiring 57 connected to the second bonding pad 52 B is selected.
  • the bonding wire connection part 60 a formed at the end part of the second wiring 56 connected to the first bonding pad 51 B and the bonding wire connection part 60 b formed at the end part of the third wiring 57 connected to the second bonding pad 52 B can be electrically connected by the bonding wire 61 as the connection member.
  • a bonding wire 54 is connected to the second bonding pad 52 B.
  • the bonding wire 61 is not connected to the bonding wire connection part 60 d corresponding to the second bonding pad 52 B′ and therefore the second bonding pad 52 B′ functions as a preliminary bonding pad. Accordingly, the bonding wire 54 is not connected to the bonding pad 52 B′.
  • the degree of freedom of connection at the relay board 50 is improved by providing the bonding wire connection part 60 .
  • a fifth wiring 70 is connected to a first bonding pad 51 C.
  • a sixth wiring 80 is connected to a first bonding pad 51 D.
  • a seventh wiring 90 and an eighth wiring 95 are connected to a second bonding pad 52 C.
  • a ninth wiring 100 is connected to a second bonding pad 52 D.
  • the fifth wiring 70 , the sixth wiring 80 , and the ninth wiring 100 , as well as the first wiring 55 split on the way so as to form wiring parts 70 A and 70 A′, wiring parts 80 A and 80 A′, and wiring parts 100 A and 100 A′.
  • An end part of the wiring part 70 A of the fifth wiring 70 and an end part of the seventh wiring 90 separated from the end part of the wiring part 70 A by a designated length form a bump connection part 110 .
  • An end part of the wiring part 70 A′ of the fifth wiring 70 and an end part of the wiring part 100 A of the ninth wiring 100 separated from the end part of the wiring part 70 A′ by a designated length form a bump connection part 115 .
  • An end part of a wiring part 80 A of a fifth wiring 80 and an end part of a wiring part 100 A′ of a ninth wiring 100 separated from the end part of the wiring part 80 A at a designated length form a bump connection part 120 .
  • an end part of a wiring part 80 A′ of the fifth wiring 80 and an end part of an eighth wiring 95 separated from the end part of the wiring part 80 A′ at a designated length form a bump connection part 125 .
  • bump connection parts 110 , 115 , 120 , and 125 Detailed structures of the bump connection parts 110 , 115 , 120 , and 125 are discussed below. Stud bumps as connection members can be applied to the bump connection parts 110 , 115 , 120 , and 125 . A necessary wiring among the fifth through ninth wirings 70 , 80 , 90 , 95 and 100 can be selected for connection.
  • the bump connection parts 110 and 120 are selected from the bump connection parts 110 , 115 , 120 , and 125 .
  • a stud bump 130 a is formed so that the end part of the wiring part 70 A of the fifth wiring 70 forming the bump connection part 110 is bridged with the end part of the seventh wiring 90 .
  • a stud bump 130 b is formed so that the end part of the wiring part 80 A of the fifth wiring 80 forming the bump connection part 120 is bridged with (connected to) the end part of the wiring part 100 A′ of the ninth wiring 100 .
  • the wiring part 70 A of the fifth wiring 70 and the seventh wiring 90 are connected.
  • the wiring part 80 A of the sixth wiring 80 and the wiring part 100 A′ of the ninth wiring 100 are connected.
  • first bonding pad 51 C and the second bonding pad 52 C can be electrically connected, and the first bonding pad 51 D and the second bonding pad 52 D can be electrically connected.
  • the stud bumps are not formed at the bump connection parts 115 and 125 . Therefore, the wiring part 70 A′ of the fifth wiring 70 and the wiring part 100 A of the ninth wiring 100 are not electrically connected. In addition, the wiring part 80 A′ of the sixth wiring 80 and the eighth wiring 95 are not electrically connected.
  • the first bonding pad 51 C and the second bonding pad 52 D is not electrically connected, and the first bonding pad 51 D and the second bonding pad 52 C are not electrically connected.
  • a stud bump is used as the connection member.
  • equipment such as wire bonder or bump bonder and a material such as a metal wiring made of gold used in a manufacturing process of a semiconductor device can be used, special equipment and material are not necessary and therefore high productivity can be achieved. Therefore, it is possible to form the connection member easily and at low cost.
  • connection member is not limited to the stud bump.
  • connection member for example, a conductive resin paste containing fine particles such as silver, copper or carbon can be used.
  • a conductive resin paste containing fine particles such as silver, copper or carbon can be used.
  • the bonding pads 51 C or 51 D and 52 C or 52 D can be optionally selected. Based on the selection of the bonding pads, to which of the connection parts 110 , 115 , 120 and 125 the connection member such as the stud bumps are to be arranged, may be determined. Hence, it is possible to improve the degree of freedom of connection of the plural separated connection parts in the relay board.
  • a tenth wiring 150 is connected to the first bonding pad 51 E.
  • a bonding wire connection part 60 c is formed at an end part of the tenth wiring 150 , as well as a bonding wire connection part 60 a being formed at the end of the second wiring 56 .
  • the bonding wire connection part 60 c and the second bonding pad 52 E or 52 E′ can be selectively connected by using a bonding wire as the connection member. That is, depending on the arrangement of the pads of the semiconductor chip and the wiring board or the lead frame, the bonding pad 52 E or 52 E′ can be optionally selected.
  • a bonding wire connection part 60 c and the second bonding pad 52 E are connected by the bonding wire 155 . More specifically, at the second bonding part 52 E, the bonding wire 155 is connected end to end at a part where the bonding wire 54 is connected. On the other hand, the bonding wire 155 is not connected to the second bonding pad 52 E′, so that the second bonding pad 52 E′ functions as a preliminary bonding pad.
  • second bonding pads 52 A′, 52 B′ and 52 E′ are each selected as a second bonding pad to which a bonding wire 54 is connected
  • the second bonding pad 52 D is selected as a pad to which a first bonding pad 51 C is electrically connected
  • the second bonding pad 52 C is selected as a pad to which a first bonding pad 51 D is electrically connected
  • FIG. 5 is a plan view showing a second schematic structure of the relay board 50 of the first embodiment of the present invention.
  • the second bonding pad 52 A is selected and the bonding wire is connected to the second bonding pad 52 A.
  • the first wiring 55 electrically connecting the first bonding pad 51 A and the second bonding pad 52 A or 52 A′ splits on the way. Therefore, it is possible to select either of the second bonding pads 52 A and 52 A′ having the same electric potentials. In the example shown in FIG. 5 , the second bonding pad 52 A′ is selected and the bonding wire 54 is connected to the second bonding pad 52 A′. On the other hand, the second bonding pad 52 A functions as a preliminary bonding pad.
  • the bonding wire connection part 60 a formed at the end part of the second wiring 56 connecting to the first bonding pad 51 B and the bonding wire connection part 60 b formed at the end part of the third wiring 57 connecting to the second bonding pad 52 B can be electrically connected by the bonding wire 61 .
  • the second bonding pad 52 B′ is selected as a second bonding pad electrically connecting to the first bonding pad 51 B.
  • the bonding wire 61 connects the bonding wire connection part 60 a formed at the end part of the second wiring 56 connecting to the first bonding pad 51 B and the bonding wire connection part 60 d formed at the end part of the fourth wiring 58 connecting to the second bonding pad 52 B′.
  • the second bonding pad 52 B functions as a preliminary bonding pad.
  • the bump connection parts 110 and 120 are selected from the bump connection parts 110 , 115 , 120 and 125 and the stud bumps 130 are formed at the bump connection parts 110 and 120 .
  • the wiring part 70 A of the fifth wiring 70 and the seventh wiring 90 are connected.
  • the wiring part BOA of the sixth wiring 80 and the wiring part 100 A′ of the ninth wiring 100 are connected.
  • the first bonding pad 51 C and the second bonding pad 52 C are electrically connected and the first bonding pad 51 D and the second bonding pad 52 D are electrically connected.
  • first bonding pad 51 D and the second bonding pad 52 C are electrically connected and the first bonding pad 51 C and the second bonding pad 52 D are electrically connected.
  • the stud bumps 130 c and 130 d are formed at the bump connection parts 115 and 125 .
  • the wiring part 70 A′ of the fifth wiring 70 and the wiring part 100 A of the ninth wiring 100 can be electrically connected.
  • the wiring part 80 A′ of the sixth wiring 80 and the eighth wiring 95 can be electrically connected.
  • the stud bumps are not formed at the bump connection parts 110 and 120 . Therefore, the wiring part 70 A of the fifth wiring 70 and the seventh wiring 90 are not electrically connected. In addition, the wiring part 80 A of the sixth wiring 80 and the wiring part 100 A′ of the ninth wiring 100 are not electrically connected. As a result of this, the first bonding pad 51 C and the second bonding pad 52 C are not electrically connected and the first bonding pad 51 D and the second bonding pad 52 D are not electrically connected.
  • the bonding wire connection part 60 formed at the end part of the tenth wiring 150 and the second bonding pad 52 E can be electrically connected by the bonding wire 155 .
  • the second bonding pad 52 E′ is selected.
  • bonding wire 54 is stuck on and connected to the bonding wire 155 .
  • the bonding wire is not connected to the second bonding pad 52 E.
  • the second bonding pad 52 E functions as a preliminary pad.
  • a connection structure of the bonding wires 54 and 155 to the second bonding pad 52 E′ is discussed below.
  • the relay board 50 of the present invention and relay boards having other structures as discussed below can be made of a material the same as the semiconductor chip provided in the semiconductor device where the relay board is mounted, such as silicon (Si).
  • a wiring, a bonding pad or the like is formed on the silicon substrate through the same process as the manufacturing process for the semiconductor chip.
  • an insulation layer such as a silicon oxide film is formed on a main surface of a silicon substrate and a metal layer such as an aluminum (Al) layer is formed on the insulation layer.
  • a metal layer such as an aluminum (Al) layer is formed on the insulation layer.
  • the relay board with high productivity and minute wiring can be easily formed. Because of this, in the relay board, it is possible to form wiring having a complex connection structure at a high yield.
  • the coefficient of thermal expansion of the relay board is the same as the coefficient of thermal expansion of the semiconductor chip. In a case of a semiconductor device having a structure where the relay board comes in contact with the semiconductor chip, it is possible to avoid generation of strain or stress concentration due to the difference between the coefficients of the thermal expansion so that it is possible to improve the reliability of the semiconductor device.
  • the material for the relay board is not limited to being the same as the material for the semiconductor chip.
  • a printed board made of glass epoxy, glass Bismaleimide-Triazine (BT), or the like may be used for the relay board.
  • BT glass Bismaleimide-Triazine
  • Such a printed board is relatively economical and the coefficient of thermal expansion of the relay board can be made the same as or similar to the coefficient of thermal expansion of the wiring board of the semiconductor device. Hence, it is possible to reduce or avoid generation of strain or stress concentration due to the difference of the coefficients of thermal expansion.
  • a flexible tape substrate such as a polyimide film can be used as such a relay board.
  • a tape substrate it is possible to form minute wiring and make the film thin.
  • an influence of strain due to the difference of the coefficients of thermal expansion may not be given.
  • An insulating resin film where a wiring circuit is formed may be used as the material for the relay board.
  • connection part Next, a structure of the connection part is discussed.
  • FIG. 6 is a view showing a structure of the bonding wire connection part 60 .
  • FIG. 6 -(A) is a plan view of the bonding wire connection part 60 .
  • FIG. 6 -(B) is a cross-sectional view taken along X-X′ in FIG. 6 -(A).
  • a wiring (for example a second wiring 56 shown in FIG. 4 ) is formed on the insulation film 160 of the relay board 50 .
  • the insulation layer 160 may be made of a silicon oxide film, for example, formed on the semiconductor substrate made of silicon, for example.
  • the relay board 50 is a printed board made of glass epoxy or a polyimide film
  • a basic material itself of the relay board 50 is made of insulation material and a basic material part corresponds to the insulation layer.
  • the wiring is shown by a dotted line.
  • the wiring may be made of metal such as aluminum, copper, gold, silver or nickel or an alloy of any thereof. Particularly, it is preferable that the wiring be made of copper if the relay board is a printed board made of glass epoxy or a polyimide film.
  • the width of an end part of the wiring 56 is formed so as to be greater than widths of other parts of the wiring 56 .
  • FIG. 7 is a plan view showing a configuration of the end part of the wiring in another example of the bonding wire connection part.
  • FIG. 8 is a plan view showing a configuration of an end part of a wiring in another example of the bonding wire connection part.
  • the configuration of the end part of the wiring is not limited to the configuration shown in FIG. 6 -(A).
  • the end part may be formed so that the width of the end part is the same as the width of other parts of the wiring.
  • the end part may have a circular-shaped configuration having a diameter greater than the width of other parts of the wiring.
  • an insulation film 162 is formed on the wiring (for example the second wiring 56 ).
  • a resin film such as polyimide film or epoxy film, a silicon oxide film, a silicon nitride film, or the like can be used.
  • a multi-layer film may be formed. For example, a double-layer structure of silicon oxide film and silicon nitride film may be used.
  • a metal plating part 164 is formed in the opening part.
  • a main surface of the metal plating part 164 has a substantially rectangular-shaped configuration.
  • metal plating part 164 For example, gold plating, a double-layer plating of nickel and gold, copper plating, or the like is applied as the metal plating part 164 .
  • a bonding wire such as the bonding wire 61 is connected to the metal plating part 164 .
  • the insulation film 162 or the metal plating part 164 is not always required to be provided.
  • FIG. 9 is a view showing a structure of the bump connection part 110 .
  • FIG. 9 -(A) is a plan view of the bump connection part 110 .
  • FIG. 9 -(B) is a cross-sectional view taken along X-X′ in FIG. 9 -(A).
  • two wirings for example the wiring part 70 A of the fifth wiring 70 and the seventh wiring 90 in a structure shown in FIG. 4 , are provided on the insulation layer 160 of the relay board 50 so as to be separated from each other at a designated length and face each other.
  • the wirings are shown by dotted lines.
  • the width of an end part of the wiring namely the length in a longitudinal direction in FIG. 9 -(A), is formed so as to be greater than widths of other parts of the wiring.
  • FIG. 10 through FIG. 15 are plan views showing other examples of the configuration of the end part of the wiring of the bump bonding connection part. As shown in FIG. 10 through FIG. 15 , the configuration of the end parts of the wirings facing each other is not limited to the configuration shown in FIG. 9 -(A).
  • the end part may be formed so that the width of the end part is the same as the width of other parts of the wiring part.
  • the end parts of the wirings facing each other have, respectively, L-shaped configurations. That is, if the end part of one of the wiring is rotated 180 degrees, the configuration of the rotated end part is the same as the end part of the other wiring.
  • connection member such as the stud bump is provided in the center of a part where the end parts of the wirings facing each other are separated from each other. However, if the position where connection member is provided is shifted to an upper, lower, right or left side, a desirable connection may not be obtained.
  • end parts 75 - 1 and 75 - 2 of the wirings may be formed in line symmetry where a part where the end parts are separated is the axis of the symmetry. Furthermore, in a case where the bump connection part is formed at the end parts of three wirings, as shown in FIG. 13 or FIG.
  • end parts 76 - 1 through 76 - 3 of the wirings can be formed so that a head end part of the end part 76 - 1 of the wiring forms an acute angle on two sides and the end parts 76 - 2 and 76 - 3 of the other wirings having sides parallel to the sides of the end part 76 - 1 are close but separated at a designated length.
  • end parts 77 - 1 through 77 - 4 are formed where head ends of the end parts of the wirings are close but separated at a designated length.
  • width of the connection part be greater than the width of the wiring part and the length of a part where the end parts face each other is set to be long.
  • the insulation film 162 is formed on the wiring part 70 A of the fifth wiring 70 and the seventh wiring 90 . Discussion of the material for the insulation film 162 is omitted here.
  • An opening part is formed in a part covering the end part of the wiring of the insulation film 162 .
  • a metal plating whose main surface has a substantially rectangular-shaped configuration is provided in the opening part. Discussion of the material for the metal plating part 164 is omitted here.
  • FIG. 16 is a cross-sectional view showing the arrangement of the stud bump 130 to the bump connection part 110 .
  • the stud bump 130 is provided so that the position of the stud bump 130 is higher than the insulation film 162 covering the wirings 70 A and 90 facing each other.
  • the stud bump 130 bridges the metal plating parts 164 a and 164 b formed on the end parts of the wirings.
  • the surface of the metal plating part 164 is higher than the surface of the insulation film 162 . Hence, it is possible to securely connect the stud bump 130 and therefore a good yield of the relay board can be maintained.
  • connection member such as the stud bump 130 is formed so as to bridge the end parts of the wirings 70 A and 90 facing each other. This is shown in FIG. 16 -(B).
  • the arrangement of the stud bump may be a structure shown in FIG. 17 .
  • FIG. 17 is a cross-sectional view showing another arrangement of the stud bump 130 and the bump connection part 110 .
  • a stud bump 130 - 1 a is provided on a part where the insulation film 162 is not provided at the end part of the wiring part 70 A.
  • a stud bump 130 - 1 b is provided on a part where the insulation film 162 is not provided at the end part of the seventh wiring 90 .
  • a stud bump 130 - 2 is provided so as to bridge the stud bumps 130 - 1 a and 130 - 1 b.
  • the stud bump 130 is provided on the wirings 70 A and 90 so as to cover the insulation film 162 . Because of this, a contact area of the stud bump 130 and the wirings 70 A and 90 may be reduced so that contact strength of the stud bump 130 may be low.
  • the wire 70 A and the stud bump 130 - 1 a are connected having a sufficiently large area and the wiring 90 and the stud bump 130 - 1 b are connected having a sufficiently large area. Therefore, it is possible to obtain high connection strength and secure electrical connection between the wiring 70 A and the stud bump 130 - 1 a and high connection strength and secure electrical connection between the wiring 90 and the stud bump 130 - 1 b.
  • FIG. 18 is a view showing the connection structure of the bonding wires 54 and 155 to the second bonding pad 52 E′.
  • the bonding wire 155 is connected to a part of the second bonding pad 52 E shown in FIG. 4 which is next to a part where the bonding wire 54 is connected. On the other hand, the bonding wire 54 is stuck on the bonding wire 155 situated on the second bonding pad 52 E′ shown in FIG. 5 .
  • a stud bump 157 is provided on the second bonding pad 52 E′ provided on the relay board 50 .
  • Another end part of the bonding wire 155 connecting to the bonding wire connection part 60 c formed on the end part of the tenth wire 150 connected by the first bonding pad 51 E shown in FIG. 5 is connected on the stud bump 157 .
  • the bonding wire 54 configured to electrically connect the wiring board or the lead frame and the relay board 50 is stuck on and connected to the bonding wire 155 .
  • the bonding wires 54 and 155 are stuck and connected. Therefore, it is possible to make an area of the second bonding pad 52 E′ small and make the size of the relay board 50 small.
  • the bonding wire 155 is provided on the second bonding pad 52 E′, it is possible for the bonding wire 155 to be situated higher by the height of the stud bump 157 . Accordingly, it is possible to prevent the bonding wire 155 from dropping and coming in contact with another wire.
  • the bonding wire 155 is put between the bonding wire 54 and the stud bump 157 , it is possible to increase contact-capability between the bonding wires 54 and 155 .
  • the end part of the wiring connected by the first bonding pad 51 and the end part of the wiring connected by the second bonding pad 52 , the first bonding pad 51 and the end part of the wiring connected by the second bonding pad 52 , or the second bonding pad 52 and the end part of the wiring connected by the first bonding pad 51 are connected by the connection member such as the bonding wire or the stud bump formed on the connection part of the wiring.
  • relay board 50 Because of this, it is possible to apply the relay board 50 to a different semiconductor device. Hence, it is possible to reduce a manufacturing cost of the relay board 50 and the semiconductor device having the relay board 50 .
  • the relay board 50 can be placed in wide use. Hence, it is possible to improve the degree of freedom of the combination of the semiconductor chip mounted on the wiring board or the lead frame.
  • bonding pad of the relay board 50 the wire bonding is applied can be optionally set. Hence, it is possible to improve the yield.
  • the pad functioning as a preliminary bonding pad in a certain configuration can be used as a first or second bonding pad in a different configuration.
  • the relay board 50 can be placed in wide use. Hence, it is possible to improve the degree of freedom of the combination of the semiconductor chip mounted on the wiring board or the lead frame.
  • FIG. 19 is a first plan view of a schematic structure of the first modified example of the relay board of the embodiment of the present invention.
  • FIG. 20 is a second plan view of a schematic structure of the first modified example of the relay board of the embodiment of the present invention.
  • first bonding pads 51 - 1 through 51 - 7 are provided along a side (upper side in FIG. 19 and FIG. 20 ) of the relay board 500 whose main surface has a rectangular-shaped configuration. Bonding wires 53 configured to electrically connect the semiconductor chip and the relay board 500 are connected to the first bonding pads 51 - 1 through 51 - 7 .
  • second bonding pads 52 - 1 through 52 - 13 are provided along the other side (lower side in FIG. 19 and FIG. 20 ) of the relay board 500 .
  • Bonding wires 54 configured to electrically connect another semiconductor chip, the wiring board or the lead frame and the relay board 500 are connected to the second bonding pads 52 - 1 through 52 - 7 .
  • the bonding wires 54 are not connected to the second bonding pads 52 - 8 through 52 - 13 and the second bonding pads 52 - 8 through 52 - 13 function as preliminary bonding pads.
  • the wiring where the bump connection part is selectively provided is provided between the first bonding pad 51 and the second bonding pad 52 .
  • the wirings extending from the bonding pads 51 - 1 and 52 - 1 and the wiring 510 provided corresponding to the wirings are connected by the stud bumps 130 a and 130 b provided at the connection parts 520 and 530 , respectively, so that the bonding pads 51 - 1 and 52 - 1 can be electrically connected.
  • stud bumps 130 a and 130 b are not provided at the connection parts 520 and 530 between the wirings extending from the bonding pads 51 - 1 and 52 - 1 and the wiring 510 provided corresponding to the wirings, so that the bonding pads 51 - 1 and 52 - 1 are not electrically connected. Rather, a stud bump 130 c is provided at the connection part 550 between another wiring 540 extending from the bonding pad 51 - 1 and the wiring extending from the bonding pad 52 - 8 , so that the bonding pads 51 - 1 and 52 - 8 can be electrically connected.
  • a pitch P 2 between the bonding pads 52 - 8 and 52 - 10 in FIG. 20 is twice as long as a pitch P 1 between the bonding pads 52 - 1 and 52 - 2 in FIG. 19 .
  • a wiring extending (bending) in three or four directions is applied as a wiring connecting the bonding pad 51 and the other bonding pad 52 .
  • wirings 560 extending in four directions are provided in an area between the bonding pad 51 - 6 or 51 - 7 and bonding pad 52 - 7 or 52 - 11 .
  • End parts of the wiring 560 face end parts of the wirings extending from the bonding pads 51 - 6 , 51 - 7 , 52 - 7 , or 52 - 11 so that the end parts form four connection parts 570 a , 570 b , 570 c and 570 d .
  • By selectively providing stud bumps 130 to the connection parts it is possible to select a state where the bonding pads 51 - 7 and 52 - 7 can be electrically connected as shown in FIG. 19 or a state where the bonding pads 51 - 6 and 52 - 11 can be electrically connected as shown in FIG. 20 .
  • a wiring extending in three directions such as a T-shaped wiring 580 , it is possible to select or change corresponding bonding pads.
  • the wiring 560 extending in three or four directions, it is possible to improve the degree of freedom of the wiring way whereby the first and second bonding pads 51 and 52 are connected.
  • FIG. 21 is a plan view of a schematic structure of the second modified example of the relay board of the embodiment of the present invention.
  • first bonding pads 51 - 1 through 51 - 3 are provided along an upper side of the relay board 500 whose main surface has a rectangular-shaped configuration. Bonding wires (not shown in FIG. 21 ) configured to electrically connect the semiconductor chip and the relay board 600 are connected to the first bonding pads 51 - 1 through 51 - 3 .
  • second bonding pads 52 - 1 through 52 - 3 are provided along a lower side of the relay board 600 . Bonding wires configured to electrically connect another semiconductor chip, the wiring board or the lead frame and the relay board 600 are connected to the second bonding pads 52 - 1 through 52 - 3 .
  • the wiring is provided between the first bonding pad 51 and the second bonding pad 52 .
  • Bonding wire connection parts 610 and/or bump connection parts 620 are provided in the wirings.
  • a boning wire 615 is connected to the selected bonding wire connection part 610 or the stud bump 130 is formed at the selected bump connection part 620 , so that the first bonding pad 51 and the second bonding pad 52 can be electrically connected.
  • the wirings between the first bonding pads 51 and the second bonding pads 52 , the bonding wire connection parts 610 or the bump connection parts 620 for the wirings are provided in the relay board 600 .
  • the wire connection parts 610 or the bump connection parts 620 to be used for providing the stud bumps 130 and/or the bonding wires 615 can be selected.
  • a stud bump 130 is selected as a connection member so that a first bonding pad 51 - 1 and a second bonding pad 52 - 1 can be electrically connected; a first bonding pad 51 - 2 and a second bonding pad 52 - 2 can be electrically connected; and a first bonding pad 51 - 3 and a second bonding pad 52 - 3 can be electrically connected.
  • a stud bump 130 and a bonding wire 615 are selected as connection members so that the first bonding pad 51 - 1 and the second bonding pad 52 - 1 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 3 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 2 can be electrically connected.
  • the stud bump 130 is selected as a connection member so that the first bonding pad 51 - 1 and the second bonding pad 52 - 2 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 1 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 3 can be electrically connected.
  • the stud bump 130 is selected as a connection member so that the first bonding pad 51 - 1 and the second bonding pad 52 - 3 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 1 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 2 can be electrically connected.
  • the stud bump 130 and the bonding wire 615 are selected as connection members so that the first bonding pad 51 - 1 and the second bonding pad 52 - 2 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 3 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 1 can be electrically connected.
  • the stud bump 130 is selected as the connection member so that the first bonding pad 51 - 1 and the second bonding pad 52 - 3 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 2 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 1 can be electrically connected.
  • FIG. 22 through FIG. 24 are plan views of the schematic structure of the third modified example of the relay board of the embodiment of the present invention.
  • first bonding pads 51 - 1 through 51 - 3 are provided along an upper side of a relay board 700 whose main surface has a rectangular-shaped configuration. Bonding wires (not shown in FIG. 22 through FIG. 24 ) configured to electrically connect the semiconductor chip and the relay board 700 are connected to the first bonding pads 51 - 1 through 51 - 3 .
  • second bonding pads 52 - 1 through 52 - 3 are provided along a lower side of the relay board 600 .
  • Bonding wires (not shown in FIG. 22 through FIG. 24 ) configured to electrically connect other semiconductor chip, the wiring board or the lead frame and the relay board 700 are connected to the second bonding pads 52 - 1 through 52 - 3 .
  • wiring are provided between the first bonding pads 51 and the second bonding pads in a lattice state.
  • Bonding wire connection parts 610 and/or bump connection parts 620 are provided at the respective wirings.
  • a bonding wire 615 is provided at the bonding wire connection part 610 and a stud bump 130 is provided at the bump connection part 620 so that the first bonding pad 51 and the second bonding pad 52 can be electrically connected.
  • a pad indicated as “NC” means a preliminary bonding pad where a bonding wire configured to electrically connect other semiconductor chip, the wiring board or the lead frame and the relay board 700 is not connected.
  • the wirings between the first bonding pads 51 and the second bonding pads 52 , the bonding wire connection parts 610 or the bump connection parts 620 for the wirings are provided in the relay board 700 .
  • the wire connection parts 610 or the bump connection parts 620 to be used for providing the stud bumps 130 and/or the bonding wires 615 can be selected.
  • a first bonding pad 51 - 1 and a second bonding pad 52 - 1 can be electrically connected; a first bonding pad 51 - 2 and a second bonding pad 52 - 2 can be electrically connected; and a first bonding pad 51 - 3 and a second bonding pad 52 - 3 can be electrically connected.
  • the first bonding pad 51 - 1 and the second bonding pad 52 - 1 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 3 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 2 can be electrically connected.
  • the first bonding pad 51 - 1 and the second bonding pad 52 - 2 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 1 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 3 can be electrically connected.
  • the first bonding pad 51 - 1 and the second bonding pad 52 - 3 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 1 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 2 can be electrically connected.
  • the first bonding pad 51 - 1 and the second bonding pad 52 - 2 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 3 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 1 can be electrically connected.
  • the first bonding pad 51 - 1 and the second bonding pad 52 - 3 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 2 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 1 can be electrically connected.
  • FIG. 25 through FIG. 27 are plan views of the schematic structure of the fourth modified example of the relay board of the embodiment of the present invention.
  • first bonding pads 51 - 1 through 51 - 3 are provided along an upper side of a relay board 710 whose main surface has a rectangular-shaped configuration. Bonding wires (not shown in FIG. 25 through FIG. 27 ) configured to electrically connect the semiconductor chip and the relay board 710 are connected to the first bonding pads 51 - 1 through 51 - 3 .
  • second bonding pads 52 - 4 through 52 - 6 are provided along a left side of the relay board 710 .
  • Bonding wires (not shown in FIG. 25 through FIG. 27 ) configured to electrically connect other semiconductor chip, the wiring board or the lead frame and the relay board 700 are connected to the second bonding pads 52 - 4 through 52 - 6 .
  • an arrangement direction of the first bonding pads 51 - 1 through 51 - 3 is substantially perpendicular to an arrangement direction of the second bonding pads 52 - 4 through 52 - 6 .
  • wirings are provided between the first bonding pads 51 and the second bonding pads in a lattice state.
  • Bonding wire connection parts 610 and/or bump connection parts 620 are provided at the respective wirings.
  • a bonding wire 615 is provided at the bonding wire connection part 610 and a stud bump 130 is provided at the bump connection part 620 so that the first bonding pad 51 and the second bonding pad 52 can be electrically connected.
  • a pad indicated as “NC” means a preliminary bonding pad where a bonding wire configured to electrically connect another semiconductor chip, the wiring board or the lead frame and the relay board 710 is not connected.
  • the wirings between the first bonding pads 51 and the second bonding pads 52 , the bonding wire connection parts 610 or the bump connection parts 620 for the wirings are provided in the relay board 700 .
  • the wire connection parts 610 or the bump connection parts 620 to be used for providing the stud bumps 130 and/or the bonding wires 615 can be selected.
  • a first bonding pad 51 - 1 and a second bonding pad 52 - 4 can be electrically connected; a first bonding pad 51 - 2 and a second bonding pad 52 - 5 can be electrically connected; and a first bonding pad 51 - 3 and a second bonding pad 52 - 6 can be electrically connected.
  • the first bonding pad 51 - 1 and the second bonding pad 52 - 4 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 6 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 5 can be electrically connected.
  • the first bonding pad 51 - 1 and the second bonding pad 52 - 5 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 4 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 6 can be electrically connected.
  • the first bonding pad 51 - 1 and the second bonding pad 52 - 6 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 4 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 5 can be electrically connected.
  • the first bonding pad 51 - 1 and the second bonding pad 52 - 5 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 6 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 4 can be electrically connected.
  • the first bonding pad 51 - 1 and the second bonding pad 52 - 6 can be electrically connected; the first bonding pad 51 - 2 and the second bonding pad 52 - 5 can be electrically connected; and the first bonding pad 51 - 3 and the second bonding pad 52 - 4 can be electrically connected.
  • FIG. 28 and FIG. 29 are plan views of the schematic structure of the fifth modified example of the relay board of the embodiment of the present invention.
  • first bonding pads 51 - 4 through 51 - 6 are provided along a longitudinal side of a relay board 720 whose main surface has a rectangular-shaped configuration. Bonding wires (not shown in FIG. 28 and FIG. 29 ) configured to electrically connect the semiconductor chip and the relay board 720 are connected to the first bonding pads 51 - 4 through 51 - 6 .
  • a second bonding pad 52 - 7 is provided between the first bonding pads 51 - 4 and 51 - 5 ; a second bonding pad 52 - 8 is provided between the first bonding pads 51 - 5 and 51 - 6 ; and a second bonding pad 52 - 9 is provided at a right side of the first bonding pad 51 - 6 .
  • Bonding wires (not shown in FIG. 28 and FIG. 29 ) configured to electrically connect another semiconductor chip, the wiring board or the lead frame and the relay board 720 are connected to the second bonding pads 52 - 7 through 52 - 9 .
  • first bonding pads 51 - 4 through 51 - 6 and the second bonding pads 52 - 7 through 52 - 9 are arranged in a straight line state in the example shown in FIG. 28 and FIG. 29 .
  • wirings are provided between the first bonding pads 51 and the second bonding pads 52 in a lattice state.
  • Bonding wire connection parts 610 and/or bump connection parts 620 are provided at the respective wirings.
  • a bonding wire 615 is provided at the bonding wire connection part 610 and a stud bump 130 is provided at the bump connection part 620 so that the first bonding pad 51 and the second bonding pad 52 can be electrically connected.
  • the wirings between the first bonding pads 51 and the second bonding pads 52 , the bonding wire connection parts 610 or the bump connection parts 620 for the wirings are provided in the relay board 720 .
  • the wire connection parts 610 or the bump connection parts 620 to be used for providing the stud bumps 130 and/or the bonding wires 615 can be selected.
  • a first bonding pad 51 - 4 and a second bonding pad 52 - 7 can be electrically connected; a first bonding pad 51 - 5 and a second bonding pad 52 - 8 can be electrically connected; and a first bonding pad 51 - 6 and a second bonding pad 52 - 9 can be electrically connected.
  • the first bonding pad 51 - 4 and the second bonding pad 52 - 7 can be electrically connected; the first bonding pad 51 - 5 and the second bonding pad 52 - 9 can be electrically connected; and the first bonding pad 51 - 6 and the second bonding pad 52 - 8 can be electrically connected.
  • the first bonding pad 51 - 4 and the second bonding pad 52 - 8 can be electrically connected; the first bonding pad 51 - 5 and the second bonding pad 52 - 7 can be electrically connected; and the first bonding pad 51 - 6 and the second bonding pad 52 - 9 can be electrically connected.
  • the first bonding pad 51 - 4 and the second bonding pad 52 - 9 can be electrically connected; the first bonding pad 51 - 5 and the second bonding pad 52 - 7 can be electrically connected; and the first bonding pad 51 - 6 and the second bonding pad 52 - 8 can be electrically connected.
  • the first bonding pad 51 - 4 and the second bonding pad 52 - 8 can be electrically connected; the first bonding pad 51 - 5 and the second bonding pad 52 - 9 can be electrically connected; and the first bonding pad 51 - 6 and the second bonding pad 52 - 7 can be electrically connected.
  • the first bonding pad 51 - 4 and the second bonding pad 52 - 9 can be electrically connected; the first bonding pad 51 - 5 and the second bonding pad 52 - 8 can be electrically connected; and the first bonding pad 51 - 6 and the second bonding pad 52 - 7 can be electrically connected.
  • FIG. 30 is a view showing a first example of a semiconductor device having a relay board of the embodiment of the present invention.
  • a semiconductor device 900 is a so-called Ball Grid Array (BGA) package type semiconductor device.
  • BGA Ball Grid Array
  • a first semiconductor chip 6 is mounted on a wiring board 4 having a lower surface where plural spherical shaped electrodes (bumps) 2 are formed.
  • the first semiconductor chip 6 is adhered and fixed to the wiring board 4 by an adhesive 10 A.
  • a second semiconductor chip 8 and a relay board 750 are provided side by side on the first semiconductor chip 6 .
  • the second semiconductor chip 8 and the relay board 750 are adhered and fixed to the first semiconductor chip 6 by adhesives 10 B and 10 C.
  • An electrode of the wiring board 4 and an electrode of the first semiconductor chip 6 are connected by a bonding wire 551 .
  • the electrode of the wiring board 4 and an electrode of the second semiconductor chip 8 are connected by the bonding wire 551 .
  • the electrode of the wiring board. 4 and an electrode of the relay board 750 are connected by the bonding wire 551 .
  • the electrode of the semiconductor chip 6 and the electrode of the second semiconductor chip 8 are connected by the bonding wire 551 .
  • the electrode of the relay board 750 and the electrode of the first semiconductor chip 6 are connected by the bonding wire 551 .
  • the electrode of the relay board 750 and the electrode of the second semiconductor chip 8 are connected by the bonding wire 551 .
  • the first semiconductor chip 6 , the second semiconductor chip 8 , the relay board 750 and the bonding wires 551 are sealed by sealing resin so that the semiconductor device 900 is formed.
  • An organic substrate made of, for example glass epoxy, glass Bismaleimide-Triazine (BT), or polyimide or an inorganic substrate made of, for example, ceramic, glass, or silicon may be used as the wiring board 4 .
  • a resin adhesive paste or film made of, for example, epoxy or polyimide may be used as the adhesive 10 .
  • the-present invention is not limited to the above-mentioned example.
  • FIG. 31 is a view showing a second example of a semiconductor device having the relay board of the embodiment of the present invention.
  • a semiconductor device 910 has a structure where a semiconductor chip 8 and a relay board 750 are provided side by side on a dye pad (dye stage) 556 of a lead frame made of iron, copper, or the like.
  • the semiconductor chip 8 is adhered and fixed to the dye pad 556 by an adhesive 10 A.
  • the relay board 750 is adhered and fixed to the dye pad 556 by an adhesive 10 C.
  • An electrode of the semiconductor chip 8 and an electrode of the relay board 750 are connected by the bonding wire 551 .
  • An inner lead part 557 of the lead frame and the electrode of the relay board 750 are connected by the bonding wire 551 .
  • the electrode of the semiconductor chip 8 and the inner lead part 557 of the lead frame are connected by the bonding wire 551 .
  • the semiconductor chip 8 , the relay board 750 , the inner lead part 557 and the bonding wires 551 are sealed by sealing resin so that the semiconductor device 910 is formed.
  • the same material for the adhesive 10 as the material discussed above with reference to FIG. 30 can be used.
  • FIG. 32 is a view showing a third example of a semiconductor device having the relay board of the embodiment of the present invention.
  • a semiconductor device 920 has a structure where a relay board 750 is adhered and fixed on the wiring board 4 by adhesive 10 C.
  • a first semiconductor chip 6 is flip chip connected on the relay board 750 and adhered and fixed to the relay board 750 by the adhesive 10 D.
  • An electrode of the wiring board 4 and an electrode of the relay board 750 are connected by the bonding wire 551 .
  • the semiconductor chip 6 , the relay board 750 , and the bonding wires 551 are sealed by sealing resin 9 so that the semiconductor device 920 is formed.
  • the semiconductor chip 6 is flip chip connected to the relay board 750 .
  • the height of the semiconductor device 920 can be reduced so that it is possible to make the semiconductor device where the relay board is mounted thin.
  • FIG. 33 is a view showing a fourth example of a semiconductor device having the relay board of the embodiment of the present invention.
  • a semiconductor device 930 has a structure where an opening part is formed in the substantially center part of the wiring board 4 .
  • a relay board 750 having an area larger than the opening part covers the opening part.
  • the semiconductor chip 6 is received in the opening part.
  • An electrode of the semiconductor chip is connected and fixed to a corresponding electrode of the relay board 750 .
  • Another electrode of the relay board 750 is connected to a corresponding electrode of the wiring board 4 .
  • the semiconductor chip 6 and the relay board 750 are adhered and fixed by the adhesive 10 E.
  • the relay board 750 and the wiring board 4 are adhered and fixed by the adhesive 10 E.
  • a bonding wire is not used in the semiconductor device 930 shown in FIG. 33 .
  • the semiconductor device 560 shown in FIG. 32 it is possible to obtain good electrical connection and the height of the semiconductor device 930 can be reduced so that it is possible to make the semiconductor device where the relay board is mounted thin.
  • FIG. 34 is a view showing a fifth example of a semiconductor device having a relay board of the embodiment of the present invention.
  • a semiconductor device 940 has a structure where a relay board 750 is adhered and fixed on a semiconductor chip 6 by the adhesive 10 C.
  • the semiconductor chip 6 is adhered and fixed on a wiring board 4 by the adhesive 10 A.
  • An electrode of the wiring board 4 and an electrode of the first semiconductor chip 6 are connected by a bonding wire 551 .
  • the electrode of the wiring board 4 and a relay board 750 are connected by the bonding wire 551 .
  • the electrode of the semiconductor chip 6 and the electrode of the relay board 750 are connected by the bonding wire 551 .
  • the semiconductor chip 6 , the relay board 750 and the bonding wires 551 are sealed by sealing resin 9 so that the semiconductor device 940 is formed.
  • the external size of the relay board 750 is less than the external size of the semiconductor chip 6 .
  • the relay board is provided on the semiconductor chip 6 . Hence, it is possible to electrically connect the relay board 750 and the first semiconductor chip 6 without making the size of the semiconductor device 940 large.
  • FIG. 35 is a view showing a sixth example of a semiconductor device having a relay board of the embodiment of the present invention.
  • a semiconductor device 950 has a structure where two relay boards 750 are adhered and fixed on a semiconductor chip 6 by the adhesive 10 C.
  • the semiconductor chip 6 is adhered and fixed on a wiring board 4 by the adhesive 10 A.
  • An electrode pad 7 of the semiconductor chip 6 is provided in the substantially center part of the semiconductor chip 6 . Electrodes of the relay boards 750 provided separately are connected to the electrode pad 7 of the semiconductor chip 6 and the wiring board 4 .
  • the semiconductor chip 6 , two relay boards 750 and the bonding wires 551 are sealed by sealing resin 9 so that the semiconductor device 950 is formed.
  • the relay boards 750 are provided on the semiconductor chip 6 so as to be received in the external configuration of the semiconductor chip 6 . Hence, it is possible to electrically connect the relay board 750 and the first semiconductor chip 6 without making the size of the semiconductor device 950 large.
  • FIG. 36 is a view showing a seventh example of a semiconductor device having a relay board of the embodiment of the present invention.
  • the semiconductor device 960 has a structure where the relay board 750 is adhered and fixed to the semiconductor chip 6 by the adhesive 10 C and the semiconductor chip 6 is adhered and fixed to the wiring board 4 by the adhesive 10 A.
  • Two semiconductor chips 8 a and 8 b are separately adhered and fixed on the relay board 750 by the adhesive 10 E. That is, the semiconductor chips 8 a and 8 b are mounted on the semiconductor chip 6 via the relay board 750 .
  • the wiring board 4 and the semiconductor chip 6 are connected by the bonding wire 551 .
  • the wiring board 4 and the relay board 750 are connected by the bonding wire 551 .
  • the relay board 750 and the semiconductor chips 8 a and 8 b are connected by the bonding wire 551 .
  • the semiconductor chip 6 , the semiconductor chips 8 a and 8 b , the relay board 750 and the bonding wires 551 are sealed by sealing resin 9 so that the semiconductor device 960 is formed.
  • the relay board 750 of the present invention which can be placed in wide use is provided between the semiconductor chip 3 and semiconductor chips 8 a and 8 b . Hence, it is possible to improve the degree of freedom of combinations of the stuck semiconductor chips.
  • FIG. 37 and FIG. 38 are views showing an eighth example of a semiconductor device having a relay board of the embodiment of the present invention. More specifically, FIG. 37 is a plan view of a semiconductor device 970 .
  • FIG. 38 -(A) is a cross-sectional view taken along line X-X′ of FIG. 37 .
  • FIG. 38 -(B) is a cross-sectional view taken along line Y-Y′ of FIG. 37 .
  • FIG. 37 shows the semiconductor device 970 in a state where the sealing resin 9 shown in FIG. 38 is not provided.
  • the first semiconductor chip 651 is adhered and fixed on the wiring board 4 by the adhesive 10 A.
  • the relay board 660 of the present invention is adhered and fixed on the first semiconductor chip 651 by the adhesive 10 C.
  • the second semiconductor chip 652 is adhered and fixed on the relay board 660 by the adhesive 10 B. Therefore, the relay board 660 is put between the first semiconductor chip 651 and the second semiconductor chip 652 .
  • the first semiconductor chip 651 , the second semiconductor chip 652 , the relay board 660 and the bonding wires 551 are sealed by sealing resin 9 so that the semiconductor device 970 is formed.
  • the length of the relay board 660 in an X-X′ direction is less than lengths of the first semiconductor chip 651 and the second semiconductor chip 652 in the X-X′ direction (See FIG. 38 -(A)).
  • the length of the relay board 660 in the Y-Y′ direction is greater than the lengths of the first semiconductor chip 651 and the second semiconductor chip 652 in the Y-Y′ direction (See FIG. 38 -(B)).
  • a bonding pad 661 provided in the vicinity of an end part of the relay board 660 in the Y-Y′ direction is connected to the wiring board 4 and the second semiconductor chip 652 by the bonding wire 551 .
  • the relay board 660 forms a space S between the first semiconductor chip 651 and the second semiconductor chip 652 .
  • the relay board 660 provided between the semiconductor chip 651 and the second semiconductor chip 652 is positioned so as not to overlap an electrode pad 653 provided in the vicinity of an end part of the first semiconductor chip 651 (See FIG. 38 -(A)) in the X-X′ direction.
  • the relay board 660 is positioned so as to overlap the electrode pad 653 where the relay board 660 is separated from the second semiconductor chip 652 at a designated length.
  • the second semiconductor chip 652 and the wiring board 4 are connected by the bonding wire 551 .
  • the electrode pad 653 of the first semiconductor chip 651 and an electrode pad of the wiring board 4 are connected by the bonding wire 654 .
  • the relay board 660 forms the space S between the first semiconductor chip 651 and the second semiconductor chip 652 . Therefore, it is possible to connect the first semiconductor chip 651 and the wiring board 4 without making the bonding wire 654 contact the second semiconductor chip 652 situated above the bonding wire 654 .
  • connection member may be provided at the connection part provided in the relay board after the relay board is provided on the semiconductor chip or the wiring board.
  • the relay board may be provided on the semiconductor chip or the wiring board after the connection member is provided on the relay board in advance.
  • connection member be provided on the relay board after the relay board is provided on the semiconductor chip or the wiring board. As a result of this, it is possible to improve the yield.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
US11/295,472 2005-09-30 2005-12-07 Relay board and semiconductor device having the relay board Abandoned US20070075437A1 (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070132102A1 (en) * 2005-12-08 2007-06-14 Fujitsu Limited Relay board provided in semiconductor device, semiconductor device, and manufacturing method of semiconductor device
US20080136011A1 (en) * 2006-12-11 2008-06-12 Nec Electronics Corporation Semiconductor device
US20090001530A1 (en) * 2007-06-18 2009-01-01 Kabushiki Kaisha Toshiba Semiconductor device
US20090014895A1 (en) * 2007-07-09 2009-01-15 Samsung Electronics Co, Ltd. Interposer chip, method of manufacturing the interposer chip, and multi-chip package having the interposer chip
US8598709B2 (en) 2010-08-31 2013-12-03 Infineon Technologies Ag Method and system for routing electrical connections of semiconductor chips
US10051739B2 (en) 2015-01-05 2018-08-14 Crrc Qingdao Sifang Co., Ltd. Control relay board for railway vehicle
CN110010583A (zh) * 2015-04-28 2019-07-12 东芝存储器株式会社 半导体装置

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4873635B2 (ja) * 2007-01-17 2012-02-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR101185886B1 (ko) 2007-07-23 2012-09-25 삼성전자주식회사 유니버설 배선 라인들을 포함하는 반도체 칩, 반도체패키지, 카드 및 시스템
KR101490334B1 (ko) 2008-04-30 2015-02-06 삼성전자주식회사 인터포저 칩 및 인터포저 칩을 갖는 멀티-칩 패키지
US8018037B2 (en) * 2009-04-16 2011-09-13 Mediatek Inc. Semiconductor chip package
JP5411082B2 (ja) * 2010-08-03 2014-02-12 日本電信電話株式会社 Mems素子用パッケージ
KR101737053B1 (ko) * 2010-12-31 2017-05-18 삼성전자주식회사 반도체 패키지
JP2013197331A (ja) * 2012-03-21 2013-09-30 Sumitomo Electric Ind Ltd 半導体デバイス
WO2014032228A1 (en) * 2012-08-28 2014-03-06 Sandisk Semiconductor (Shanghai) Co., Ltd. Bridge ball wire bonding
CN105514074B (zh) * 2015-12-01 2018-07-03 上海伊诺尔信息技术有限公司 智能卡芯片封装结构及其制造方法
JP2022035627A (ja) * 2020-08-21 2022-03-04 新光電気工業株式会社 半導体装置及びその製造方法
WO2023223829A1 (ja) * 2022-05-19 2023-11-23 ローム株式会社 半導体装置

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3801388A (en) * 1971-09-30 1974-04-02 Sony Corp Printed circuit board crossover and method for manufacturing the same
US4694572A (en) * 1986-06-13 1987-09-22 Tektronix, Inc. Printed polymer circuit board method
US5357051A (en) * 1994-01-31 1994-10-18 Hwang Richard H Printed circuit board for reducing radio frequency interferences
US5541814A (en) * 1993-10-08 1996-07-30 Quick Technologies Ltd. Personalizable multi-chip carrier including removable fuses
US5552966A (en) * 1990-12-20 1996-09-03 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board and method for manufacturing same
US5598031A (en) * 1993-06-23 1997-01-28 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
US6740821B1 (en) * 2002-03-01 2004-05-25 Micron Technology, Inc. Selectively configurable circuit board
US6917120B2 (en) * 2000-08-03 2005-07-12 Minebea Co., Ltd. Microchip controller board
US6958532B1 (en) * 1999-06-18 2005-10-25 Nec Electronics Corporation Semiconductor storage device
US6979905B2 (en) * 2003-01-29 2005-12-27 Sharp Kabushiki Kaisha Semiconductor device
US7199304B2 (en) * 2002-09-04 2007-04-03 Intel Corporation Configurable microelectronic package using electrically conductive material

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61146877A (ja) 1984-12-12 1986-07-04 三菱レイヨン株式会社 繊維構造品の制電,撥水撥油処理方法
JPH02109344A (ja) 1988-10-18 1990-04-23 Mitsubishi Electric Corp 半導体装置
JPH02216839A (ja) 1989-02-17 1990-08-29 Nec Corp 半導体装置
JPH0513490A (ja) 1991-07-02 1993-01-22 Nec Corp 樹脂封止型半導体装置
JPH0595074A (ja) * 1991-10-02 1993-04-16 Seiko Epson Corp 半導体装置
WO1995000973A1 (en) 1993-06-23 1995-01-05 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
JPH08153939A (ja) 1994-11-30 1996-06-11 Seikosha Co Ltd モード選択可能な回路基板の構成
JPH0998020A (ja) 1995-10-03 1997-04-08 Matsushita Electric Ind Co Ltd 発振器
JPH11265975A (ja) 1998-03-17 1999-09-28 Mitsubishi Electric Corp 多層化集積回路装置
JP3588793B2 (ja) 1998-06-29 2004-11-17 株式会社安川電機 制御盤更新方法
JP3765952B2 (ja) * 1999-10-19 2006-04-12 富士通株式会社 半導体装置
JP2001127246A (ja) 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
JP2001257307A (ja) 2000-03-09 2001-09-21 Sharp Corp 半導体装置
JP3948292B2 (ja) * 2002-02-01 2007-07-25 株式会社日立製作所 半導体記憶装置及びその製造方法
US20030230796A1 (en) * 2002-06-12 2003-12-18 Aminuddin Ismail Stacked die semiconductor device
JP4068974B2 (ja) 2003-01-22 2008-03-26 株式会社ルネサステクノロジ 半導体装置
JP2004356264A (ja) 2003-05-28 2004-12-16 Hitachi Ltd 受動部品内蔵基板及びそれを用いた高周波回路モジュール
JP3994084B2 (ja) * 2003-12-22 2007-10-17 沖電気工業株式会社 半導体装置

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3801388A (en) * 1971-09-30 1974-04-02 Sony Corp Printed circuit board crossover and method for manufacturing the same
US4694572A (en) * 1986-06-13 1987-09-22 Tektronix, Inc. Printed polymer circuit board method
US5552966A (en) * 1990-12-20 1996-09-03 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board and method for manufacturing same
US5598031A (en) * 1993-06-23 1997-01-28 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
US5541814A (en) * 1993-10-08 1996-07-30 Quick Technologies Ltd. Personalizable multi-chip carrier including removable fuses
US5357051A (en) * 1994-01-31 1994-10-18 Hwang Richard H Printed circuit board for reducing radio frequency interferences
US6958532B1 (en) * 1999-06-18 2005-10-25 Nec Electronics Corporation Semiconductor storage device
US6917120B2 (en) * 2000-08-03 2005-07-12 Minebea Co., Ltd. Microchip controller board
US6740821B1 (en) * 2002-03-01 2004-05-25 Micron Technology, Inc. Selectively configurable circuit board
US7199304B2 (en) * 2002-09-04 2007-04-03 Intel Corporation Configurable microelectronic package using electrically conductive material
US6979905B2 (en) * 2003-01-29 2005-12-27 Sharp Kabushiki Kaisha Semiconductor device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070132102A1 (en) * 2005-12-08 2007-06-14 Fujitsu Limited Relay board provided in semiconductor device, semiconductor device, and manufacturing method of semiconductor device
US7973404B2 (en) * 2005-12-08 2011-07-05 Fujitsu Semiconductor Limited Relay board provided in semiconductor device, semiconductor device, and manufacturing method of semiconductor device
US20080136011A1 (en) * 2006-12-11 2008-06-12 Nec Electronics Corporation Semiconductor device
US20090001530A1 (en) * 2007-06-18 2009-01-01 Kabushiki Kaisha Toshiba Semiconductor device
US7989932B2 (en) * 2007-06-18 2011-08-02 Kabushiki Kaisha Toshiba Semiconductor device
US20090014895A1 (en) * 2007-07-09 2009-01-15 Samsung Electronics Co, Ltd. Interposer chip, method of manufacturing the interposer chip, and multi-chip package having the interposer chip
US7667331B2 (en) 2007-07-09 2010-02-23 Samsung Electronics Co., Ltd. Interposer chip, method of manufacturing the interposer chip, and multi-chip package having the interposer chip
KR101376487B1 (ko) 2007-07-09 2014-03-20 삼성전자주식회사 인터포저 칩, 그의 제조 방법 및 인터포저 칩을 갖는멀티-칩 패키지
US8598709B2 (en) 2010-08-31 2013-12-03 Infineon Technologies Ag Method and system for routing electrical connections of semiconductor chips
DE102011053161B4 (de) * 2010-08-31 2021-01-28 Infineon Technologies Ag Verfahren und system zum führen von elektrischen verbindungen von halbleiterchips
US10051739B2 (en) 2015-01-05 2018-08-14 Crrc Qingdao Sifang Co., Ltd. Control relay board for railway vehicle
CN110010583A (zh) * 2015-04-28 2019-07-12 东芝存储器株式会社 半导体装置

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US20100258926A1 (en) 2010-10-14
KR100724001B1 (ko) 2007-06-04

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