WO2014032228A1 - Bridge ball wire bonding - Google Patents

Bridge ball wire bonding Download PDF

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Publication number
WO2014032228A1
WO2014032228A1 PCT/CN2012/080668 CN2012080668W WO2014032228A1 WO 2014032228 A1 WO2014032228 A1 WO 2014032228A1 CN 2012080668 W CN2012080668 W CN 2012080668W WO 2014032228 A1 WO2014032228 A1 WO 2014032228A1
Authority
WO
WIPO (PCT)
Prior art keywords
bonding
ball
bump
semiconductor device
bonding pad
Prior art date
Application number
PCT/CN2012/080668
Other languages
French (fr)
Inventor
Li Wang
Wenqiang ZHU
Peter NIAN
Robertito Piaduche
Aj ARMENTANO
Jianjian ZHANG
Original Assignee
Sandisk Semiconductor (Shanghai) Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Semiconductor (Shanghai) Co., Ltd. filed Critical Sandisk Semiconductor (Shanghai) Co., Ltd.
Priority to PCT/CN2012/080668 priority Critical patent/WO2014032228A1/en
Publication of WO2014032228A1 publication Critical patent/WO2014032228A1/en

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present technology relates to semiconductor devices.
  • the semiconductor device 100 comprises a substrate 110 and a semiconductor die 120 such as an ASIC (Application Specific Integrated Circuit) die and memory dies like flash, SRAM and DDR.
  • the substrate 110 comprises a plurality of bonding fingers 114 aligned along an edge of the substrate 110 in the plan view of FIG. 1A.
  • the semiconductor die 120 comprises a plurality of bonding pads 124 aligned also along an edge of the semiconductor die 120 in the plan view of FIG. IB.
  • the leftmost two adjacent bonding pads 124 are connected to a leftmost bonding finger 114 via two separate bonding wires 140 by a wire bonding process.
  • a length of wire typically gold
  • the wire protrudes through a tip of the capillary, where a high- voltage electric charge is applied to the wire from a transducer associated with the capillary tip.
  • the capillary is lowered to the bonding pad 124 and ultrasonic energy is applied by the transducer.
  • the bonding pad 124 can also be heated to facilitate bonding.
  • the combined heat, pressure, and ultrasonic energy create a weld between the gold ball 128 and the bonding pad 124.
  • the capillary is then pulled up and away from the bonding pad 124, as the wire 140 is passed out through the capillary.
  • the resulting bond on the bonding pad 124 is referred as a ball bond.
  • the capillary carrying the wire 140 moves over to the bonding finger 114 on the substrate 110, and descends and crushes the wire 140 by touching the bonding surface of the bonding finger 114 to make the wire bond again using heat, pressure and ultrasonic energy.
  • the capillary then pays out a small length of wire and tears the wire from the bonding finger 114.
  • the resulting bond on the bonding finger 114 is often referred as a wedge bond or a stitch bond.
  • FIG. 1A and FIG. IB are schematic plan view and perspective view showing a conventional semiconductor device, respectively.
  • FIG. 2A and FIG. 2B are schematic plan view and perspective view showing a semiconductor device according to a first embodiment of the present technology, respectively.
  • FIG. 2C is a schematic sectional view of the semiconductor device taken along line C- C in FIG. 2A.
  • FIG. 3 A to FIG. 3C are schematic perspective views showing a method of fabricating the semiconductor device according to the first embodiment of the present technology.
  • FIG. 4A and FIG. 4B are schematic plan view and perspective view showing a semiconductor device according to a second embodiment of the present technology, respectively.
  • FIG. 4C is a partial enlarged perspective view of the semiconductor device shown in FIG. 3B.
  • FIG. 4D is a schematic sectional view taken along line D-D in FIG. 4A.
  • FIG. 4E is a schematic enlarged partial plan view of the semiconductor device according to a second embodiment of the present technology.
  • FIG. 5A to FIG. 5C are schematic perspective views showing a method of fabricating the semiconductor device according to the second embodiment of the present technology.
  • FIG. 6A is a schematic plan view showing a semiconductor device according to a first variant of the second embodiment of the present technology.
  • FIG. 6B is a partial enlarged plan view of the semiconductor device shown in FIG. 6A.
  • FIG. 7 is a schematic perspective view of a semiconductor device according to a second variant of the second embodiment of the present technology.
  • FIGS. 2A through 7 relate to a semiconductor device. It is understood that the present technology may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the present technology to those skilled in the art. Indeed, the present technology is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. However, it will be clear to those of ordinary skill in the art that the present technology may be practiced without such specific details.
  • FIG. 2 A and FIG. 2B are schematic plan view and perspective view showing a semiconductor device 1000 according to a first embodiment of the present technology, respectively.
  • the semiconductor device 1000 comprises a substrate 1010 and a semiconductor die 1020 disposed above the substrate 1010.
  • the substrate 1010 has a substantially rectangular profile for example, as shown in the plan view of FIG. 2 A.
  • the substrate 1010 can include a wiring board such as printed circuit board (PCB).
  • the substrate 1010 comprises a plurality of bonding fingers 1014 aligned along an edge of the substrate 1010.
  • the bonding fingers 1014 can have a same rectangular profile for example in the plan view of FIG. 2 A.
  • the semiconductor die 1020 has a substantially rectangular profile aligned with the substrate 1010 in the plan view of FIG. 2 A.
  • the semiconductor die 1020 can include a memory die or an ASIC die.
  • the semiconductor die 1020 comprises a plurality of bonding pads 1024, including for example a rightmost first bonding pad 1124 and an adjacent second bonding pad 1224.
  • the bonding pads 1024 are aligned along an edge of the semiconductor die 1020 as shown in the plan view of FIG. 2 A and arranged with a uniform spacing S between adjacent bonding pads 1024.
  • the spacing S refers to a distance between opposing edges of two adjacent bonding pads 1024, as shown for the first bonding pad 1124 and the second bonding pad 1224 in FIG. 2 A.
  • the spacing S can be less than 20 ⁇ in case that the semiconductor die 1020 is a fine pitch element for example an ASIC die.
  • the bonding pads 1024 have a same rectangular profiles for example in the plan view of FIG. 2 A.
  • Each bonding pad 1024 has an upper surface which is either coplanar with the upper surface of the semiconductor die 1020 or lower than the upper surface of the semiconductor die 1020.
  • the upper surfaces of the first bonding pad 1124 and the second bonding pad 1224 are coplanar with the upper surface of the semiconductor die 1020.
  • the upper surface of the semiconductor die 1020 between the first bonding pad 1124 and the second bonding pad 1224 is covered by a passivation layer (not shown) such as a solder resist layer.
  • the semiconductor device 1000 further comprises a bonding member 1081 including a single bonding wire 1040 having a ball 1328 disposed on a first end 1041 and an opposite second end 1042 bonded directly on the bonding finger 1014 of the substrate 1010.
  • the ball 1328 electrically connects two adjacent bonding pads 1024, for example the first bonding pad 1124 and the second bonding pad 1224 by directly bonded onto adjacent portions of the first bonding pad 1124 and the second bonding pad 1224.
  • Both the bonding wire 1040 and the ball 1328 are made of gold. As shown in a sectional view of FIG.
  • the ball 1328 can serve as a bridging member for electrically and physically connecting the first bonding pad 1124 and second bonding pad 1224, therefore the present technology can be referred as a bridge ball wire bonding.
  • the ball 1328 actually has a substantially semi-spherical shape with a spherical top surface continuous formed from the first end of the bonding wire 1040 and a bottom flat surface contacting adjacent portions of the first bonding pad 1124 and second bonding pad 1224 and the solder resist layer therebetween.
  • the ball 1328 can have a diameter of about 50- 70 ⁇ , which is much greater than the spacing S between two adjacent bonding pads for a fine pitch element.
  • the second end 1042 of the bonding wire 1040 is bonded directly onto a bonding finger 1014 on the substrate 1010 for example via wedge bonding.
  • the bonding finger 1014 can supply power.
  • FIG. 2 A and FIG. 2B show two such bonding members 1081 and 1082 in the rightmost and leftmost portions of the semiconductor device 1000; however there may be more bonding members illustrated in FIG. 2A and 2B if necessary according to layout design of the semiconductor device 1000. And there may be many more bonding pads 1024, bonding fingers 1014 and bond wires 1040 than those shown in FIG. 2 A and FIG. 2B.
  • a single bonding wire 1040 can be used to supply power from one bonding finger 1014 simultaneously to two adjacent bonding pads for example the first and second bonding pads 1124 and 1224 on the semiconductor die 1020, compared with the conventional semiconductor device 100 in which two separate bonding wires 140 are used to supply power from a bonding finger 114 to two adjacent bonding pads. Therefore the present embodiment saves cost, speeds up production, and improves yield. Further details regarding the semiconductor device 1000 will be discussed with reference to a method of fabricating the semiconductor device according to the first embodiment of the present technology as shown in FIG. 3 A to FIG. 3C.
  • the semiconductor die 1020 is disposed above the substrate 1010 by a die attach process.
  • the semiconductor die 1020 can be attached on the substrate 1010 via an adhesive layer (not shown) such as die attach film (DAF).
  • DAF die attach film
  • the semiconductor die 1020 comprises a plurality of bonding pads 1024 including the rightmost first bonding pad 1124 and the adjacent second bonding pad 1224.
  • a ball 1328 is bonded onto both the first bonding pad 1124 and the second bonding pad 1224 using a capillary 1090.
  • the capillary 1090 has a needle-like shape and includes a profiled needle head 1092 and a central cavity 1094 feeding a bonding wire 1040.
  • the capillary 1090 can also comprise a transducer (not shown) to apply current and ultrasonic energy.
  • a ball made of gold is formed from a gold bonding wire at the tip of the capillary 1090.
  • the ball is affixed on both the first bonding pad 1124 and the second bonding pad 1224 under pressure applied by the capillary 1090, while the transducer applies ultrasonic energy.
  • the bond process may be further facilitated by heating the surface of the first bonding pad 1124 and second bonding pad 1224 receiving the ball.
  • the combined heat, pressure, and ultrasonic energy deforms the ball 1328 as the semi-spherical shape and bond the ball 1328 onto both the first bonding pad 1124 and second bonding pad 1224.
  • the ball 1328 preferably has a diameter greater than a ball 1028 formed for a regular ball bond on a single bonding pad 1024 shown in Figure 2 A.
  • the ball 1328 can have a diameter of 20% greater than the ball 1028 for a regular ball bonding process. Specifically, if the ball 1028 for a regular ball bond has a diameter of 30-50 ⁇ , the ball 1328 for bridge ball wire bonding can have a diameter in a range of about 50-70 ⁇ . This could be accomplished by adjusting the parameters of the capillary 1090 such as current applied by the transducer.
  • the capillary 1090 is moved over to the bonding finger 1014 on the substrate 1010 while releasing the bonding wire 1040 continuously from the ball 1328.
  • the capillary 1090 carrying the wire 1040 then crushes the wire 1040 on the bonding finger 1014 via the wedge bonding process described above.
  • FIG. 4A and FIG. 4B are schematic plan view and perspective view showing a semiconductor device 2000 according to the second embodiment of the present technology, respectively.
  • the semiconductor device 2000 comprises a substrate 2010 and a semiconductor die 2020 disposed above the substrate 2010. As shown in the plan view of FIG. 3 A, both the substrate 2010 and semiconductor die 2020 have a substantially rectangular profile aligned relative to each other.
  • the substrate 2010 further comprises a plurality of bonding fingers 2014 aligned along an edge of the substrate 2010.
  • the semiconductor die 2020 comprises a plurality of bonding pads 2024 aligned along an edge of the semiconductor die 2020, including for example a rightmost first bonding pad 2124 and an adjacent second bonding pad 2224.
  • the semiconductor device 2000 further comprises a first bump 2128 on the first bonding pad 2124 and a second bump 2228 on the adjacent second bonding pad 2224.
  • first bump 2128 and second bump 2228 have a same stud like shape with an upper neck portion. It is noted that the neck portion of the first bump 2128 and second bump 2228 are not shown in the plan view of FIG. 4E for the sake of clarity.
  • the first bump 2128 and second bump 2228 are disposed in the respective center of the first bonding pad 2124 and second bonding pad 2224, respectively, so that a spacing SP between adjacent first bonding pad 2124 and second bonding pad 2224 is the same as a spacing SB between the first bump 2128 and second bump 2228. Both the first bump 2128 and second bump 2228 are made of gold.
  • the semiconductor device 2000 also comprises a bonding member 2081 which is substantially the same as the bonding member 1081 of the semiconductor device 1000 according to the first embodiment shown in FIG. 2A to FIG. 2C.
  • the bonding member 2081 of the semiconductor device 2000 includes a single bonding wire 2040 having a ball 2328 at a first end 2041 and an opposite second end 2042 bonded directly on the bonding finger 2014.
  • the ball 2328 of the bonding member 2081 in the second embodiment is physically bonded to both the first bump 2128 and second bump 2228 so as to electrically connect the first bonding pad 2124 and the second bonding pad 2224 via the first bump 2128 and second bump 2228, respectively.
  • the ball 2328 has a spherical like shape continuous formed from the first end 2041 of the bonding wire 2040 at an upper portion and contacting the first bump 2128 and second bump 2228 at a lower potion. As shown in FIG. 4E, the ball 2328 has a diameter D substantially twice as large as a radius R of the first bump 2128 and the second bump 2228.
  • the ball 2328 can have a diameter of about 30-50 ⁇ .
  • the first bump 2128, the second bump 2228 and the ball 2328 can serve as a bridging member electrically and physically connecting the first bonding pad 2124 and the second bonding pad 2224.
  • the second end 2042 of the bonding wire 2040 is bonded directly onto a bonding finger 2014 on the substrate 2010 for example via wedge bonding.
  • the bonding finger 2014 can supply power.
  • FIG. 4A and FIG. 4B show two such bonding members 2081 and 2082 and associated bumps in the rightmost and leftmost portion of the semiconductor device 2000; however there may be more bonding members and bumps illustrated in FIG. 4A and 4B if necessary according to layout design of the semiconductor device 2000. And there may be many more bonding pads 2024 and bonding fingers 2014 and bond wires 2040 than those shown in FIG. 4 A and FIG. 4B.
  • a single bonding wire 2040 can be used to supply power from one bonding finger 2014 simultaneously to two adjacent bonding pads on the semiconductor die 2020. Therefore the present embodiment saves cost, reduces production time, and improves yield. Moreover, the ball 2328 is stacked between the first bump 2128 and the second bump 2228 without touching the passivation layer between the two adjacent bonding pads, thus avoiding damages to the semiconductor die 2020 during wire bonding. Further details regarding the semiconductor device 2000 will be discussed with reference to a method of fabricating the semiconductor device 2000 according to the second embodiment of the present technology as shown in FIG. 5A to FIG. 5C.
  • the semiconductor die 2020 is disposed above the substrate 2010 by a die attach process.
  • the semiconductor die 2020 can be attached on the substrate 2010 via an adhesive layer (not shown) such as die attach film (DAF).
  • the semiconductor die 2020 comprises a plurality of bonding pads 2024 including the rightmost first bonding pad 2124 and the adjacent second bonding pad 2224.
  • the capillary 2090 disposes a first bump 2128 and a second bump 2228, respectively, onto the first bonding pad 2124 and the second bonding pad 2224, respectively.
  • the capillary 2090 includes a profiled needle head 2092 and a central cavity 2094 feeding a bonding wire 2040.
  • the capillary 2090 can also comprise a transducer (not shown) to apply current and ultrasonic energy.
  • the above step can be accomplished as following.
  • a first ball made of gold is formed from a gold bonding wire at the tip of the capillary 2090.
  • the first ball is pressed onto the first bonding pad 2124 under a first pressure applied by the capillary 2090, while the transducer applies ultrasonic energy.
  • the bond process may be further facilitated by heating the surface of the first bonding pad 2124 receiving the first ball.
  • the combined heat, pressure, and ultrasonic energy bond the first ball onto the first bonding pad 2124.
  • the bonding wire connected to the first ball is cut by the capillary 2090, thus forming a first bump 2128 on the first bonding pad 2124.
  • the above processes are repeated so that second ball is pressed onto the second bonding pad 2124 by a second pressure to form a second bump 2228 on the second bonding pad 2224.
  • the capillary 2090 bonds a third ball 2328 onto both the first bump 2128 and the second bump 2228, respectively.
  • the above step can be accomplished as following.
  • a third ball made of gold is formed from a gold bonding wire at the tip of the capillary 2090.
  • the ball is stacked on both the first bump 2128 and the second bump 2228 under a third pressure applied by the capillary 2090, while the transducer applies ultrasonic energy.
  • the combined heat, pressure, and ultrasonic energy slightly deform the ball 2328 and bond the ball 2328 onto both the bump 2128 and second bonding pad 2228.
  • the third pressure for bonding the third ball onto the first and second bump is preferably greater than the first and second pressure for disposing the first and second bump on the first and second bonding pad respectively in order to improve bonding strength and reliability of the bridge ball wire bonding structure as formed.
  • the capillary 2090 is moved over to the bonding finger 2014 on the substrate 2010 while releasing the bonding wire 2040 continuously from the third ball 2328.
  • the capillary 2090 carrying the wire 2040 then crushes the wire 2040 on the bonding finger 2014 via a wedge bonding process described above.
  • the first, second and third ball can have a substantially same diameter, which can be the same as the diameter of a ball formed for a regular ball bond.
  • the diameter of the first, second and third ball is about 30-50 ⁇ .
  • the third ball can also have a diameter greater than the first and second ball in order to improve bonding strength.
  • the third ball can be further prevented from touching the passivation layer between the adjacent bonding pads of the semiconductor die in a first variant of the second embodiment of the present technology as describe below.
  • the semiconductor device 2000' shown in FIG. 6A and FIG. 6B is substantially the same as the semiconductor device 2000 except the positions of the first bump 2128 and the second bump 2228. Therefore other aspects and details of the semiconductor device 2000' are omitted herein to avoid redundancy.
  • the first bump 2128 and the second bump 2228 are offset relative to the respective center of the first bonding pad 2124 and second bonding pad 2224 so as to be closer to each other. That is, a spacing SP between adjacent first bonding pad 2124 and second bonding pad 2224 is greater than a spacing SB between the first bump 2128 and second bump 2228. Due to such arrangement, the third ball 2328 can have a greater contact area with the first bump 2128 and 2228. Therefore, both the bonding strength and reliability of the bridge ball bonding structure can be improved, since a smaller pressure can be applied to the third ball for obtaining a desired bonding strength, thus further preventing the third ball from touching the passivation layer between the adjacent bonding pads.
  • FIG. 7 is a schematic perspective view of a semiconductor device 3000 according to a second variant of the second embodiment of the present technology.
  • the semiconductor device 3000 comprises a substrate 3010, a first semiconductor die 3020 disposed above the substrate 3010 and a second semiconductor die 3030 disposed above the semiconductor die 3020.
  • the second semiconductor die 3030 can be an ASIC die and the first semiconductor die 3020 can be a memory die.
  • the substrate 3010 further comprises a plurality of bonding fingers 3014 aligned along an edge of the substrate 3010.
  • the second semiconductor die 3030 comprises a plurality of bonding pads 3034 aligned along an edge of the semiconductor die 3030, including for example an adjacent first bonding pad 3134 and second bonding pad 3234.
  • Other details of the substrate 3010, semiconductor die 3030, bumps and ball bonding members of the semiconductor device 3000 are substantially the same as the substrate 2010, the semiconductor die 2020, bumps and ball bonding member of the semiconductor device 2000 and will not be repeated herein to avoid redundancy.
  • the present technology relates to a semiconductor device.
  • the semiconductor device comprises: a substrate, a semiconductor die disposed above the substrate, and a bonding member.
  • the substrate further comprises a bonding finger.
  • the semiconductor die further comprises a first and an adjacent second bonding pads.
  • the bonding member further comprises a single bonding wire having a ball disposed on a first end that electrically connects the first bonding pad and the second bonding pad and an opposite second end bonded directly on the bonding finger.
  • the bonding finger supplies power.
  • the first bonding pad and the second bonding pad are separated by a spacing of less than 20 ⁇ .
  • the ball is bonded directly on adjacent portions of the first bonding pad and the second bonding pad.
  • the ball has a diameter of about 50-70 ⁇ .
  • the semiconductor device further comprises: a first and a second bump, respectively, disposed on the first and the second bonding pad, respectively.
  • the ball is disposed between and above the first bump and the second bump.
  • the ball is physically bonded to both the first bump and the second bump.
  • the first bump and the second bump are offset relative to the respective center of the first and second bonding pads so as to be closer to each other.
  • the ball has a diameter substantially twice as large as a radius of the first bump and the second bump.
  • the diameter of the ball is in a range of about 30-50 ⁇ .
  • the bonding wire comprises gold.
  • the present technology relates to a semiconductor device.
  • the semiconductor device comprises: a substrate further comprising a bonding finger; a semiconductor die disposed above the substrate, the semiconductor die further comprising a first and an adjacent second bonding pads; a bridging member electrically and physically connecting the first and the second bonding pads, and a single bonding wire physically and electrically connecting the bridging member at a first end and the bonding finger at a second end.
  • the bridging member comprises a ball bonded directly on adjacent portions of the first bonding pad and the second bonding pad.
  • the bridging member comprises: a first and second bump, respectively, disposed on the first and the second bonding pads, respectively; and a ball connected to the first end of the bonding wire and stacked between the first bump and the second bump.
  • the present technology relates to a method of fabricating a semiconductor device.
  • the method comprises following steps of: disposing a semiconductor die above a substrate, the substrate further comprising a bonding finger, and the semiconductor die further comprising a first and an adjacent second bonding pads; bonding a ball onto both the first bonding pad and the second bonding pad; releasing a single bonding wire continuously from the ball to the bonding finger; and wedge bonding the single bonding wire onto the bonding finger.
  • the ball has a diameter of about 50-70 ⁇ .
  • the present technology relates to a method of fabricating a semiconductor device.
  • the method comprises following steps of: disposing a semiconductor die above a substrate, the substrate further comprising a bonding finger, and the semiconductor die further comprising a first and an adjacent second bonding pads; pressing a first ball onto the first bonding pad by applying a first pressure so as to form a first bump on the first bonding pad; pressing a second ball onto the second bonding pad by applying a second pressure so as to form a second bump on the second bonding pad; bonding a third ball onto both the first bump and the second bump; releasing a single bonding wire continuously from the third ball to the bonding finger; and wedge bonding the single bonding wire onto the bonding finger.
  • the first ball, the second ball and the third ball have a substantially same diameter.
  • the diameter is about 30-50 ⁇ .
  • Third pressure is greater than the first pressure and the second pressure.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor device and a method of fabricating the semiconductor device are provided by the implementation of the present invention. The semiconductor device comprises: a substrate, a semiconductor die disposed above the substrate, and a bonding member. The substrate further comprises a bonding finger. The semiconductor die further comprises a first and an adjacent second bonding pads. The bonding member further comprises a single bonding wire having a ball disposed on a first end that electrically connects the first bonding pad and the second bonding pad and an opposite second end bonded directly on the bonding finger.

Description

BRIDGE BALL WIRE BONDING
BACKGROUND OF THE INVENTION
Field
[0001] The present technology relates to semiconductor devices.
Description of Related Art
[0002] Consumer demand for compact products with increased functionality continues to drive the semiconductor industry to provide high density packaging of the semiconductor devices. Wireless applications such as cell phones and consumer products like pocket PCs require maximum functional integration in the smallest footprint, lowest profile and low-cost packaging.
[0003] One example of such semiconductor device 100 can be shown in a schematic plan view and perspective view of FIG. 1A and FIG. IB. The semiconductor device 100 comprises a substrate 110 and a semiconductor die 120 such as an ASIC (Application Specific Integrated Circuit) die and memory dies like flash, SRAM and DDR. The substrate 110 comprises a plurality of bonding fingers 114 aligned along an edge of the substrate 110 in the plan view of FIG. 1A. The semiconductor die 120 comprises a plurality of bonding pads 124 aligned also along an edge of the semiconductor die 120 in the plan view of FIG. IB.
[0004] In some layout design of such semiconductor device, it is necessary to connect one bonding finger 114 on the substrate 110 to two adjacent bonding pads 124 on the semiconductor die 120, for example for supplying power to the separate parts within the semiconductor die 120. As shown in FIG. 1 A and IB, the leftmost two adjacent bonding pads 124 are connected to a leftmost bonding finger 114 via two separate bonding wires 140 by a wire bonding process. During such wire bonding process, a length of wire (typically gold) is fed through a central cavity of a needle-like disposable tool called the capillary (not shown). The wire protrudes through a tip of the capillary, where a high- voltage electric charge is applied to the wire from a transducer associated with the capillary tip. The electric charge melts the wire at the tip and the wire forms into a ball owing to the surface tension of the molten metal. As the ball solidifies, the capillary is lowered to the bonding pad 124 and ultrasonic energy is applied by the transducer. The bonding pad 124 can also be heated to facilitate bonding. The combined heat, pressure, and ultrasonic energy create a weld between the gold ball 128 and the bonding pad 124. The capillary is then pulled up and away from the bonding pad 124, as the wire 140 is passed out through the capillary. The resulting bond on the bonding pad 124 is referred as a ball bond. Then the capillary carrying the wire 140 moves over to the bonding finger 114 on the substrate 110, and descends and crushes the wire 140 by touching the bonding surface of the bonding finger 114 to make the wire bond again using heat, pressure and ultrasonic energy. The capillary then pays out a small length of wire and tears the wire from the bonding finger 114. The resulting bond on the bonding finger 114 is often referred as a wedge bond or a stitch bond.
DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1A and FIG. IB are schematic plan view and perspective view showing a conventional semiconductor device, respectively.
[0006] FIG. 2A and FIG. 2B are schematic plan view and perspective view showing a semiconductor device according to a first embodiment of the present technology, respectively.
[0007] FIG. 2C is a schematic sectional view of the semiconductor device taken along line C- C in FIG. 2A.
[0008] FIG. 3 A to FIG. 3C are schematic perspective views showing a method of fabricating the semiconductor device according to the first embodiment of the present technology.
[0009] FIG. 4A and FIG. 4B are schematic plan view and perspective view showing a semiconductor device according to a second embodiment of the present technology, respectively.
[0010] FIG. 4C is a partial enlarged perspective view of the semiconductor device shown in FIG. 3B.
[0011] FIG. 4D is a schematic sectional view taken along line D-D in FIG. 4A.
[0012] FIG. 4E is a schematic enlarged partial plan view of the semiconductor device according to a second embodiment of the present technology.
[0013] FIG. 5A to FIG. 5C are schematic perspective views showing a method of fabricating the semiconductor device according to the second embodiment of the present technology. [0014] FIG. 6A is a schematic plan view showing a semiconductor device according to a first variant of the second embodiment of the present technology.
[0015] FIG. 6B is a partial enlarged plan view of the semiconductor device shown in FIG. 6A.
[0016] FIG. 7 is a schematic perspective view of a semiconductor device according to a second variant of the second embodiment of the present technology.
DETAILED DESCRIPTION
[0017] Embodiments will now be described with reference to FIGS. 2A through 7, which relate to a semiconductor device. It is understood that the present technology may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the present technology to those skilled in the art. Indeed, the present technology is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. However, it will be clear to those of ordinary skill in the art that the present technology may be practiced without such specific details.
[0018] The terms "left", "right", "top", "bottom", "upper", "lower", "above" and/or "below" as may be used herein are for convenience and illustrative purposes only, and are not meant to limit the description of the present technology inasmuch as the referenced item can be exchanged in position. Throughout the figures in this application, the mould compound is not shown for sake of clarity and simplicity.
[0019] FIG. 2 A and FIG. 2B are schematic plan view and perspective view showing a semiconductor device 1000 according to a first embodiment of the present technology, respectively.
[0020] The semiconductor device 1000 comprises a substrate 1010 and a semiconductor die 1020 disposed above the substrate 1010. [0021] The substrate 1010 has a substantially rectangular profile for example, as shown in the plan view of FIG. 2 A. The substrate 1010 can include a wiring board such as printed circuit board (PCB). The substrate 1010 comprises a plurality of bonding fingers 1014 aligned along an edge of the substrate 1010. The bonding fingers 1014 can have a same rectangular profile for example in the plan view of FIG. 2 A.
[0022] The semiconductor die 1020 has a substantially rectangular profile aligned with the substrate 1010 in the plan view of FIG. 2 A. The semiconductor die 1020 can include a memory die or an ASIC die. The semiconductor die 1020 comprises a plurality of bonding pads 1024, including for example a rightmost first bonding pad 1124 and an adjacent second bonding pad 1224. The bonding pads 1024 are aligned along an edge of the semiconductor die 1020 as shown in the plan view of FIG. 2 A and arranged with a uniform spacing S between adjacent bonding pads 1024. The spacing S refers to a distance between opposing edges of two adjacent bonding pads 1024, as shown for the first bonding pad 1124 and the second bonding pad 1224 in FIG. 2 A. The spacing S can be less than 20 μπι in case that the semiconductor die 1020 is a fine pitch element for example an ASIC die. The bonding pads 1024 have a same rectangular profiles for example in the plan view of FIG. 2 A. Each bonding pad 1024 has an upper surface which is either coplanar with the upper surface of the semiconductor die 1020 or lower than the upper surface of the semiconductor die 1020. For example, as shown in a sectional view of FIG. 2C, the upper surfaces of the first bonding pad 1124 and the second bonding pad 1224 are coplanar with the upper surface of the semiconductor die 1020. The upper surface of the semiconductor die 1020 between the first bonding pad 1124 and the second bonding pad 1224 is covered by a passivation layer (not shown) such as a solder resist layer.
[0023] The semiconductor device 1000 further comprises a bonding member 1081 including a single bonding wire 1040 having a ball 1328 disposed on a first end 1041 and an opposite second end 1042 bonded directly on the bonding finger 1014 of the substrate 1010. The ball 1328 electrically connects two adjacent bonding pads 1024, for example the first bonding pad 1124 and the second bonding pad 1224 by directly bonded onto adjacent portions of the first bonding pad 1124 and the second bonding pad 1224. Both the bonding wire 1040 and the ball 1328 are made of gold. As shown in a sectional view of FIG. 2C, the ball 1328 can serve as a bridging member for electrically and physically connecting the first bonding pad 1124 and second bonding pad 1224, therefore the present technology can be referred as a bridge ball wire bonding. The ball 1328 actually has a substantially semi-spherical shape with a spherical top surface continuous formed from the first end of the bonding wire 1040 and a bottom flat surface contacting adjacent portions of the first bonding pad 1124 and second bonding pad 1224 and the solder resist layer therebetween. The ball 1328 can have a diameter of about 50- 70 μπι, which is much greater than the spacing S between two adjacent bonding pads for a fine pitch element. This can facilitate to improve the process window for wire bonding and ensure a reliable bonding strength on both adjacent first and second bonding pads. The second end 1042 of the bonding wire 1040 is bonded directly onto a bonding finger 1014 on the substrate 1010 for example via wedge bonding. The bonding finger 1014 can supply power.
[0024] FIG. 2 A and FIG. 2B show two such bonding members 1081 and 1082 in the rightmost and leftmost portions of the semiconductor device 1000; however there may be more bonding members illustrated in FIG. 2A and 2B if necessary according to layout design of the semiconductor device 1000. And there may be many more bonding pads 1024, bonding fingers 1014 and bond wires 1040 than those shown in FIG. 2 A and FIG. 2B.
[0025] According to the first embodiment of the present technology, a single bonding wire 1040 can be used to supply power from one bonding finger 1014 simultaneously to two adjacent bonding pads for example the first and second bonding pads 1124 and 1224 on the semiconductor die 1020, compared with the conventional semiconductor device 100 in which two separate bonding wires 140 are used to supply power from a bonding finger 114 to two adjacent bonding pads. Therefore the present embodiment saves cost, speeds up production, and improves yield. Further details regarding the semiconductor device 1000 will be discussed with reference to a method of fabricating the semiconductor device according to the first embodiment of the present technology as shown in FIG. 3 A to FIG. 3C.
[0026] As shown in FIG. 3 A, the semiconductor die 1020 is disposed above the substrate 1010 by a die attach process. The semiconductor die 1020 can be attached on the substrate 1010 via an adhesive layer (not shown) such as die attach film (DAF). The semiconductor die 1020 comprises a plurality of bonding pads 1024 including the rightmost first bonding pad 1124 and the adjacent second bonding pad 1224.
[0027] Next, as shown in FIG. 3B, a ball 1328 is bonded onto both the first bonding pad 1124 and the second bonding pad 1224 using a capillary 1090. The capillary 1090 has a needle-like shape and includes a profiled needle head 1092 and a central cavity 1094 feeding a bonding wire 1040. The capillary 1090 can also comprise a transducer (not shown) to apply current and ultrasonic energy. The above step can be accomplished as following. A ball made of gold is formed from a gold bonding wire at the tip of the capillary 1090. Then the ball is affixed on both the first bonding pad 1124 and the second bonding pad 1224 under pressure applied by the capillary 1090, while the transducer applies ultrasonic energy. In embodiments, the bond process may be further facilitated by heating the surface of the first bonding pad 1124 and second bonding pad 1224 receiving the ball. The combined heat, pressure, and ultrasonic energy deforms the ball 1328 as the semi-spherical shape and bond the ball 1328 onto both the first bonding pad 1124 and second bonding pad 1224. The ball 1328 preferably has a diameter greater than a ball 1028 formed for a regular ball bond on a single bonding pad 1024 shown in Figure 2 A. In one example, the ball 1328 can have a diameter of 20% greater than the ball 1028 for a regular ball bonding process. Specifically, if the ball 1028 for a regular ball bond has a diameter of 30-50μπι, the ball 1328 for bridge ball wire bonding can have a diameter in a range of about 50-70 μπι. This could be accomplished by adjusting the parameters of the capillary 1090 such as current applied by the transducer.
[0028] Then as shown in FIG. 3C, the capillary 1090 is moved over to the bonding finger 1014 on the substrate 1010 while releasing the bonding wire 1040 continuously from the ball 1328. The capillary 1090 carrying the wire 1040 then crushes the wire 1040 on the bonding finger 1014 via the wedge bonding process described above.
[0029] The above-described wire bonding process can be repeated for adjacent bonding pads connected to the same bonding finger 1014 in the semiconductor device 1000.
[0030] It should be noted that in the present embodiment, since the ball 1328 directly contacts the passivation layer (not shown) between adjacent bonding pads 1024, the passivation layer might suffer slight damages near the edges of the bonding pads 1024 due to the fact that the passivation layer between the bonding pads is also touched by the ball 1328 upon bonding the ball 1328 onto the adjacent bonding pads 1024. This might affect long time reliability of the semiconductor device 1000 under rigorous service conditions. Such potential disadvantage can be further avoided by a second embodiment of the present technology described as below.
[0031] FIG. 4A and FIG. 4B are schematic plan view and perspective view showing a semiconductor device 2000 according to the second embodiment of the present technology, respectively. [0032] The semiconductor device 2000 comprises a substrate 2010 and a semiconductor die 2020 disposed above the substrate 2010. As shown in the plan view of FIG. 3 A, both the substrate 2010 and semiconductor die 2020 have a substantially rectangular profile aligned relative to each other. The substrate 2010 further comprises a plurality of bonding fingers 2014 aligned along an edge of the substrate 2010. The semiconductor die 2020 comprises a plurality of bonding pads 2024 aligned along an edge of the semiconductor die 2020, including for example a rightmost first bonding pad 2124 and an adjacent second bonding pad 2224.
[0033] The semiconductor device 2000 further comprises a first bump 2128 on the first bonding pad 2124 and a second bump 2228 on the adjacent second bonding pad 2224. As shown in perspective view of FIG. 4C, sectional view FIG. 4D and plan view of FIG. 4E, the first bump 2128 and second bump 2228 have a same stud like shape with an upper neck portion. It is noted that the neck portion of the first bump 2128 and second bump 2228 are not shown in the plan view of FIG. 4E for the sake of clarity. The first bump 2128 and second bump 2228 are disposed in the respective center of the first bonding pad 2124 and second bonding pad 2224, respectively, so that a spacing SP between adjacent first bonding pad 2124 and second bonding pad 2224 is the same as a spacing SB between the first bump 2128 and second bump 2228. Both the first bump 2128 and second bump 2228 are made of gold. The semiconductor device 2000 also comprises a bonding member 2081 which is substantially the same as the bonding member 1081 of the semiconductor device 1000 according to the first embodiment shown in FIG. 2A to FIG. 2C. The bonding member 2081 of the semiconductor device 2000 includes a single bonding wire 2040 having a ball 2328 at a first end 2041 and an opposite second end 2042 bonded directly on the bonding finger 2014. Unlike the bonding member 1081 with the ball 1328 bonded directly onto adjacent bonding pads in the first embodiment, the ball 2328 of the bonding member 2081 in the second embodiment is physically bonded to both the first bump 2128 and second bump 2228 so as to electrically connect the first bonding pad 2124 and the second bonding pad 2224 via the first bump 2128 and second bump 2228, respectively. The ball 2328 has a spherical like shape continuous formed from the first end 2041 of the bonding wire 2040 at an upper portion and contacting the first bump 2128 and second bump 2228 at a lower potion. As shown in FIG. 4E, the ball 2328 has a diameter D substantially twice as large as a radius R of the first bump 2128 and the second bump 2228. For example, the ball 2328 can have a diameter of about 30-50 μπι. The first bump 2128, the second bump 2228 and the ball 2328 can serve as a bridging member electrically and physically connecting the first bonding pad 2124 and the second bonding pad 2224. The second end 2042 of the bonding wire 2040 is bonded directly onto a bonding finger 2014 on the substrate 2010 for example via wedge bonding. The bonding finger 2014 can supply power.
[0034] FIG. 4A and FIG. 4B show two such bonding members 2081 and 2082 and associated bumps in the rightmost and leftmost portion of the semiconductor device 2000; however there may be more bonding members and bumps illustrated in FIG. 4A and 4B if necessary according to layout design of the semiconductor device 2000. And there may be many more bonding pads 2024 and bonding fingers 2014 and bond wires 2040 than those shown in FIG. 4 A and FIG. 4B.
[0035] According to the second embodiment of the present technology, a single bonding wire 2040 can be used to supply power from one bonding finger 2014 simultaneously to two adjacent bonding pads on the semiconductor die 2020. Therefore the present embodiment saves cost, reduces production time, and improves yield. Moreover, the ball 2328 is stacked between the first bump 2128 and the second bump 2228 without touching the passivation layer between the two adjacent bonding pads, thus avoiding damages to the semiconductor die 2020 during wire bonding. Further details regarding the semiconductor device 2000 will be discussed with reference to a method of fabricating the semiconductor device 2000 according to the second embodiment of the present technology as shown in FIG. 5A to FIG. 5C.
[0036] As shown in FIG. 5A, the semiconductor die 2020 is disposed above the substrate 2010 by a die attach process. The semiconductor die 2020 can be attached on the substrate 2010 via an adhesive layer (not shown) such as die attach film (DAF). The semiconductor die 2020 comprises a plurality of bonding pads 2024 including the rightmost first bonding pad 2124 and the adjacent second bonding pad 2224. Then, the capillary 2090 disposes a first bump 2128 and a second bump 2228, respectively, onto the first bonding pad 2124 and the second bonding pad 2224, respectively. The capillary 2090 includes a profiled needle head 2092 and a central cavity 2094 feeding a bonding wire 2040. The capillary 2090 can also comprise a transducer (not shown) to apply current and ultrasonic energy. The above step can be accomplished as following. A first ball made of gold is formed from a gold bonding wire at the tip of the capillary 2090. Then the first ball is pressed onto the first bonding pad 2124 under a first pressure applied by the capillary 2090, while the transducer applies ultrasonic energy. The bond process may be further facilitated by heating the surface of the first bonding pad 2124 receiving the first ball. The combined heat, pressure, and ultrasonic energy bond the first ball onto the first bonding pad 2124. Then the bonding wire connected to the first ball is cut by the capillary 2090, thus forming a first bump 2128 on the first bonding pad 2124. Then, the above processes are repeated so that second ball is pressed onto the second bonding pad 2124 by a second pressure to form a second bump 2228 on the second bonding pad 2224.
[0037] Next, as shown in FIG. 5B, the capillary 2090 bonds a third ball 2328 onto both the first bump 2128 and the second bump 2228, respectively. The above step can be accomplished as following. A third ball made of gold is formed from a gold bonding wire at the tip of the capillary 2090. Then the ball is stacked on both the first bump 2128 and the second bump 2228 under a third pressure applied by the capillary 2090, while the transducer applies ultrasonic energy. The combined heat, pressure, and ultrasonic energy slightly deform the ball 2328 and bond the ball 2328 onto both the bump 2128 and second bonding pad 2228. The third pressure for bonding the third ball onto the first and second bump is preferably greater than the first and second pressure for disposing the first and second bump on the first and second bonding pad respectively in order to improve bonding strength and reliability of the bridge ball wire bonding structure as formed.
[0038] Then as shown in FIG. 5C, the capillary 2090 is moved over to the bonding finger 2014 on the substrate 2010 while releasing the bonding wire 2040 continuously from the third ball 2328. The capillary 2090 carrying the wire 2040 then crushes the wire 2040 on the bonding finger 2014 via a wedge bonding process described above.
[0039] The above-described wire bonding process can be repeated for adjacent bonding pads connected to the same bonding finger 2014 in the semiconductor device 2000.
[0040] In the second embodiment, the first, second and third ball can have a substantially same diameter, which can be the same as the diameter of a ball formed for a regular ball bond. For example, the diameter of the first, second and third ball is about 30-50 μπι. In this way, it is not necessary to adjust the parameters of the capillary 2090 throughout the wire bonding process for the semiconductor device 2000, thus reducing the complexity of the overall process and improving throughput. Alternatively, the third ball can also have a diameter greater than the first and second ball in order to improve bonding strength.
[0041] The third ball can be further prevented from touching the passivation layer between the adjacent bonding pads of the semiconductor die in a first variant of the second embodiment of the present technology as describe below. [0042] As shown in FIG. 6A and FIG. 6B, the semiconductor device 2000' shown in FIG. 6A and FIG. 6B is substantially the same as the semiconductor device 2000 except the positions of the first bump 2128 and the second bump 2228. Therefore other aspects and details of the semiconductor device 2000' are omitted herein to avoid redundancy.
[0043] As shown in FIG. 6B, the first bump 2128 and the second bump 2228 are offset relative to the respective center of the first bonding pad 2124 and second bonding pad 2224 so as to be closer to each other. That is, a spacing SP between adjacent first bonding pad 2124 and second bonding pad 2224 is greater than a spacing SB between the first bump 2128 and second bump 2228. Due to such arrangement, the third ball 2328 can have a greater contact area with the first bump 2128 and 2228. Therefore, both the bonding strength and reliability of the bridge ball bonding structure can be improved, since a smaller pressure can be applied to the third ball for obtaining a desired bonding strength, thus further preventing the third ball from touching the passivation layer between the adjacent bonding pads.
[0044] The present technology is not limited to a semiconductor device with one semiconductor die. FIG. 7 is a schematic perspective view of a semiconductor device 3000 according to a second variant of the second embodiment of the present technology. The semiconductor device 3000 comprises a substrate 3010, a first semiconductor die 3020 disposed above the substrate 3010 and a second semiconductor die 3030 disposed above the semiconductor die 3020. For example, the second semiconductor die 3030 can be an ASIC die and the first semiconductor die 3020 can be a memory die. The substrate 3010 further comprises a plurality of bonding fingers 3014 aligned along an edge of the substrate 3010. The second semiconductor die 3030 comprises a plurality of bonding pads 3034 aligned along an edge of the semiconductor die 3030, including for example an adjacent first bonding pad 3134 and second bonding pad 3234. Other details of the substrate 3010, semiconductor die 3030, bumps and ball bonding members of the semiconductor device 3000 are substantially the same as the substrate 2010, the semiconductor die 2020, bumps and ball bonding member of the semiconductor device 2000 and will not be repeated herein to avoid redundancy.
[0045] According to the embodiments of the present technology, a single bonding wire can be used to supply power from one bonding finger on the substrate simultaneously to two adjacent bonding pads on the semiconductor die disposed above the substrate. Therefore the present technology could save cost, reduce production time, and improve yields of the semiconductor device. [0046] In one aspect, the present technology relates to a semiconductor device. The semiconductor device comprises: a substrate, a semiconductor die disposed above the substrate, and a bonding member. The substrate further comprises a bonding finger. The semiconductor die further comprises a first and an adjacent second bonding pads. The bonding member further comprises a single bonding wire having a ball disposed on a first end that electrically connects the first bonding pad and the second bonding pad and an opposite second end bonded directly on the bonding finger.
[0047] In embodiments, the bonding finger supplies power. The first bonding pad and the second bonding pad are separated by a spacing of less than 20 μπι. The ball is bonded directly on adjacent portions of the first bonding pad and the second bonding pad. The ball has a diameter of about 50-70 μπι.
[0048] In embodiments, the semiconductor device further comprises: a first and a second bump, respectively, disposed on the first and the second bonding pad, respectively. The ball is disposed between and above the first bump and the second bump. The ball is physically bonded to both the first bump and the second bump. The first bump and the second bump are offset relative to the respective center of the first and second bonding pads so as to be closer to each other. The ball has a diameter substantially twice as large as a radius of the first bump and the second bump. The diameter of the ball is in a range of about 30-50 μπι.
[0049] In embodiments, the bonding wire comprises gold.
[0050] In another aspect, the present technology relates to a semiconductor device. The semiconductor device comprises: a substrate further comprising a bonding finger; a semiconductor die disposed above the substrate, the semiconductor die further comprising a first and an adjacent second bonding pads; a bridging member electrically and physically connecting the first and the second bonding pads, and a single bonding wire physically and electrically connecting the bridging member at a first end and the bonding finger at a second end.
[0051] In embodiments, the bridging member comprises a ball bonded directly on adjacent portions of the first bonding pad and the second bonding pad. Alternatively, the bridging member comprises: a first and second bump, respectively, disposed on the first and the second bonding pads, respectively; and a ball connected to the first end of the bonding wire and stacked between the first bump and the second bump [0052] In another aspect, the present technology relates to a method of fabricating a semiconductor device. The method comprises following steps of: disposing a semiconductor die above a substrate, the substrate further comprising a bonding finger, and the semiconductor die further comprising a first and an adjacent second bonding pads; bonding a ball onto both the first bonding pad and the second bonding pad; releasing a single bonding wire continuously from the ball to the bonding finger; and wedge bonding the single bonding wire onto the bonding finger.
[0053] In embodiments, the ball has a diameter of about 50-70 μπι.
[0054] In another aspect, the present technology relates to a method of fabricating a semiconductor device. The method comprises following steps of: disposing a semiconductor die above a substrate, the substrate further comprising a bonding finger, and the semiconductor die further comprising a first and an adjacent second bonding pads; pressing a first ball onto the first bonding pad by applying a first pressure so as to form a first bump on the first bonding pad; pressing a second ball onto the second bonding pad by applying a second pressure so as to form a second bump on the second bonding pad; bonding a third ball onto both the first bump and the second bump; releasing a single bonding wire continuously from the third ball to the bonding finger; and wedge bonding the single bonding wire onto the bonding finger.
[0055] In embodiments, the first ball, the second ball and the third ball have a substantially same diameter. For example, the diameter is about 30-50 μπι. Third pressure is greater than the first pressure and the second pressure.
[0056] The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims

CLAIMS We claim:
1. A semiconductor device comprising:
a substrate, the substrate further comprising a bonding finger;
a semiconductor die disposed above the substrate, the semiconductor die further comprising a first and an adjacent second bonding pads; and
a bonding member, the bonding member further comprising a single bonding wire having a ball disposed on a first end that electrically connects the first bonding pad and the second bonding pad and an opposite second end bonded directly on the bonding finger.
2. The semiconductor device of claim 1, wherein the bonding finger supplies power.
3. The semiconductor device of claim 1, wherein the first bonding pad and the second bonding pad are separated by a spacing of less than 20 μπι.
4. The semiconductor device of claim 1, wherein the ball is bonded directly on adjacent portions of the first bonding pad and the second bonding pad.
5. The semiconductor device of claim 4, wherein the ball has a diameter of about 50-70 μπι.
6. The semiconductor device of claim 1, wherein the semiconductor device further comprises:
a first and a second bump, respectively, disposed on the first and the second bonding pad, respectively,
wherein the ball is disposed between and above the first bump and the second bump.
7. The semiconductor device of claim 6, wherein the ball is physically bonded to both the first bump and the second bump.
8. The semiconductor device of claim 6, wherein the first bump and the second bump are offset relative to the respective center of the first and second bonding pads so as to be closer to each other.
9. The semiconductor device of claim 6, wherein the ball has a diameter substantially twice as large as a radius of the first bump and the second bump.
10. The semiconductor device of claim 9, wherein the diameter of the ball is in a range of about 30-50 μπι.
11. The semiconductor device of claim 1, wherein the bonding wire comprises gold.
12. A semiconductor device comprising:
a substrate, the substrate further comprising a bonding finger;
a semiconductor die disposed above the substrate, the semiconductor die further comprising a first and an adjacent second bonding pads;
a bridging member electrically and physically connecting the first and the second bonding pads, and
a single bonding wire physically and electrically connecting the bridging member at a first end and the bonding finger at a second end.
13. The semiconductor device of claim 12, wherein the bridging member comprises a ball bonded directly on adjacent portions of the first bonding pad and the second bonding pad.
14. The semiconductor device of claim 12, wherein the bridging member comprises:
a first and second bump, respectively, disposed on the first and the second bonding pads, respectively; and
a ball connected to the first end of the bonding wire and stacked between the first bump and the second bump.
15. A method of fabricating a semiconductor device comprising the steps of:
disposing a semiconductor die above a substrate, the substrate further comprising a bonding finger, and the semiconductor die further comprising a first and an adjacent second bonding pads;
bonding a ball onto both the first bonding pad and the second bonding pad;
releasing a single bonding wire continuously from the ball to the bonding finger; and
wedge bonding the single bonding wire onto the bonding finger.
16. The method of claim 15, wherein the ball has a diameter of about 50-70 μπι.
17. A method of fabricating a semiconductor device comprising the steps of:
disposing a semiconductor die above a substrate, the substrate further comprising a bonding finger, and the semiconductor die further comprising a first and an adjacent second bonding pads;
pressing a first ball onto the first bonding pad by applying a first pressure so as to form a first bump on the first bonding pad;
pressing a second ball onto the second bonding pad by applying a second pressure so as to form a second bump on the second bonding pad;
bonding a third ball onto both the first bump and the second bump; releasing a single bonding wire continuously from the third ball to the bonding finger; and
wedge bonding the single bonding wire onto the bonding finger.
18. The method of claim 17, wherein the first ball, the second ball and the third ball have a substantially same diameter.
19. The method of claim 18, wherein the diameter is about 30-50 μπι.
20. The method of claim 17, wherein the third pressure is greater than the first pressure and the second pressure.
PCT/CN2012/080668 2012-08-28 2012-08-28 Bridge ball wire bonding WO2014032228A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021049996A1 (en) * 2019-09-10 2021-03-18 Ribet Federico Bonding of electrically conducting wire to contact pad of a microchip

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003152011A (en) * 2001-11-15 2003-05-23 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
CN1941348A (en) * 2005-09-30 2007-04-04 富士通株式会社 Relay board and semiconductor device having the relay board
US20070215994A1 (en) * 2002-07-31 2007-09-20 Microchip Technology Incorporated Connecting a Plurality of Bond Pads and/or Inner Leads With a Single Bond Wire
US20120061826A1 (en) * 2010-07-29 2012-03-15 Elpida Memory, Inc. Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003152011A (en) * 2001-11-15 2003-05-23 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
US20070215994A1 (en) * 2002-07-31 2007-09-20 Microchip Technology Incorporated Connecting a Plurality of Bond Pads and/or Inner Leads With a Single Bond Wire
CN1941348A (en) * 2005-09-30 2007-04-04 富士通株式会社 Relay board and semiconductor device having the relay board
US20120061826A1 (en) * 2010-07-29 2012-03-15 Elpida Memory, Inc. Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021049996A1 (en) * 2019-09-10 2021-03-18 Ribet Federico Bonding of electrically conducting wire to contact pad of a microchip

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