TWI666704B - 半導體裝置與其形成方法 - Google Patents

半導體裝置與其形成方法 Download PDF

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TWI666704B
TWI666704B TW106103214A TW106103214A TWI666704B TW I666704 B TWI666704 B TW I666704B TW 106103214 A TW106103214 A TW 106103214A TW 106103214 A TW106103214 A TW 106103214A TW I666704 B TWI666704 B TW I666704B
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Taiwan
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layer
forming
silicide
metal
metal layer
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TW106103214A
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TW201737346A (zh
Inventor
許家銘
周沛瑜
曹志彬
許光源
陳志輝
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台灣積體電路製造股份有限公司
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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Abstract

半導體裝置的形成方法中，第一接點孔形成於源極/汲極區或閘極上的一或多個介電層中。黏著層形成於第一接點孔中。第一金屬層形成於第一接點孔中的黏著層上。矽化物層形成於第一金屬層的上表面上。矽化物層包含的金屬元素與第一金屬層相同。

Description

半導體裝置與其形成方法
本發明實施例關於半導體裝置的形成方法，更特別關於源極/汲極區上的導電層之結構與其形成方法。
隨著半導體裝置的尺寸縮小，開始採用多種非鋁或銅的金屬。舉例來說，鈷已用於通孔或接點結構的導電材料。但由於鈷為活性金屬且易與氧、濕氣、或酸反應，通常難以採用穩定態的鈷。
本發明一實施例提供之半導體裝置的形成方法，包括：形成第一接點孔於源極/汲極區或閘極上的一或多個介電層中；形成黏著層於第一接點孔中；形成第一金屬層於第一接點孔中的黏著層上；以及形成矽化物層於第一金屬層的上表面上，其中矽化物層包含的金屬元素與第一金屬層相同。
本發明一實施例提供之半導體裝置的形成方法，包括：形成第一接點孔於源極/汲極區或閘極上的一或多個介電層中；形成第一金屬層於第一接點孔中；以及形成較上矽化物層於第一金屬層的上表面上，其中源極/汲極區與閘極中至少一者包含較下矽化物層，第一金屬層接觸較下矽化物層，較上矽化物層覆蓋第一金屬層的至少部份上表面，且較上矽化物 層包含的金屬元素與第一金屬層相同。
本發明一實施例提供之半導體裝置，包括場效電晶體，且包括：源極/汲極區；源極/汲極矽化物層，形成於源極/汲極區上；以及第一接點，連接至源極/汲極矽化物層，其中：第一接點包括第一金屬層；第一金屬層的上表面至少被矽化物層覆蓋；以及矽化物層包含的金屬元素與第一金屬層相同。
H1‧‧‧高度差異
X1-X1‧‧‧剖線
1、300‧‧‧基板
3、320‧‧‧隔離絕緣層
5、310‧‧‧鰭狀結構
10‧‧‧金屬閘極結構
12‧‧‧閘極介電層
14‧‧‧功函數調整層
16‧‧‧金屬材料層
20、340‧‧‧蓋絕緣層
30、350‧‧‧側壁間隔物
33、90‧‧‧接點蝕刻停止層
40‧‧‧第一層間介電層
50、360‧‧‧源極/汲極區
55、80‧‧‧矽化物層
60‧‧‧第二層間介電層
65‧‧‧接點孔
70‧‧‧黏著層
75‧‧‧第一金屬層
109‧‧‧通孔開口
100‧‧‧第三層間介電層
110、110A、110B‧‧‧通孔插塞
315‧‧‧通道區
370‧‧‧層間介電層
第1A圖係本發明一實施例中，半導體裝置於製程的多個階段之一者的上視圖。
第1B圖係沿著第1A圖中X1-X1剖線的剖視圖。
第1C圖係閘極結構的放大圖。
第1D圖係本發明一實施例中，半導體裝置於製程的多個階段之一者的透視圖。
第2至9圖係本發明一實施例中，半導體裝置於製程的多個階段沿著第1A圖中X1-X1剖線的剖視圖。
第10A至10C圖係本發明一些實施例的剖視圖。
第11A至11C圖係本發明一些實施例的剖視圖。
第12圖係本發明另一實施例的剖視圖。
第13圖係本發明另一實施例的剖視圖。
第14至17圖係本發明另一實施例中，半導體裝置於製程的多個階段沿著第1A圖中X1-X1剖線的剖視圖。
第18至21圖係本發明另一實施例中，半導體裝置於製程的 多個階段沿著第1A圖中X1-X1剖線的剖視圖。
應理解的是，下述內容提供的不同實施例或實例可實施本發明實施例的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一結構於第二結構上的敘述包含兩者直接接觸，或兩者之間隔有其他額外結構而非直接接觸。多種結構可依不同比例繪示，以簡化並清楚說明。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。此外，用語「之組成為」可指「包含」或「由...組成」。
第1A與1B圖係本發明一實施例中，半導體裝置於多個製程之一者的圖式。第1A圖係上視圖，而第1B圖係沿著第1A圖中剖線X1-X1的剖視圖。
第1A與1B圖為形成金屬閘極結構後的半導體裝置之結構。在第1A與1B圖中，金屬閘極結構10形成於通道層(比如部份的鰭狀結構5)上，而蓋絕緣層20位於金屬閘極結構10上。鰭狀結構5位於基板1上，且自隔離絕緣層3凸起。在第2圖及其後圖式中，將省略基板1與絕緣層3以簡化圖式。在一些實施例中，金屬閘極結構10的厚度介於約15nm至約50nm之間。 在一些實施例中，蓋絕緣層20之厚度介於約10nm至約30nm之間。在其他實施例中，蓋絕緣層20之厚度介於約15nm至約20nm之間。側壁間隔物30位於金屬閘極結構10與蓋絕緣層20的側壁上。在一些實施例中，側壁間隔物30之底部的膜厚介於約3nm至約15nm之間。在其他實施例中，側壁間隔物30之底部的膜厚介於約4nm至約10nm之間。金屬閘極結構10、蓋絕緣層20、與側壁間隔物30的組合可稱作閘極結構。此外，源極/汲極區50形成於與閘極結構相鄰處，而接點蝕刻停止層33形成於閘極結構與源極/汲極區50上。在一些實施例中，接點蝕刻停止層33之膜厚介於約1nm至約20nm之間。閘極結構之間的空間可填有第一層間介電層40。矽化物層55更形成於源極/汲極區50上。在本發明實施例中，用語「源極」與「汲極」可交替使用，且兩者無實質上的結構差異。用語「源極/汲極」可為源極與汲極中的任一者。
矽化物層55包含一或多種鈷矽化物(如CoSi、CoSi2、Co2Si、Co3Si，統稱鈷矽化物)、鈦矽化物(如Ti5Si3、TiSi、TiSi2、TiSi3、Ti6Si4，統稱鈦矽化物)、鎳矽化物(如Ni3Si、Ni31Si12、Ni2Si、Ni3Si2、NiSi、NiSi2，統稱鎳矽化物)、銅矽化物(如Cu17Si3、Cu56Si11、Cu5Si、Cu33Si7、Cu4Si、Cu19Si6、Cu3Si、Cu87Si13，統稱銅矽化物)、鎢矽化物(W5Si3、WSi2，統稱鎢矽化物)、或鉬矽化物(Mo3Si、Mo5Si3、MoSi2，統稱鉬矽化物)。
第1C圖係閘極結構的放大圖。金屬閘極結構10包含一或多個金屬材料層16，比如鋁、銅、鎢、鈦、鉭、氮化鈦、 鈦鋁、碳化鈦鋁、氮化鈦鋁、氮化鉭、鎳矽、鈷矽、或其他導電材料。閘極介電層12位於通道層5與金屬閘極之間，且包含一或多個金屬氧化物層如高介電常數之金屬氧化物。用於高介電常數之介電層的金屬氧化物包含下述金屬的氧化物：Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu、及/或上述之組合。在一些實施例中，通道層5與高介電常數之閘極介電層12之間隔有界面層，其可為厚度介於0.6nm至2nm的氧化矽。
在一些實施例中，一或多個功函數調整層14夾設於閘極介電層12與金屬材料層16之間。功函數調整層14之組成可為導電材料，比如單層的TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi、或TiAlC；或者上述材料中兩者以上的多層。對n型通道的場效電晶體來說，TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi、與TaSi中的一或多者作為功函數調整層。對p型通道的場效電晶體來說，TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC、與Co中的一或多者作為功函數調整層。
蓋絕緣層20包含一或多層的絕緣材料如氮化矽為主的材料，比如SiN、SiCN、或SiOCN。側壁間隔物30之組成材料與蓋絕緣層20不同，且可包含一或多層的絕緣材料如氮化矽為主的材料，比如SiN、SiON、SiCN、或SiOCN。接點蝕刻停止層33之組成與蓋絕緣層20及側壁間隔物30不同，且可包含一或多層的絕緣材料如氮化矽為主的材料，比如SiN、SiON、SiCN、或SiOCN。層間介電層40包含一或多層的氧化矽、SiOC、 SiOCN、SiCN、其他低介電常數的材料、或孔洞材料。第一層間介電層40之形成方法可為低壓化學氣相沉積、電漿化學氣相沉積、或其他合適的成膜方法。
接點蝕刻停止層33、側壁間隔物30、蓋絕緣層20、與第一層間介電層40之材料可彼此不同，因此可選擇性地蝕刻這些層狀物。在一實施例中，接點蝕刻停止層之組成為SiN，側壁間隔物30之組成為SiOCN、SiCN、或SiON，蓋絕緣層20之組成為SiN或SiON，且第一層間介電層40之組成為氧化矽。
在此實施例中，鰭狀物場效電晶體之製程為閘極置換製程。
第1D圖係鰭狀物場效電晶體結構的透視圖。鰭狀物場效電晶體結構可由下述步驟製作。
首先，鰭狀結構310形成於基板300上。鰭狀結構包含底部區與較上區(如通道區315)。舉例來說，基板可為p型矽基板，其雜質濃度介於約1>1015cm-3至約1>1018cm-3之間。在其他實施例中，基板為n型矽基板，其雜質濃度介於約1×1015cm-3至約1×1018cm-3之間。在其他實施例中，基板可包含另一半導體元素如鍺、半導體化合物如IV-IV族半導體化合物(如SiC或SiGe)、III-V族半導體化合物(如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP)、或上述之組合。在一實施例中，基板可為絕緣層上矽基板的矽層。
在形成鰭狀結構310後，形成隔離絕緣層320於鰭狀結構310上。隔離絕緣層320包含一或多層的絕緣材料，比如 氧化矽、氮氧化矽、或氮化矽，其形成方法可為低壓化學氣相沉積、電漿化學氣相沉積、可流動的化學氣相沉積。隔離絕緣層320亦可為一或多層形成，比如旋轉塗佈玻璃、氧化矽、SiON、SiOCN、及/或摻雜氟的矽酸鹽玻璃。
在形成隔離絕緣層320於鰭狀結構上之後，進行平坦化步驟以移除部份的隔離絕緣層320。平坦化步驟可包含化學機械研磨及/或回蝕刻製程。接著，可進一步移除(凹陷化)隔離絕緣層，以露出鰭狀結構的較上區。
接著形成虛置閘極結構於露出的鰭狀結構上。虛置閘極結構包含虛置閘極層(由多晶矽組成)與虛置閘極介電層。側壁間隔物350包含一或多層的絕緣材料，其亦形成於虛置閘極層的側壁上。在形成虛置閘極結構後，虛置閘極結構未覆蓋的鰭狀結構310將凹陷至低於隔離絕緣層320的上表面。接著以磊晶成長法形成源極/汲極區360於凹陷的鰭狀結構上。源極/汲極區可包含應力材料，以施加應力至通道區315。
接著形成層間介電層370於虛置閘極結構與源極/汲極區上。層間介電層370包含一或多層的氧化矽、SiOC、SiOCN、SiCN、其他低介電常數材料、或孔洞材料。在平坦化步驟後，移除虛置閘極結構以形成閘極空間。接著形成金屬閘極結構330於閘極空間中，且金屬閘極結構330包含金屬閘極與閘極介電層(如高介電常數介電層)。此外，蓋絕緣層340形成於金屬閘極結構330上，以形成第1D圖所示之鰭狀物場效電晶體。在第1D圖中，省略部份的金屬閘極結構330、蓋絕緣層340、側壁間隔物350、與層間介電層370以顯示下方的結構。
第1D圖中的金屬閘極結構330、蓋絕緣層340、側壁間隔物350、源極/汲極區360、與層間介電層370，分別對應第1A與1B圖中的金屬閘極結構10、蓋絕緣層20、側壁間隔物30、源極/汲極區50、與第一層間介電層40。
第2至9圖係本發明一實施例中，半導體裝置於製程中的多個階段中沿著第1A圖之剖線X1-X1的剖視圖。應理解的是，在第2至9圖之製程之前、之中、或之後可進行額外步驟，且此方法之額外實施例可省略一些步驟或將其置換為其他步驟。步驟/製程的順序可交換。與前述實施例相同或類似的結構、設置、材料、及/或製程可用於下述實施例，且可省略相關的細節說明。
如第2圖所示，第二層間介電層60形成於第1B圖之結構上。第二層間介電層60的材料與形成製程，可與第一層間介電層40的材料與形成製程類似。在一些實施例中，形成於第一層間介電層40與第二層間介電層60之間的接點蝕刻停止層(未圖示)其組成可為SiN、SiC、或SiCN。
接著如第3圖所示，接點孔65形成於第一層間介電層40與第二層間介電層60中，以露出源極/汲極區之矽化物層55與金屬閘極結構10的金屬閘極之部份上表面。在一些實施例中，閘極矽化物層亦形成於金屬閘極結構上，且接點孔65亦露出閘極矽化物層。
在形成接點孔65後，毯覆性地形成黏著層70，接著形成第一金屬層75以覆蓋所有的上表面，如第4圖所示。
黏著層70包含一或多層的導電材料。在一些實施 例中，黏著層70包含TiN層形成於Ti層上。在一些實施例中，TiN層與Ti層的厚度合計約1nm至約13nm之間。黏著層70的形成方法可為化學氣相沉積、物理氣相沉積如濺鍍、原子層沉積、電鍍、上述之組合、或其他合適的成膜方法。黏著層70係用以避免第一金屬層75剝離。在一些實施例中，並未採用黏著層70，且第一金屬層75直接形成於接點孔中。在這些例子中，第一金屬層75直接接觸矽化物層55。
第一金屬層75係鈷、鎢、鉬、或銅。在一實施例中，鈷作為第一金屬層75。第一金屬層75的形成方法可為化學氣相沉積、物理氣相沉積、原子層沉積、電鍍、上述之組合、或其他合適的成膜方法。
在形成「厚」的第一金屬層之後，進行平坦化步驟如化學機械研磨或回蝕刻製程，以移第二層間介電層60之上表面上的黏著層與第一金屬層，如第5圖所示。
接著形成較上的矽化物層80於第一金屬層75之上表面上，如第6圖所示。在一些實施例中，矽化物層80包含的金屬元素與第一金屬層75相同。舉例來說，若第一金屬層75之組成為鈷，則矽化物層80為鈷矽化物。若第一金屬層75之組成為鎢，則矽化物層80為鎢矽化物。若第一金屬層75之組成為鉬，則矽化物層80為鉬矽化物。若第一金屬層75之組成為銅，則矽化物層80為銅矽化物。
當第一金屬層75由鈷所組成，可將SiH4及/或Si2H6氣體(矽烷氣體源)與一或多種稀釋氣體(如He或H2)導入真空腔室中，且具有第5圖之結構的基板亦置入此真空腔室。在提 供矽烷氣體之前先提供H2氣體，可還原第一金屬層(如鈷)的表面上之氧化物層(如氧化鈷)，以得乾淨與純粹的鈷表面。提供矽烷氣體時可搭配稀釋氣體如He及/或H2。以He及/或H2而非N2或其他氮源氣體作為稀釋氣體，由於該氣體熱傳導較佳，可成長較均勻的矽化物。
在一些實施例中，加熱基板至約300℃至約800℃之間。在此條件下，第一金屬層75之表面的鈷原子與來自矽烷源氣體的矽原子反應，形成鈷的矽化物層80。在一些實施例中，在形成鈷的矽化物層80後進行額外的回火步驟。額外的回火步驟其溫度介於約300℃至約800℃之間，且回火氣體為下述之一或多者：H2、NH3、He、與Ar。在一實施例中，回火氣體採用NH3。在一些實施例中，藉由上述步驟可得無突起的鈷矽層，其表面粗糙度介於約0.1nm至約2nm之間。
舉例來說，當溫度高至約700℃至800℃之間時，主要形成CoSi2。舉例來說，當溫度低至300℃至400℃之間時，主要形成Co2Si。當溫度介於約400℃至600℃時，主要形成CoSi。值得注意的是，CoSi2的電阻低於Co2Si或CoSi的電阻。此外，可進行額外熱步驟。
同樣地，當第一金屬層75之組成為Cu或Ti時，矽化物層80的形成方法可採用矽烷源氣體。
在其他實施例中，形成薄矽層(如多晶矽層或非晶矽層)於第5圖之結構上，接著進行回火步驟以形成矽化物層80於第一金屬層75上。在這些例子中，形成矽化物層後，以濕蝕刻移除第二層間介電層60上的矽層。在一些實施例中，矽化物 層80的厚度介於約3nm至約5nm之間。
接著形成接點蝕刻停止層90於矽化物層80與第二層間介電層60上，如第7圖所示。接點蝕刻停止層包含一或多層的SiN、SiC、SiCN、或SiON。在一些實施例中，接點蝕刻停止層90的厚度介於約10nm至約30nm之間。
接點蝕刻停止層90的形成方法可為電漿增強化學氣相沉積，其採用SiH4及/或S2H6氣體、氮源氣體(如N2或NH3)、碳源氣體(如CH4)、及/或氧源氣體(如O2)。由於採用相同的矽烷類氣體，沉積接點蝕刻停止層90與形成矽化物層80(如鈷矽化物)的製程可進行於相同的真空腔室或相同的形成工具，只需簡單改變源氣體與其他參數(如溫度或壓力)。在一實施例中，在沉積接點蝕刻停止層前，先提供氮源氣體如NH3。如此一來，形成接點蝕刻停止層的步驟，將使殘留於第二層間介電層60之表面上的Si形成介電材料(如SiN)。
接著如第8圖所示，形成第三層間介電層100於接點蝕刻停止層90上。第三層間介電層100的材料與形成製程，與第一層間介電層40及/或第二層間介電層60之材料與形成製程類似。此外，接點開口109形成於第三層間介電層100與接點蝕刻停止層90中。在一些實施例中，形成接點開口109的蝕刻步驟停止於矽化物層80上。換言之，矽化物層80可作為蝕刻停止層。在其他實施例中的接點蝕刻製程時，蝕刻並移除接點開口之底部的矽化物層80。
此外，通孔插塞110形成於接點開口109中，以電性連接至第一金屬層75，如第9圖所示。通孔插塞110包含一或 多層的導電材料如TiN、Ti、Cu、Al、W、上述之合金、或其他合適材料。
應理解的是可對第9圖之裝置進行額外的互補金氧半製程，以形成多種結構如內連線金屬層、介電層、保護層、與類似物。
第10A至10C圖係本發明一些實施例的剖視圖。第10A至10C圖僅顯示結構的相關部份。
在第10A圖中，矽化物層80完全覆蓋第一金屬層75的上表面。第10B與10C圖不同於第10A圖，矽化物層80只覆蓋第一金屬層75其部份的上表面。在第10B圖中，矽化物層80只形成於通孔插塞110下。在第10C圖中，矽化物層80形成於第一金屬層75的上表面上，除了通孔插塞110形成處。在一些實施例中，在形成接點開口109後，移除矽化物層80以形成第10C圖的結構。移除矽化物層80的方法可為電漿處理或離子轟擊處理。接著選擇性的成長金屬材料(如鈷)，使移除矽化物後形成的凹陷填有金屬材料。
第11A至11C圖係本發明一些實施例的剖視圖。第11A至11C圖僅顯示結構的相關部份。
依據形成接點開口109的接點蝕刻條件(比如過蝕刻條件)，通孔插塞的底部位置將有所不同。在第11A圖中，通孔插塞110的底部位於矽化物層80的上表面。在第11B圖中，通孔插塞110的底部位於矽化物層80其沿著Z方向的中間處。換言之，通孔插塞110部份地埋置於矽化物層80中。在第11C圖中，通孔插塞110接觸第一金屬層75的上表面。換言之，通孔插塞 110穿過矽化物層80。
第12圖係本發明另一實施例的剖視圖。第12圖僅顯示結構的相關部份。
在第12圖中，形成相對厚的矽化物層80。在一些實施例中，矽化物層80的厚度介於約5nm至約10nm之間。如第12圖所示，矽化物層80自第二層間介電層的上表面凸起。綜上所述，接點蝕刻停止層90具有隆起的階狀物。在一些實施例中，位於第二層間介電層上的接點蝕刻停止層90之上表面，與位於矽化物層80上的接點蝕刻停止層90之上表面之間的高度差異H1，介於約0.5nm至約4nm之間。
第13圖係本發明另一實施例的剖視圖。在一些實施例中，第一金屬層75具有實質上矩形的形狀，且可沿著平面圖的Y向延伸。在這些例子中，兩個以上的通孔插塞110A與110B位於第一金屬層75上，如第13圖所示。
第14至17圖係本發明另一實施例中，半導體裝置於製程中的多個階段中沿著第1A圖之剖線X1-X1的剖視圖。應理解的是，在第14至17圖之製程之前、之中、或之後可進行額外步驟，且此方法之額外實施例可省略一些步驟或將其置換為其他步驟。步驟/製程的順序可交換。與前述實施例相同或類似的結構、設置、材料、及/或製程可用於下述實施例，且可省略相關的細節說明。
與第6及7圖之結構與製程不同，接點蝕刻停止層90與第三層間介電層100形成於第5圖之結構上，而不形成矽化物層於第一金屬層75上，如第14圖所示。此外，接點開口109 形成於第三層間介電層100與接點蝕刻停止層90中，以露出第一金屬層75的部份上表面，如第15圖所示。
接著形成矽化物層80於接點開口109之底部的第一金屬層75的上表面上。矽化物層的形成方法可與前述類似。
接著形成通孔插塞110於通孔開口109中，如第17圖所示。第17圖與第10B圖類似，矽化物層80只形成於通孔插塞110下。在一些實施例中，接點蝕刻停止層90的厚度大於或等於通孔插塞110的一半高度。
第18至21圖係本發明另一實施例中，半導體裝置於製程中的多個階段中沿著第1A圖之剖線X1-X1的剖視圖。應理解的是，在第18至21圖之製程之前、之中、或之後可進行額外步驟，且此方法之額外實施例可省略一些步驟或將其置換為其他步驟。步驟/製程的順序可交換。與前述實施例相同或類似的結構、設置、材料、及/或製程可用於下述實施例，且可省略相關的細節說明。
在前述實施例中，在形成接點蝕刻停止層與接點孔65(如第2與3圖所示)之前，先形成矽化物層55。如第18圖所示之下述實施例中，未形成矽化物層於源極/汲極區50上即形成接點蝕刻停止層33。接著如第19圖所示，形成接點孔65以露出部份源極/汲極區50。
接著形成矽化物層55於源極/汲極區50上，如第20圖所示。藉由與第4至5圖所述之步驟類似的方法，可形成黏著層70(視情況，非必要)與第一金屬層75，如第21圖所示。在第21圖中，矽化物層55只形成於源極/汲極區50之間的界面，而 接點蝕刻停止層33直接接觸源極/汲極區50。
矽化物層55亦形成於金屬閘極結構10上的接點孔之底部，如第20圖所示。
在形成第21圖所示之結構後，進行前述實施例解釋的步驟以形成通孔插塞110。
與現有技術相較，上述多種實施例或實施例具有多種優點。舉例來說，本發明實施例之矽化物層(如鈷矽化物)形成於第一金屬層(如鈷)的表面上，矽化物層可作為保護層以保護下方的金屬層(如鈷)在空氣與後續製程步驟中免於氧化或損傷。此外，當形成用於通孔插塞之接點開口時，矽化物層可作為蝕刻停止層，比避免通孔穿透至下方層。此外，矽化物層可選擇性地形成於第一金屬層的表面上(換言之，只成長在金屬表面而不成長在絕緣層)，且矽化物層與接點蝕刻停止層可形成於相同的真空腔室或相同的沉積膜工具中。上述特徵可降低電阻，避免漏電流以及過度蝕刻。若矽化物層沉積於整片晶圓上並轉換成矽化物層，而不是選擇性的生長在第一金屬層表面，則其餘的矽化物將成為第一金屬層之間漏電路徑，導致額外漏電流。
應理解的是，上述內容不需說明所有優點，並非所有的實施例或例子均需包含特定優點，且其他實施例或實例自可具有不同優點。
在本發明一實施例中，半導體裝置的形成方法包括：形成第一接點孔於源極/汲極區或閘極上的一或多個介電層中。形成黏著層於第一接點孔中。形成第一金屬層於第一接 點孔中的黏著層上。形成矽化物層於第一金屬層的上表面上。矽化物層包含的金屬元素與第一金屬層相同。
在本發明另一實施例中，半導體裝置的形成方法包括：形成第一接點孔於源極/汲極區或閘極上的一或多個介電層中。形成第一金屬層於第一接點孔中。形成較上矽化物層於第一金屬層的上表面上。源極/汲極區與閘極中至少一者包含較下矽化物層。第一金屬層接觸較下矽化物層。較上矽化物層覆蓋第一金屬層的至少部份上表面。較上矽化物層包含的金屬元素與第一金屬層相同。
在本發明另一實施例中，半導體裝置包括場效電晶體，且包括源極/汲極區；源極/汲極矽化物層，形成於源極/汲極區上；以及第一接點，連接至源極/汲極矽化物層。第一接點包括第一金屬層。第一金屬層的上表面至少被矽化物層覆蓋。矽化物層包含的金屬元素與第一金屬層相同。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明實施例。本技術領域中具有通常知識者應理解可採用本發明實施例作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明實施例之精神與範疇，並可在未脫離本發明實施例之精神與範疇的前提下進行改變、替換、或更動。

Claims (14)

  1. 一種半導體裝置的形成方法，包括：形成一第一接點孔於一源極/汲極區或一閘極上的一或多個介電層中；形成一黏著層於該第一接點孔中；形成一第一金屬層於該第一接點孔中的該黏著層上；形成一矽化物層於該第一金屬層的上表面上；以及形成一絕緣層接觸該矽化物層和該或該些介電層之最上層，其中該矽化物層包含的金屬元素與該第一金屬層相同。
  2. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中該絕緣層與該或該些介電層之最上層的材料不同。
  3. 如申請專利範圍第2項所述之半導體裝置的形成方法，更包括：形成一額外介電層於該絕緣層上；形成一第二接點孔於該額外介電層與該絕緣層中；以及形成一第二金屬層於該第一金屬層上以電性連接至該第一金屬層。
  4. 如申請專利範圍第3項所述之半導體裝置的形成方法，其中該第二金屬層直接接觸該矽化物層的上表面，或穿過該矽化物層以直接接觸該第一金屬層。
  5. 如申請專利範圍第1或2項所述之半導體裝置的形成方法，其中該源極/汲極區包含一源極/汲極矽化物層；以及該黏著層接觸該源極/汲極矽化物層。
  6. 如申請專利範圍第1或2項所述之半導體裝置的形成方法，其中該矽化物層覆蓋該第一金屬層的所有上表面。
  7. 如申請專利範圍第1或2項所述之半導體裝置的形成方法，其中該矽化物層覆蓋該第一金屬層的部份上表面。
  8. 如申請專利範圍第7項所述之半導體裝置的形成方法，更包括：形成一額外介電層於該絕緣層上；形成一第二接點孔於該額外介電層與該絕緣層中；以及形成一第二金屬層於該第一金屬層上以電性連接至該第一金屬層。
  9. 如申請專利範圍第8項所述之半導體裝置的形成方法，其中該第二金屬層直接接觸該第一金屬層或該矽化物層。
  10. 一種半導體裝置的形成方法，包括：形成一第一接點孔於一源極/汲極區或一閘極上的一或多個介電層中；形成一黏著層於該第一接點孔中；形成一第一金屬層於該第一接點孔中的該黏著層上；以及形成一較上矽化物層於該第一金屬層的上表面上；其中該源極/汲極區與該閘極中至少一者包含一較下矽化物層，該黏著層接觸該較下矽化物層，該較上矽化物層覆蓋該第一金屬層的至少部份上表面，該較上矽化物層的側面被該黏著層或該第一金屬層覆蓋，且該較上矽化物層包含的金屬元素與該第一金屬層相同。
  11. 如申請專利範圍第10項所述之半導體裝置的形成方法，更包括形成一絕緣層接觸較上矽化物層和該或該些介電層的最上層，其中該絕緣層與該或該些介電層的最上層的材料不同。
  12. 如申請專利範圍第11項所述之半導體裝置的形成方法，更包括：形成一額外介電層於該絕緣層上；形成一第二接點孔於該額外介電層與該絕緣層中；以及形成一第二金屬層於該第一金屬層上以電性連接至該第一金屬層。
  13. 一種半導體裝置，包括一場效電晶體，且包括：一源極/汲極區；一源極/汲極矽化物層，形成於該源極/汲極區上；以及一第一接點，連接至該源極/汲極矽化物層，其中：該第一接點包括一黏著層和一第一金屬層於該黏著層上；該第一金屬層的上表面至少被一矽化物層覆蓋，且該矽化物層的側面被該黏著層或該第一金屬層覆蓋；以及該矽化物層包含的金屬元素與該第一金屬層相同。
  14. 如申請專利範圍第13項所述之半導體裝置，更包括一介電層，其中該第一接點埋置於該介電層中，且該矽化物層自該介電層之上表面凸起。
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