TWI533418B - 用於半導體封裝結構之基板及其製造方法 - Google Patents

用於半導體封裝結構之基板及其製造方法 Download PDF

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Publication number
TWI533418B
TWI533418B TW102123100A TW102123100A TWI533418B TW I533418 B TWI533418 B TW I533418B TW 102123100 A TW102123100 A TW 102123100A TW 102123100 A TW102123100 A TW 102123100A TW I533418 B TWI533418 B TW I533418B
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Taiwan
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layer
circuit layer
dielectric layer
package substrate
pillars
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TW102123100A
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TW201403770A (zh
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陳天賜
李俊哲
王聖民
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日月光半導體製造股份有限公司
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
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    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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Description

用於半導體封裝結構之基板及其製造方法
本發明係關於一種封裝基板及其製造方法，詳言之，係關於一種具有柱體之封裝基板及其製造方法。
習知封裝基板具有複數個柱體以連接一半導體晶粒之焊料凸塊(Solder Bump)。在經過回焊(Reflow)製程後，該晶粒及該等柱體間會形成複數個焊料結合點(Solder Joints)，使得該晶粒接合(Bonded)至該等柱體，且確保彼此間之電性連接。該等柱體通常係利用電鍍方式形成。然而，電鍍槽(Plating Bath)中不可預測且多變的電鍍參數經常會導致過度電鍍(Over-Plating)或電鍍不足(Under-Plating)，如此接著，會導致電鍍後之柱體之頂面不共平面。此共平面問題對封裝後之焊料結合之可靠度有負面影響。細線路(Fine-Pitch)的焊料凸塊、晶圓級封裝(Wafer Level Packaging,WLP)及大尺寸基板對此問題特別敏感。此共平面問題主要導因於電流密度不均勻分佈，其在微尺寸(Micro-scale)圖案時特別嚴重。此電流密度不均勻分佈並非由導因於單一因素，而是多種因素，例如：電鍍槽的設計、化學添加物、電流密度的強度、所使用的電流種類、陽極和陰極的距離、攪拌方式、化學反應物濃度的維持、預清洗溶液、圖案的結構、配置及體積、高寬高比(High Aspect Ratio)等等。目前的製 造方法很難將該等柱體高度的偏差(Deviation)控制在5μm的範圍內。
本發明之一實施例係關於一種封裝基板，其包括一介電層、一電路層，位於介電層上或介電層內，及複數個柱體，位於電路層上。每一柱體具有一頂面，用以形成外部電性連接，且柱體之頂面彼此大致上共平面。
本發明之另一實施例係關於一種半導體封裝結構，其包括一介電層、一電路層，位於介電層上或介電層內，及複數個柱體，位於電路層上。每一柱體之頂端與介電層之上表面間之距離係定義為一高度，且每一柱體所對應之高度之值係大致上相等。
本發明之另一實施例係關於一種封裝基板之製造方法，其包括以下步驟：提供一具有一電路層之介電層，電路層係位於介電層上或介電層內；形成一光阻圖案鄰近於電路層，其中光阻圖案具有複數個開口；形成複數個柱體於光阻圖案之開口中，其中柱體係電性連接至電路層；平坦化柱體，使得每一柱體具有一頂面，且柱體之頂面彼此大致上共平面；及移除該光阻圖案。
1e‧‧‧本發明封裝基板之另一實施例
1‧‧‧本發明封裝基板之一實施例
1a‧‧‧本發明封裝基板之一實施例
1b‧‧‧本發明封裝基板之一實施例
1c‧‧‧本發明封裝基板之一實施例
1d‧‧‧本發明封裝基板之一實施例
1f‧‧‧本發明封裝基板之另一實施例
1g‧‧‧本發明封裝基板之另一實施例
1h‧‧‧本發明封裝基板之另一實施例
1i‧‧‧本發明封裝基板之另一實施例
1j‧‧‧本發明封裝基板之另一實施例
1k‧‧‧本發明封裝基板之另一實施例
1m‧‧‧本發明封裝基板之另一實施例
1n‧‧‧本發明封裝基板之另一實施例
2‧‧‧本發明半導體封裝結構之一實施例
2a‧‧‧本發明半導體封裝結構之另一實施例
2b‧‧‧本發明半導體封裝結構之另一實施例
2c‧‧‧本發明半導體封裝結構之另一實施例
2h‧‧‧本發明半導體封裝結構之另一實施例
2i‧‧‧本發明半導體封裝結構之另一實施例
2j‧‧‧本發明半導體封裝結構之另一實施例
2k‧‧‧本發明半導體封裝結構之另一實施例
10‧‧‧中心部
11‧‧‧導電通道
12‧‧‧上內電路層
14‧‧‧下內電路層
16‧‧‧上介電層
17‧‧‧上導電箔
18‧‧‧下介電層
19‧‧‧下導電箔
20‧‧‧上最外層電路層
22‧‧‧上晶種層
24‧‧‧上金屬層
26‧‧‧下最外層電路層
28‧‧‧下晶種層
30‧‧‧下金屬層
32‧‧‧上內連接金屬
34‧‧‧下內連接金屬
36‧‧‧柱體
37‧‧‧表面處理層
38‧‧‧上保護層
40‧‧‧下保護層
42‧‧‧上乾膜
44‧‧‧下乾膜
46‧‧‧上光阻圖案
48‧‧‧下光阻圖案
50‧‧‧陶瓷砂輪
52‧‧‧上晶粒
54‧‧‧上焊球
56‧‧‧底膠
58‧‧‧封裝材料
60‧‧‧下焊球
62‧‧‧上光阻層
64‧‧‧頂光阻層
66‧‧‧突出部
68‧‧‧頂光阻層
70‧‧‧鑽頭
72‧‧‧鑽頭
80‧‧‧載體
81‧‧‧第一介電層
82‧‧‧第二介電層
83‧‧‧第三介電層
84‧‧‧下電路層
85‧‧‧第一電路層
86‧‧‧第二電路層
87‧‧‧第三電路層
88‧‧‧柱體
89‧‧‧上保護層
90‧‧‧載體
91‧‧‧第一介電層
92‧‧‧第二介電層
93‧‧‧第三介電層
94‧‧‧下電路層
95‧‧‧第一電路層
96‧‧‧第二電路層
97‧‧‧第三電路層
98‧‧‧柱體
99‧‧‧上保護層
100‧‧‧內層結構
101‧‧‧中心部上表面
102‧‧‧中心部下表面
103‧‧‧貫穿孔
111‧‧‧導電金屬
112‧‧‧中心絕緣材料
161‧‧‧上介電層開口
162‧‧‧上介電層上表面
181‧‧‧下介電層開口
361‧‧‧柱體頂面
362‧‧‧凹陷部
363‧‧‧參考面
381‧‧‧上保護層開口
401‧‧‧下保護層開口
421‧‧‧上乾膜開口
441‧‧‧下乾膜開口
461‧‧‧上光阻圖案開口
462‧‧‧上光阻圖案上表面
621‧‧‧上光阻層開口
641‧‧‧頂光阻層開口
681‧‧‧頂光阻層開口
801‧‧‧載體上表面
802‧‧‧載體下表面
803‧‧‧上金屬箔
804‧‧‧下金屬箔
811‧‧‧第一介電層開口
821‧‧‧第二介電層開口
831‧‧‧第三介電層開口
851‧‧‧第一內連接金屬
861‧‧‧第二內連接金屬
871‧‧‧第三內連接金屬
881‧‧‧柱體頂面
891‧‧‧上保護層開口
901‧‧‧載體上表面
902‧‧‧載體下表面
903‧‧‧上金屬箔
904‧‧‧下金屬箔
911‧‧‧第一介電層開口
921‧‧‧第二介電層開口
931‧‧‧第三介電層開口
941‧‧‧第一內連接金屬
951‧‧‧第二內連接金屬
961‧‧‧第三內連接金屬
981‧‧‧柱體頂面
991‧‧‧下保護層
992‧‧‧上保護層開口
9031‧‧‧薄金屬層
9041‧‧‧薄金屬層
圖1顯示本發明封裝基板之一實施例之示意圖。
圖2至9顯示本發明封裝基板之製造方法之一實施例之示意圖。
圖10顯示本發明半導體封裝結構之一實施例之示意圖。
圖11顯示本發明半導體封裝結構之另一實施例之示意圖。
圖12至13顯示本發明封裝基板之製造方法之另一實施例之示意圖。
圖14顯示本發明半導體封裝結構之另一實施例之示意圖。
圖15顯示本發明封裝基板之製造方法之另一實施例之示意圖。
圖16顯示本發明半導體封裝結構之另一實施例之示意圖。
圖17顯示本發明封裝基板之另一實施例之示意圖。
圖18顯示本發明封裝基板之製造方法之另一實施例之示意圖。
圖19顯示本發明封裝基板之另一實施例之示意圖。
圖20顯示本發明封裝基板之另一實施例之示意圖。
圖21顯示本發明封裝基板之製造方法之另一實施例之示意圖。
圖22顯示本發明封裝基板之另一實施例之示意圖。
圖23顯示本發明半導體封裝結構之另一實施例之示意圖。
圖24至25顯示本發明封裝基板之製造方法之另一實施例之示意圖。
圖26顯示本發明半導體封裝結構之另一實施例之示意圖。
圖27顯示本發明半導體封裝結構之另一實施例之示意圖。
圖28顯示本發明封裝基板之製造方法之另一實施例之示意圖。
圖29顯示本發明半導體封裝結構之另一實施例之示意圖。
圖30顯示本發明封裝基板之另一實施例之示意圖。
圖31顯示本發明封裝基板之製造方法之另一實施例之示意圖。
圖32顯示本發明封裝基板之另一實施例之示意圖。
圖33至38顯示本發明封裝基板之製造方法之另一實施例之示意圖。
參考圖1，顯示本發明封裝基板之一實施例之示意圖。該封裝基板1包括一中心部10、複數個導電通道11、一上內電路層12、一下內電路層14、一上介電層16、一上導電箔17、一下介電層18、一下導電箔19、一上最外層電路層20、一下最外層電路層26、複數個上內連接金屬32、複數個下內連接金屬34、複數個柱體(Pillars)36、一上保護層38及一下保護層40。雖然該基板1例示為具有四層電路層，在其 他實施例中，該基板1可能具有僅有一層、二層、三層或五層或更多層電路層。
該中心部10具有一上表面101、一下表面102及複數個貫穿孔103。該中心部10可以是例如由纖維強化(Fiber-reinforced)樹脂材料及/或預浸材(Prepreg,PP)所製成以加強剛性。該等纖維可以例如是玻璃纖維，或KEVLAR®纖維(聚醯胺纖維(Aramid Fibers))。被纖維強化以使用於積層介電層材之樹脂材料包含ABF(Ajinomoto Build-up Film)、雙馬來亞醯胺(Bismaleimide Triazine,BT)、預浸材、聚醯亞胺(Polyimide,PI)、液晶高分子(Liquid Crystal Polymer,LCP)、環氧樹脂(Epoxy)、及其他樹脂材料。
該等導電通道11係位於該中心部10之該等貫穿孔103，且貫穿該該中心部10。每一該等導電通道11之二端分別物理接觸且電性連接該上內電路層12及該下內電路層14。在某些實施例中，該導電通道11具有一導電金屬111及一中心絕緣材料112。該導電金屬111係位於該貫穿孔103之側壁上且定義出一中心槽，且該中心絕緣材料112係位於該中心槽內。在其他實施例中，該導電金屬111可以填滿該貫穿孔103，而可省略該中心絕緣材料112。在某些實施例中，該導電金屬111之材質可以是銅。
該上內電路層12及該下內電路層14係鄰近該中心部10。在某些實施例中，該上內電路層12及該下內電路層14係分別位於該中心部10之該上表面101及該下表面102。該導電金屬111、該上內電路層12及該下內電路層14可以同時形成。因此，該上內電路層12及該下內電路層14之材質可以是銅。該上內電路層12及該下內電路層14可以具有複數個線路區段。該等線路區段具有跡線(Traces)或接墊(Pads)，且彼此電性絕緣。
該上介電層16係位於該上內電路層12上，且具有複數個開口161 以顯露部分該上內電路層12。該上導電箔17係位於該上介電層16上，且該等開口161貫穿該上導電箔17。該下介電層18係位於該下內電路層14上，且具有複數個開口181以顯露部分該下內電路層14。該下導電箔19係位於該下介電層18上，且該等開口181貫穿該下導電箔19。該上介電層16及該下介電層18之材質可以是非導電高分子，例如：聚醯亞胺(Polyimide,PI)、環氧樹脂(Epoxy)或苯基環丁烯(Benzocyclobutene,BCB)。或者，也可使用無機鈍化層，例如：二氧化矽(SiO2)。在某些實施例中，該上介電層16及該下介電層18可以是光敏感高分子，例如：苯基環丁烯(Benzocyclobutene,BCB)，且係利用旋轉塗佈(Spin Coating)或噴射塗佈(Spray Coating)而形成。
該上最外層電路層20係位於該上介電層16上，且該下最外層電路層26係位於該下介電層18上。該上最外層電路層20及該下最外層電路層26可以具有複數個區段。該等區段具有跡線或接墊，且彼此電性絕緣。在某些實施例中，該上最外層電路層20包括該上導電箔17、一上晶種層22及一上金屬層24。該上晶種層22之材質可以例如是氮化鉭(tantalum nitride)或鎢鉭(tantalum tungsten)，且該上金屬層24之材質可以例如是銅。然而，該上晶種層22及該上導電箔17可以省略，使得該上金屬層24係為最外層電路層20。同樣地，該下最外層電路層26包括該下導電箔19、一下晶種層28及一下金屬層30。該下晶種層28之材質可以例如是氮化鉭(tantalum nitride)或鎢鉭(tantalum tungsten)，且該下金屬層24之材質可以例如是銅。然而，該下晶種層28及該下導電箔19可以省略，使得該下金屬層30係為最外層電路層26。
該等上內連接金屬32係位於該上介電層16之該等開口161中，且物理接觸且電性連接該上內電路層12及該上最外層電路層20。在某些 實施例中，該上內連接金屬32包括該上晶種層22及該上金屬層24。然而，該上晶種層22可以省略，使得該上金屬層24係為上內連接金屬32。同樣地，該等下內連接金屬34係位於該下介電層18之該等開口181中，且物理接觸且電性連接該下內電路層14及該下最外層電路層26。在某些實施例中，該下內連接金屬34包括該下晶種層28及該下金屬層30。然而，該下晶種層28可以省略，使得該下金屬層30係為該下內連接金屬34。
該等柱體36係位於該上最外層電路層20上，且電性連接至該上內電路層12。每一柱體36可具有大致上圓柱之外形或大致上圓筒之外形。每一該等柱體36具有一頂面361，用以形成外部電性連接(例如：連接至一半導體晶粒上之另一電性連接)，且該等柱體36之該等頂面361係為平面且大致上共平面。在某些實施例中，該等柱體36之該等頂面361可利用機械加工形成共平面，以產生高良率及高可靠度。該等柱體36之該等頂面361之共平面性(Coplanarity)係為±3μm。換言之，該等柱體36的高度H與所需及預期的尺寸間的偏差(Deviation)係在±3μm的範圍內，其中該高度H係被定義為每一柱體36之頂面361與該上介電層16之上表面162間之距離。因此，該等高度H之最大值與該等高度H之最小值之差係為6μm或更小，亦即該等柱體36所對應之高度H之值係大致上相等。或者，該等高度H之最大值與該等高度H之最小值之差可以小於所需及預期的尺寸的10%。在某些實施例中，該等柱體36之材質係為銅，且所需及預期的高度H係約為60μm。
該上保護層38係位於該上最外層電路層20上，且具有至少一開口381以顯露部分該上最外層電路層20。該等柱體36係全部位於同一開口381中。亦即，該上保護層38並不位於該等柱體36間之空間。該下保護層40係位於該下最外層電路層26上，且具有複數個開口401。 每一開口401係顯露部分該下最外層電路層26，其中顯露之部分係可做為球墊(Ball Land)，例如一球柵陣列端點(Ball Grid Array Terminal)，以供一球柵陣列(Ball Grid Array)焊球形成於其上，如下所述。在某些實施例中，該上保護層38及該下保護層40係為防焊層(Solder Mask)，其係由例如聚醯亞胺(Polyimide,PI)所製成。
在本實施例中，該封裝基板1之該等柱體36之該等頂面361係為平坦且共平面。改善該等柱體36之該等頂面361之共平面性可以在封裝後形成較佳的焊料結合可靠度，尤其是當該等柱體36間之間距很小時。
參考圖2至9，顯示本發明封裝基板之製造方法之一實施例之示意圖。參考圖2，提供一內層結構(Inner-layer Structure)100。該內層結構100具有該中心部10、該等導電通道11、該上內電路層12及該下內電路層14。該中心部10具有一上表面101、一下表面102及複數個貫穿孔103。該中心部10可以是一預成型之預浸材(Prepreg)，其包括樹脂及玻璃纖維，或其他材料。該內層結構100係可利用選擇性圖案化一銅箔基板(Copper Clad Laminate,CCL)而成，該銅箔基板係由雙馬來亞醯胺(Bismaleimide Triazine,BT)或FR-4/FR-5環氧樹脂(Epoxies)所製成。
接著，分別形成該上介電層16及該下介電層18於該上內電路層12及該下內電路層14上。該上介電層16具有一上表面162。該上介電層16及該下介電層18之材質可以是非導電高分子，例如：聚醯亞胺(Polyimide,PI)、環氧樹脂(Epoxy)或苯基環丁烯(Benzocyclobutene,BCB)。或者，也可使用無機鈍化層，例如：二氧化矽(SiO2)。在某些實施例中，該上介電層16及該下介電層18可以是光敏感高分子，例如：苯基環丁烯(Benzocyclobutene,BCB)，且係利用旋轉塗佈(Spin Coating)或噴射塗佈(Spray Coating)而 形成。
接著，配置該上導電箔17於該上介電層16上，且配置該下導電箔19於該下介電層18上。該上導電箔17及該下導電箔19其中之一或二者可以利用壓合或其他製程所形成。在某些實施例中，該上導電箔17及該上介電層16係利用層壓(Laminating)一樹脂塗佈銅箔(Resin Coated Copper(RCC)Foil)於該內層結構100上而同時形成。同樣地，該下導電箔19及該下介電層18可利用層壓(Laminating)另一樹脂塗佈銅箔(Resin Coated Copper(RCC)Foil)於該內層結構100上而同時形成。
接著，形成複數個開口161以貫穿該上導電箔17及該上介電層16以顯露部分該上內電路層12。在某些實施例中，該等開口161可利用雷射鑽孔所形成。形成複數個開口181以貫穿該下導電箔19及該下介電層18以顯露部分該下內電路層14。如上所述，該上導電箔17及該下導電箔19可以省略。
參考圖3，形成該上晶種層22於該上導電箔17或該上介電層16(如果省略該上導電箔17)，且於該上介電層16之該等開口161中以接觸該上內電路層12。形成該下晶種層28於該下導電箔19或該下介電層18(如果省略該下導電箔19)，且於該下介電層18之該等開口181中以接觸該下內電路層14。該上晶種層22及該下晶種層28之其中之一或二者可利用無電電鍍或其他製程所形成。該上晶種層22及該下晶種層28可以是氮化鉭(tantalum nitride)或鎢鉭(tantalum tungsten)。
接著，形成一上乾膜42於該上晶種層22上。該上乾膜42具有複數個開口421以顯露該上晶種層22，且部分該等開口421係對應該上介電層16之該等開口161。形成一下乾膜44於該下晶種層28上。該下乾膜44具有複數個開口441以顯露該下晶種層28，且部分該等開口441係對應該下介電層18之該等開口181。
參考圖4，施加一金屬，例如銅，於該上乾膜42之該等開口421中以形成該上金屬層24。該金屬形成於該下乾膜44之該等開口441中以形成該下金屬層30。該上金屬層24及該下金屬層30之其中之一或二者可利用電鍍或其他製程所形成。
參考圖5，移除該上乾膜42及該下乾膜44。在本步驟中，該上最外層電路層20係形成於該上介電層16上，且該下最外層電路層26係形成於該下介電層18上。在某些實施例中，該上最外層電路層20包括一上晶種層22及一上金屬層24，且該下最外層電路層26包括一下晶種層28及一下金屬層30。該等上內連接金屬32係形成於該上介電層16之該等開口161中，且物理接觸且電性連接該上內電路層12及該上最外層電路層20。在某些實施例中，該上內連接金屬32包括該上晶種層22及該上金屬層24，且該等下內連接金屬34係位於該下介電層18之該等開口181中，且物理接觸且電性連接該下內電路層14及該下最外層電路層26。在本實施例之本步驟中，該上晶種層22及該下晶種層28還未被圖案化。
參考圖6，分別形成一上光阻圖案46及一下光阻圖案48於該上最外層電路層20及該下最外層電路層26上。該上光阻圖案46具有複數個開口461以顯露部分該上最外層電路層20。
參考圖7，施加一金屬，例如銅，於該上光阻圖案46之該等開口461中以形成該等柱體36。該等柱體36可利用例如電鍍或其他製程所形成。因此，該等柱體36係位於該最外層電路層20上，且經由該上最外層電路層20及該上內連接金屬32電性連接至該上內電路層12。
參考圖8，平坦化該等柱體36及上光阻圖案46，使得每一柱體36具有一頂面361，且該等柱體36之該等頂面361與該上光阻圖案46之上表面462大致上共平面。此平坦化步驟可以利用以下方式達成：研磨(Grinding)、拋光(Polishing)、研光(Lapping)、電漿製程 (Plasma Processing)、蝕刻(Etching)或其他製程。在某些實施例中，此平坦化步驟係利用研磨所達成，其使用陶瓷砂輪50或鑽石砂輪。不論使用何種方法，其較佳地移除在之前步驟中形成在該等柱體36上的突出部分，且薄化該上光阻圖案46，使得該等柱體36之該等頂面361與該上光阻圖案46之上表面462位於同一平面。
參考圖9，移除該上光阻圖案46及該下光阻圖案48。接著，移除未被該上金屬層24所覆蓋的該上晶種層22及部分該上導電箔17，使得該上最外層電路層20具有複數個區段，該等區段具有跡線或接墊，且彼此電性絕緣。同樣地，移除未被該下金屬層30所覆蓋的該下晶種層28及部分該下導電箔19，使得該下最外層電路層26具有複數個區段，該等區段具有跡線或接墊，且彼此電性絕緣。這些步驟可以利用例如蝕刻或其他減縮製程(Reduction Process)而達成。
接著，形成該上保護層38於該上最外層電路層20上以圍繞該等柱體36，且該上保護層38具有至少一開口381以顯露部分該上最外層電路層20。該等柱體36係位於同一開口381中。亦即，該上保護層38並不位於該等柱體36間之空間。形成該下保護層40於該下最外層電路層26上，且該下保護層40具有複數個開口401以顯露部分該下最外層電路層26。該上保護層38及該下保護層40之其中之一或二者可利用例如塗佈(Coating)或其他製程所形成。在某些實施例中，該上保護層38及該下保護層40係為防焊層(Solder Mask)，例如聚醯亞胺(Polyimide,PI)。因此，製得如圖1所示之該封裝基板1。
參考圖10，顯示本發明半導體封裝結構之一實施例之示意圖。該半導體封裝結構2包括該封裝基板1、一上晶粒52、複數個上焊球54、一底膠56、一封裝材料58及複數個下焊球60。該上晶粒52係附著至該封裝基板1。在某些實施例中，該上晶粒52之一表面可具有該等上焊球54，且每一該等上焊球54係接合至每一該等柱體36。該上焊球 54延伸至該柱體36之側壁。該底膠56係位於該上晶粒52及該封裝基板1之間以保護該等上焊球54及該等柱體36。該封裝材料58係位於該上保護層38上以包覆該上晶粒52及該底膠56。該等下焊球60係位於顯露在該下保護層40之該等開口401之該下最外層電路層26以做為外部連接。
參考圖11，顯示本發明半導體封裝結構之另一實施例之示意圖。本實施例之半導體封裝結構2a與圖10所示之半導體封裝結構2大致相同，且相同元件賦予相同標號。如圖11所示之本實施例中，封裝基板1a更包括複數個表面處理層37(例如：鎳/金)，位於該等柱體36之該等頂面361。該等表面處理層37並不延伸至該等柱體36之側壁。
參考圖12至13，顯示本發明封裝基板之製造方法之另一實施例之示意圖。本實施例之起始步驟和圖2至8相同，而不再重複敘述。參考圖12，一表面處理層37(例如：鎳/金)係形成於每一該等柱體36之該頂面361。該表面處理層37可利用例如電鍍或其他製程所形成。
參考圖13，移除該上光阻圖案46及該下光阻圖案48。接著，形成該上最外層電路層20及該下最外層電路層26，如圖9所示。在某些實施例中，該表面處理層37僅位於該柱體36之該頂面361，而不延伸至該柱體36之側壁。接著，形成該上保護層38於該上最外層電路層20上，且形成該下保護層40於該下最外層電路層26上。因此，製得如圖11所示之該封裝基板1a。
參考圖14，顯示本發明半導體封裝結構之另一實施例之示意圖。本實施例之半導體封裝結構2b與圖10所示之半導體封裝結構2大致相同，且相同元件賦予相同標號。如圖14所示之本實施例中，封裝基板1b之每一該等柱體36更具有一凹陷部362，位於該柱體36之頂端。該等凹陷部362有助於固定該等焊球54以防止封裝過程中該等焊球54及該等柱體36間之不對齊(Misalignment)。特言之，在封裝過程 之一實施例中，該晶粒52係置放於該封裝基板1b上以形成一中間組裝結構(Intermediate Assembly Structure)，且其焊球54係對齊所對應之柱體36。接著，在一爐中之回焊製程會形成焊料結合。當該中間組裝結構移動至該爐時，該等凹陷部362有助於固定該等焊球54以防止該等焊球54及該等柱體36間之不對齊。該凹陷部362具有一頂邊而形成一參考面363。該等柱體36之該等參考面363係大致上共平面，且該高度H係被定義為每一柱體36之參考面363與該上介電層16之上表面162間之距離。亦即，本實施例之該高度H相等於圖10之高度H。在某些實施例中，該凹陷部362具有一弧面，例如半球狀，且每一柱體36之參考面363與該凹陷部362之底部間之距離約為15μm。該焊球54填滿該凹陷部362且更延伸至該柱體36之側壁。
參考圖15，顯示本發明封裝基板之製造方法之另一實施例之示意圖。本實施例之起始步驟和圖2至8相同，而不再重複敘述。參考圖15，形成一上光阻層62於平坦化之該上光阻圖案46之上表面462，其中該上光阻層62具有複數個開口621以顯露該等柱體36之該等頂面361。接著，從位於該等開口621中之該等頂面361移除該等柱體36之頂端之一部分，以形成一凹陷部362於每一該等柱體36之該等頂面361。該凹陷部362可利用例如蝕刻或其他製程所形成。因此，每一該等柱體36之該等頂面361形成該參考面363，其係由該凹陷部362之頂邊所定義。接著，移除該上光阻層62，且本實施例之接續步驟與圖9相同。因此，製得如圖14所示之該封裝基板1b。
參考圖16，顯示本發明半導體封裝結構之另一實施例之示意圖。本實施例之半導體封裝結構2c與圖14所示之半導體封裝結構2b大致相同，且相同元件賦予相同標號。如圖16所示之本實施例中，封裝基板1c更包括複數個表面處理層37(例如：鎳/金)，僅位於該等柱體36之該等凹陷部362。亦即，該等表面處理層37並不延伸至該等柱體 36之側壁。該焊球54填滿該凹陷部362但不延伸至該柱體36之側壁。在製造方法中，該表面處理層37係形成於圖15之該凹陷部362上。
參考圖17，顯示本發明封裝基板之另一實施例之示意圖。本實施例之封裝基板1d與圖14所示之封裝基板1b大致相同，且相同元件賦予相同標號。圖17之封裝基板1d與圖14所示之封裝基板1b之不同處在於，本實施例之該凹陷部362之剖面具有一V形表面。
參考圖18，顯示本發明封裝基板之製造方法之另一實施例之示意圖。本實施例之起始步驟和圖2至8相同，而不再重複敘述。參考圖18，提供一鑽頭70，其剖面具有V形頭部。接著，以鑽孔(Drilling)方式從該等頂面361移除該等柱體36之頂端之一部分，以形成一凹陷部362於每一該等柱體36之該等頂面361。因此，該凹陷部362具有與該鑽頭70形狀對應之V形表面。接著，本實施例之接續步驟與圖9相同。因此，製得如圖17所示之該封裝基板1d。
參考圖19，顯示本發明封裝基板之另一實施例之示意圖。本實施例之封裝基板1e與圖17所示之封裝基板1d大致相同，且相同元件賦予相同標號。如圖19所示之本實施例中，封裝基板1e更包括複數個表面處理層37(例如：鎳/金)，僅位於該等柱體36之該等凹陷部362。亦即，該等表面處理層37並不延伸至該等柱體36之側壁。
參考圖20，顯示本發明封裝基板之另一實施例之示意圖。本實施例之封裝基板1f與圖14所示之封裝基板1b大致相同，且相同元件賦予相同標號。圖20之封裝基板1f與圖14所示之封裝基板1b之不同處在於，本實施例之該凹陷部362之剖面具有一梯形表面。
參考圖21，顯示本發明封裝基板之製造方法之另一實施例之示意圖。本實施例之起始步驟和圖2至8相同，而不再重複敘述。參考圖21，提供一鑽頭72，其剖面具有梯形頭部。接著，以鑽孔(Drilling)方式從該等頂面361移除該等柱體36之頂端之一部分，以 形成一凹陷部362於每一該等柱體36之該等頂面361。因此，該凹陷部362具有與該鑽頭70形狀對應之梯形表面。接著，本實施例之接續步驟與圖9相同。因此，製得如圖20所示之該封裝基板1f。
參考圖22，顯示本發明封裝基板之另一實施例之示意圖。本實施例之封裝基板1g與圖20所示之封裝基板1f大致相同，且相同元件賦予相同標號。如圖22所示之本實施例中，封裝基板1g更包括複數個表面處理層37(例如：鎳/金)，僅位於該等柱體36之該等凹陷部362。亦即，該等表面處理層37並不延伸至該等柱體36之側壁。
參考圖23，顯示本發明半導體封裝結構之另一實施例之示意圖。本實施例之半導體封裝結構2h與圖10所示之半導體封裝結構2大致相同，且相同元件賦予相同標號。如圖23所示之本實施例中，封裝基板1h之每一該等柱體36更具有一突出部66，其由該頂面361突出。在某些實施例中，該突出部66係位於該頂面361之外緣，且該突出部66之材質與該柱體36之材質可以相同或不同。
參考圖24至25，顯示本發明封裝基板之製造方法之另一實施例之示意圖。本實施例之起始步驟和圖2至8相同，而不再重複敘述。參考圖24，形成一頂光阻層64於平坦化之該上光阻圖案46之上表面462，其中該頂光阻層64具有複數個開口641以顯露該等柱體36之該等頂面361之一部分。
參考圖25，電鍍一金屬至該等開口641中之該等頂面361，以形成該突出部66於每一該等柱體36之該等頂面361。該突出部66之材質與該柱體36之材質可以相同或不同。接著，移除該頂光阻層64，且本實施例之接續步驟與圖9相同。因此，製得如圖23所示之該封裝基板1h。
參考圖26，顯示本發明半導體封裝結構之另一實施例之示意圖。本實施例之半導體封裝結構2i與圖23所示之半導體封裝結構2h大 致相同，且相同元件賦予相同標號。如圖26所示之本實施例中，封裝基板1i更包括複數個表面處理層37(例如：鎳/金)，僅位於該等柱體36之該等突出部66。亦即，該等表面處理層37並不延伸至該等柱體36之側壁。在製造方法中，該表面處理層37係形成於圖23之該突出部66上。
參考圖27，顯示本發明半導體封裝結構之另一實施例之示意圖。本實施例之半導體封裝結構2j與圖10所示之半導體封裝結構2大致相同，且相同元件賦予相同標號。如圖27所示之本實施例中，封裝基板1j之每一該等柱體36更具有一凹陷部362，其從該柱體36之頂端朝向該中心部10凹陷。該凹陷部362具有一頂邊而形成一參考面363，該等柱體36之該等參考面363係大致上共平面，且該高度H係被定義為每一柱體36之參考面363與該上介電層16之上表面162間之距離。亦即，本實施例之該高度H相等於圖10之高度H。在某些實施例中，該凹陷部362係位於該柱體36之頂端之外緣，而不延伸至該柱體36之底部。該焊球54更延伸至該柱體36之側壁。
參考圖28，顯示本發明封裝基板之製造方法之另一實施例之示意圖。本實施例之起始步驟和圖2至8相同，而不再重複敘述。參考圖28，形成一頂光阻層68於平坦化之該上光阻圖案46之上表面462，其中該頂光阻層68具有複數個開口681以顯露該等柱體36之該等頂面361之部分。接著，從位於該等開口681中之該等頂面361移除該等柱體36之每一頂端之一部分，以形成該凹陷部362於該等柱體36之每一該等頂端。此步驟可利用例如蝕刻或其他製程所達成。因此，每一該等柱體36之該等頂面361形成該參考面363，其係由該凹陷部362之頂邊所定義。接著，移除該頂光阻層68，且本實施例之接續步驟與圖9相同。因此，製得如圖27所示之該封裝基板1j。
參考圖29，顯示本發明半導體封裝結構之另一實施例之示意 圖。本實施例之半導體封裝結構2k與圖27所示之半導體封裝結構2j大致相同，且相同元件賦予相同標號。如圖29所示之本實施例中，封裝基板1k更包括複數個表面處理層37(例如：鎳/金)，僅位於該等柱體36之該等凹陷部362。亦即，該等表面處理層37並不延伸至該等柱體36之側壁。該焊球54填滿該凹陷部362但不延伸至該柱體36之側壁。在製造方法中，該表面處理層37係形成於圖28之該凹陷部362上。
參考圖30，顯示本發明封裝基板之另一實施例之示意圖。該封裝基板1m包括一第一介電層81、一第二介電層82、一第三介電層83、一下電路層84、一第一電路層85、一第二電路層86、一第三電路層87、複數個第一內連接金屬851、複數個第二內連接金屬861、複數個第三內連接金屬871、複數個柱體88及一上保護層89。雖然該基板1m例示為具有四層電路層，在其他實施例中，該基板1m可能具有僅有一層、二層、三層或五層或更多層電路層。
該第一介電層81之材質可以是非導電高分子，例如：聚醯亞胺(Polyimide,PI)、環氧樹脂(Epoxy)或苯基環丁烯(Benzocyclobutene,BCB)。或者，也可使用無機鈍化層，例如：二氧化矽(SiO2)。或者，該第一介電層81也可以是由纖維強化(Fiber-reinforced)樹脂材料及/或預浸材(Prepreg,PP)所製成以加強剛性。該等纖維可以例如是玻璃纖維，或KEVLAR®纖維(聚醯胺纖維(Aramid Fibers))。被纖維強化以使用於積層介電層材之樹脂材料包含ABF(Ajinomoto Build-up Film)、雙馬來亞醯胺(Bismaleimide Triazine,BT)、預浸材、聚醯亞胺(Polyimide,PI)、液晶高分子(Liquid Crystal Polymer,LCP)、環氧樹脂(Epoxy)、及其他樹脂材料。該第一介電層81具有複數個開口811以顯露部分該下電路層84。
該下電路層84係嵌於該第一介電層81，且顯露於該第一介電層81之下表面。在本實施例中，該下電路層84之下表面與該第一介電層 81之下表面係為共平面。該下電路層84之顯露之部分係可做為球墊(Ball Land)，例如一球柵陣列端點(Ball Grid Array Terminal)，以供一球柵陣列(Ball Grid Array)焊球形成於其上。
該第一電路層85係位於該第一介電層81之上表面上。該等第一內連接金屬851係位於該第一介電層81之該等開口811中，且物理接觸且電性連接該下電路層84及該第一電路層85。
該第二介電層82係位於該第一介電層81上，且具有複數個開口821以顯露部分該第一電路層85。該第二介電層82之材質與該第一介電層81之材質係相同或不同。該第二電路層86係位於該第二介電層81之上表面上。該等第二內連接金屬861係位於該第二介電層82之該等開口821中，且物理接觸且電性連接該第一電路層85及該第二電路層86。
該第三介電層83係位於該第二介電層82上，且具有複數個開口831以顯露部分該第二電路層86。該第三介電層82之材質與該第一介電層81之材質係相同或不同。該第三電路層87係位於該第三介電層83之上表面上。在本實施例中，該第三電路層87係為最上層電路層。該等第三內連接金屬871係位於該第三介電層83之該等開口831中，且物理接觸且電性連接該第二電路層86及該第三電路層87。
該等柱體88係位於該第三電路層87上，且電性連接至該第二電路層86及該第一電路層85。每一柱體88具有大致上圓柱之外形或大致上圓筒之外形。每一該等柱體88具有一頂面881，用以形成外部電性連接(例如：連接至一半導體晶粒上之另一電性連接)，且該等柱體88之該等頂面881係為平面且大致上共平面。
該上保護層89係位於該第三電路層87上，且具有至少一開口891以顯露部分該第三電路層87。該等柱體88係位於單一開口891中。在本實施例中，該上保護層89可以為防焊層(Solder Mask)，其係由例 如聚醯亞胺(Polyimide,PI)所製成。
參考圖31，顯示本發明封裝基板之製造方法之另一實施例之示意圖。提供一載體80，該載體80具有一上表面801、一下表面802、一上金屬箔803及一下金屬箔804，其中該上金屬箔803係位於該上表面801，該下金屬箔804係位於該下表面802。接著，形成該下電路層84於該上金屬箔803及該下金屬箔804上。該下電路層84之二個部份可以同時形成。接著，進行積層(Built-up)製程，以依序形成該第一介電層81、該第一電路層85、該等第一內連接金屬851、該第二介電層82、該第二電路層86、該等第二內連接金屬861、該第三介電層83、該第三電路層87及該等第三內連接金屬871於該載體80之二側，以在該載體80之二側形成二個封裝基板。
接著，形成一光阻圖案46於該第三電路層87上。該光阻圖案46具有複數個開口461以顯露部分該第三電路層87。接著，施加一金屬，例如銅，於該光阻圖案46之該等開口461中以形成該等柱體88。該等柱體88可利用例如電鍍或其他製程所形成。接著，平坦化該等柱體88及該光阻圖案46，使得每一柱體88具有一頂面881，且該等柱體88之該等頂面881與該上光阻圖案46之上表面462大致上共平面。在本實施例中，此平坦化步驟係可利用研磨所達成，其使用例如陶瓷砂輪或鑽石砂輪。接著，該二個封裝基板從該載體80卸下。
接著，移除該光阻圖案46，且形成該上保護層89於該第三電路層87上以圍繞該等柱體88，且該上保護層89具有至少一開口891以顯露部分該第三電路層87。該上保護層89可利用例如塗佈(Coating)所形成。該等柱體88係位於同一開口891中。因此，製得如圖30所示之該封裝基板1m。
參考圖32，顯示本發明封裝基板之另一實施例之示意圖。該封裝基板1n包括一第一介電層91、一第二介電層92、一第三介電層93、 一下電路層94、一第一電路層95、一第二電路層96、一第三電路層97、複數個第一內連接金屬941、複數個第二內連接金屬951、複數個第三內連接金屬961、複數個柱體98、一上保護層99及一下保護層991。雖然該基板1n例示為具有四層電路層，在其他實施例中，該基板1n可能具有僅有一層、二層、三層或五層或更多層電路層。
該第一介電層91之材質可以和圖30之該第一介電層81相同，且該第一介電層91具有複數個開口911。該下電路層94係位於該第一介電層91之下表面，且對應該等開口911。該下保護層991係位於該下電路層94上，且顯露部份該下電路層94。在本實施例中，該下保護層991係為防焊層(Solder Mask)，例如聚醯亞胺(Polyimide,PI)。該下電路層94之顯露之部分係可做為球墊(Ball Land)，例如一球柵陣列端點(Ball Grid Array Terminal)，以供一球柵陣列(Ball Grid Array)焊球形成於其上。
該第二介電層92係位於該第一介電層91上，且具有複數個開口921。該第二介電層92之材質與該第一介電層91之材質係相同或不同。該第一電路層95係位於該第二介電層92之下表面上。該等第一內連接金屬941係位於該第一介電層91之該等開口911中，且物理接觸且電性連接該下電路層94及該第一電路層95。
該第三介電層93係位於該第二介電層92上，且具有複數個開口931。該第三介電層93之材質與該第一介電層91之材質係相同或不同。該第二電路層96係位於該第三介電層93之下表面上。該等第二內連接金屬951係位於該第二介電層92之該等開口921中，且物理接觸且電性連接該第一電路層95及該第二電路層96。
該第三電路層97係嵌於該第三介電層93，且顯露於該第三介電層93之上表面。在本實施例中，該第三電路層97之上表面與該第三介電層93之上表面係為共平面。在本實施例中，該第三電路層97係為最 上層電路層。該等第三內連接金屬961係位於該第三介電層93之該等開口931中，且物理接觸且電性連接該第二電路層96及該第三電路層97。
該等柱體98係位於該第三電路層97上，且電性連接至該第二電路層96及該第一電路層95。每一柱體98具有大致上圓柱之外形或大致上圓筒之外形。每一該等柱體98具有一頂面981，用以形成外部電性連接(例如：連接至一半導體晶粒上之另一電性連接)，且該等柱體98之該等頂面981係為平面且大致上共平面。每一該等柱體98之底部可具有一薄金屬層9041以接觸該第三電路層97。然而，該薄金屬層9041可以省略。
該上保護層99係位於該第三電路層97上，且具有至少一開口992以顯露部分該第三電路層97。該等柱體98係位於單一開口992中。在本實施例中，該上保護層99可以為防焊層(Solder Mask)，其係由例如聚醯亞胺(Polyimide,PI)所製成。
參考圖33至38，顯示本發明封裝基板之製造方法之另一實施例之示意圖。參考圖33，提供一載體90，該載體90具有一上表面901、一下表面902、一上金屬箔903及一下金屬箔904，其中該上金屬箔903係位於該上表面901，該下金屬箔904係位於該下表面902。接著，形成該第三電路層97於該上金屬箔903及該下金屬箔904上。該第三電路層97之二個部份可以同時形成。接著，進行積層(Built-up)製程，以依序形成該第三介電層93、該第二電路層96、該等第三內連接金屬961、該第二介電層92、該第一電路層95、該等第二內連接金屬951、該第一介電層91、該下電路層94、該等第一內連接金屬941及該下保護層991於該載體90之二側，以在該載體90之二側形成二個封裝基板。
參考圖34，從該載體90卸下該二個封裝基板。部分該上金屬箔 903及該下金屬箔904可能殘留在該第三電路層97，以形成薄金屬層9031,9041在該第三電路層97上。該等薄金屬層9031,9041可以省略。
參考圖35，形成一上光阻圖案46於該薄金屬層9041或該第三電路層97上，且形成一下光阻圖案48於該下電路層94及該下保護層991。該上光阻圖案46具有複數個開口461以顯露部分該薄金屬層9041或該第三電路層97。
參考圖36，施加一金屬，例如銅，於該光阻圖案46之該等開口461中以形成該等柱體98。該等柱體98可利用例如電鍍或其他製程所形成。參考圖37，平坦化該等柱體98及該光阻圖案46，使得每一該等柱體98具有一頂面981，且該等柱體98之該等頂面981與該上光阻圖案46之上表面462大致上共平面。在本實施例中，此平坦化步驟係可利用研磨所達成，其使用例如陶瓷砂輪50或鑽石砂輪。
參考圖38，移除該光阻圖案46及該下光阻圖案48。接著，移除該薄金屬層9041未被該等柱體98所覆蓋的部分。接著，以塗佈方式形成該上保護層99於該第三電路層97上以圍繞該等柱體98，且該上保護層99具有至少一開口992以顯露部分該第三電路層97。該等柱體98係位於同一開口992中。因此，製得如圖32所示之該封裝基板1n。
惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
1‧‧‧本發明封裝基板之一實施例
10‧‧‧中心部
11‧‧‧導電通道
12‧‧‧上內電路層
14‧‧‧下內電路層
16‧‧‧上介電層
17‧‧‧上導電箔
18‧‧‧下介電層
19‧‧‧下導電箔
20‧‧‧上最外層電路層
22‧‧‧上晶種層
24‧‧‧上金屬層
26‧‧‧下最外層電路層
28‧‧‧下晶種層
30‧‧‧下金屬層
32‧‧‧上內連接金屬
34‧‧‧下內連接金屬
36‧‧‧柱體
38‧‧‧上保護層
40‧‧‧下保護層
100‧‧‧內層結構
101‧‧‧中心部上表面
102‧‧‧中心部下表面
103‧‧‧貫穿孔
111‧‧‧導電金屬
112‧‧‧中心絕緣材料
161‧‧‧上介電層開口
162‧‧‧上介電層上表面
181‧‧‧下介電層開口
361‧‧‧柱體頂面
381‧‧‧上保護層開口
401‧‧‧下保護層開口

Claims (13)

  1. 一種封裝基板，包括：一介電層；一第一電路層，位於該介電層上或該介電層內；複數個柱體，位於該第一電路層上，其中每一柱體具有一頂面，用以形成外部電性連接，且該等柱體之該等頂面彼此大致上共平面；一第二電路層；及複數個內連接金屬；其中該介電層具有複數個開口，且該等內連接金屬係位於該介電層之該等開口中以連接該第二電路層及該第一電路層。
  2. 如請求項1之封裝基板，更包括：一保護層，位於該第一電路層上，該保護層具有一開口以顯露部分該第一電路層及該等柱體。
  3. 如請求項1之封裝基板，其中該第一電路層係嵌於該介電層，且該第二電路層係位於該介電層上。
  4. 如請求項1之封裝基板，其中該第二電路層係嵌於該介電層，且該第一電路層係位於該介電層上。
  5. 如請求項1之封裝基板，其中該等柱體之該等頂面之共平面性係為±3μm。
  6. 一種封裝基板，包括：一介電層；一第一電路層，位於該介電層上或該介電層內；複數個柱體，位於該第一電路層上，其中每一柱體之頂端與該介電層之上表面間之距離係定義為一高度，且該等柱體所對 應之高度之值係大致上相等；一第二電路層；及複數個內連接金屬；其中該介電層具有複數個開口，且該等內連接金屬係位於該介電層之該等開口中以連接該第二電路層及該第一電路層。
  7. 如請求項6之封裝基板，其中該等高度之最大值與該等高度之最小值之差係小於6μm。
  8. 如請求項6之封裝基板，更包括一保護層，位於該第一電路層上，其中該保護層具有至少一開口，且該等柱體係位於同一開口中。
  9. 如請求項6之封裝基板，其中該第一電路層係嵌於該介電層，且該第二電路層係位於該介電層上。
  10. 如請求項6之封裝基板，其中該第二電路層係嵌於該介電層，且該第一電路層係位於該介電層上。
  11. 一種封裝基板之製造方法，包括以下步驟：提供一具有一第一電路層之介電層，該第一電路層係位於該介電層上或該介電層內，其包含：提供一具有一第二電路層之載體，該第二電路層係位於該載體上；形成該介電層於該第二電路層上，其中該介電層具有複數個開口以顯露該第二電路層；形成該第一電路層於該介電層上及複數個內連接金屬於該介電層之該等開口中以連接該第二電路層及該第一電路層；及移除該載體；形成一光阻圖案鄰近於該第一電路層，其中該光阻圖案具有複數個開口； 形成複數個柱體於該光阻圖案之該等開口中，其中該等柱體係電性連接至該第一電路層；平坦化該等柱體，使得每一柱體具有一頂面，且該等柱體之該等頂面彼此大致上共平面；及移除該光阻圖案。
  12. 如請求項11之製造方法，其中該光阻圖案係形成於該第二電路層上，且該等柱體係形成於該第二電路層上。
  13. 如請求項11之製造方法，其中該光阻圖案係形成於該第一電路層上，且該等柱體係形成於該第一電路層上。
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US8884443B2 (en) 2014-11-11
US9437532B2 (en) 2016-09-06
CN103531573A (zh) 2014-01-22
CN103531573B (zh) 2016-09-14
TW201403770A (zh) 2014-01-16
CN106158820B (zh) 2018-05-18
US9224707B2 (en) 2015-12-29
US20150021766A1 (en) 2015-01-22
US20140008814A1 (en) 2014-01-09

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