CN106158820B - 用于半导体封装结构的基板及其制造方法 - Google Patents

用于半导体封装结构的基板及其制造方法 Download PDF

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CN106158820B
CN106158820B CN201610657408.5A CN201610657408A CN106158820B CN 106158820 B CN106158820 B CN 106158820B CN 201610657408 A CN201610657408 A CN 201610657408A CN 106158820 B CN106158820 B CN 106158820B
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cylinder
layer
circuit layer
dielectric layer
package substrate
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CN106158820A (zh
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陈天赐
李俊哲
王圣民
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一封装基板包括一中心部、一上电路层及数个柱体。该多个柱体位于该上电路层上，且从该上电路层朝上。该多个柱体的顶面大致上共平面。该多个柱体提供电性连接至一半导体晶粒。借此，改善该基板及该半导体晶粒间的焊料结合可靠度。

Description

用于半导体封装结构的基板及其制造方法
本申请是2013年7月5日提交的，申请号为“201310282291.3”，发明名称为“用于半导体封装结构的基板及其制造方法”的中国发明专利申请的分案申请
技术领域
本发明关于一种封装基板及其制造方法，详言之，关于一种具有柱体的封装基板及其制造方法。
背景技术
已知封装基板具有数个柱体以连接一半导体晶粒的焊料凸块(Solder Bump)。在经过回焊(Reflow)工艺后，该晶粒及这些柱体间会形成数个焊料结合点(Solder Joints)，使得该晶粒接合(Bonded)至这些柱体，且确保彼此间的电性连接。这些柱体通常利用电镀方式形成。然而，电镀槽(Plating Bath)中不可预测且多变的电镀参数经常会导致过度电镀(Over-Plating)或电镀不足(Under-Plating)，如此接着，会导致电镀后的柱体的顶面不共平面。此共平面问题对封装后的焊料结合的可靠度有负面影响。细线路(Fine-Pitch)的焊料凸块、晶圆级封装(Wafer Level Packaging,WLP)及大尺寸基板对此问题特别敏感。此共平面问题主要导因于电流密度不均匀分布，其在微尺寸(Micro-scale)图案时特别严重。此电流密度不均匀分布并非由导因于单一因素，而是多种因素，例如：电镀槽的设计、化学添加物、电流密度的强度、所使用的电流种类、阳极和阴极的距离、搅拌方式、化学反应物浓度的维持、预清洗溶液、图案的结构、配置及体积、高宽高比(High Aspect Ratio)等等。目前的制造方法很难将这些柱体高度的偏差(Deviation)控制在5μm的范围内。
发明内容
本发明的一实施例关于一种封装基板，其包括一介电层、一电路层，位于介电层上或介电层内，及数个柱体，位于电路层上。每一柱体具有一顶面，用以形成外部电性连接，且柱体的顶面彼此大致上共平面。
本发明的另一实施例关于一种半导体封装结构，其包括一介电层、一电路层，位于介电层上或介电层内，及数个柱体，位于电路层上。每一柱体的顶端与介电层的上表面间的距离定义为一高度，且每一柱体所对应的高度的值大致上相等。
本发明的另一实施例关于一种封装基板的制造方法，其包括以下步骤：提供一具有一电路层的介电层，电路层位于介电层上或介电层内；形成一光阻图案邻近于电路层，其中光阻图案具有数个开口；形成数个柱体于光阻图案的开口中，其中柱体电性连接至电路层；平坦化柱体，使得每一柱体具有一顶面，且柱体的顶面彼此大致上共平面；及移除该光阻图案。
附图说明
图1显示本发明封装基板的一实施例的示意图。
图2至9显示本发明封装基板的制造方法的一实施例的示意图。
图10显示本发明半导体封装结构的一实施例的示意图。
图11显示本发明半导体封装结构的另一实施例的示意图。
图12至13显示本发明封装基板的制造方法的另一实施例的示意图。
图14显示本发明半导体封装结构的另一实施例的示意图。
图15显示本发明封装基板的制造方法的另一实施例的示意图。
图16显示本发明半导体封装结构的另一实施例的示意图。
图17显示本发明封装基板的另一实施例的示意图。
图18显示本发明封装基板的制造方法的另一实施例的示意图。
图19显示本发明封装基板的另一实施例的示意图。
图20显示本发明封装基板的另一实施例的示意图。
图21显示本发明封装基板的制造方法的另一实施例的示意图。
图22显示本发明封装基板的另一实施例的示意图。
图23显示本发明半导体封装结构的另一实施例的示意图。
图24至25显示本发明封装基板的制造方法的另一实施例的示意图。
图26显示本发明半导体封装结构的另一实施例的示意图。
图27显示本发明半导体封装结构的另一实施例的示意图。
图28显示本发明封装基板的制造方法的另一实施例的示意图。
图29显示本发明半导体封装结构的另一实施例的示意图。
图30显示本发明封装基板的另一实施例的示意图。
图31显示本发明封装基板的制造方法的另一实施例的示意图。
图32显示本发明封装基板的另一实施例的示意图。
图33至38显示本发明封装基板的制造方法的另一实施例的示意图。
具体实施方式
参考图1，显示本发明封装基板的一实施例的示意图。该封装基板1包括一中心部10、数个导电通道11、一上内电路层12、一下内电路层14、一上介电层16、一上导电箔17、一下介电层18、一下导电箔19、一上最外层电路层20、一下最外层电路层26、数个上内连接金属32、数个下内连接金属34、数个柱体(Pillars)36、一上保护层38及一下保护层40。虽然该基板1例示为具有四层电路层，在其他实施例中，该基板1可能具有仅有一层、二层、三层或五层或更多层电路层。
该中心部10具有一上表面101、一下表面102及数个贯穿孔103。该中心部10可以是例如由纤维强化(Fiber-reinforced)树脂材料及/或预浸材(Prepreg,PP)所制成以加强刚性。这些纤维可以例如是玻璃纤维，或纤维(聚酰胺纤维(Aramid Fibers))。被纤维强化以使用于积层介电层材的树脂材料包含ABF(Ajinomoto Build-up Film)、双马来亚酰胺(Bismaleimide Triazine,BT)、预浸材、聚酰亚胺(Polyimide,PI)、液晶高分子(Liquid Crystal Polymer,LCP)、环氧树脂(Epoxy)、及其他树脂材料。
这些导电通道11位于该中心部10的这些贯穿孔103，且贯穿该该中心部10。每一这些导电通道11的二端分别物理接触且电性连接该上内电路层12及该下内电路层14。在某些实施例中，该导电通道11具有一导电金属111及一中心绝缘材料112。该导电金属111位于该贯穿孔103的侧壁上且定义出一中心槽，且该中心绝缘材料112位于该中心槽内。在其他实施例中，该导电金属111可以填满该贯穿孔103，而可省略该中心绝缘材料112。在某些实施例中，该导电金属111的材质可以是铜。
该上内电路层12及该下内电路层14邻近该中心部10。在某些实施例中，该上内电路层12及该下内电路层14分别位于该中心部10的该上表面101及该下表面102。该导电金属111、该上内电路层12及该下内电路层14可以同时形成。因此，该上内电路层12及该下内电路层14的材质可以是铜。该上内电路层12及该下内电路层14可以具有数个线路区段。这些线路区段具有迹线(Traces)或接垫(Pads)，且彼此电性绝缘。
该上介电层16位于该上内电路层12上，且具有数个开口161以显露部分该上内电路层12。该上导电箔17位于该上介电层16上，且这些开口161贯穿该上导电箔17。该下介电层18位于该下内电路层14上，且具有数个开口181以显露部分该下内电路层14。该下导电箔19位于该下介电层18上，且这些开口181贯穿该下导电箔19。该上介电层16及该下介电层18的材质可以是非导电高分子，例如：聚酰亚胺(Polyimide,PI)、环氧树脂(Epoxy)或苯基环丁烯(Benzocyclobutene,BCB)。或者，也可使用无机钝化层，例如：二氧化硅(SiO2)。在某些实施例中，该上介电层16及该下介电层18可以是光敏感高分子，例如：苯基环丁烯(Benzocyclobutene,BCB)，且利用旋转涂布(Spin Coating)或喷射涂布(Spray Coating)而形成。
该上最外层电路层20位于该上介电层16上，且该下最外层电路层26位于该下介电层18上。该上最外层电路层20及该下最外层电路层26可以具有数个区段。这些区段具有迹线或接垫，且彼此电性绝缘。在某些实施例中，该上最外层电路层20包括该上导电箔17、一上晶种层22及一上金属层24。该上晶种层22的材质可以例如是氮化钽(tantalum nitride)或钨钽(tantalum tungsten)，且该上金属层24的材质可以例如是铜。然而，该上晶种层22及该上导电箔17可以省略，使得该上金属层24为最外层电路层20。同样地，该下最外层电路层26包括该下导电箔19、一下晶种层28及一下金属层30。该下晶种层28的材质可以例如是氮化钽(tantalum nitride)或钨钽(tantalum tungsten)，且该下金属层24的材质可以例如是铜。然而，该下晶种层28及该下导电箔19可以省略，使得该下金属层30为最外层电路层26。
这些上内连接金属32位于该上介电层16的这些开口161中，且物理接触且电性连接该上内电路层12及该上最外层电路层20。在某些实施例中，该上内连接金属32包括该上晶种层22及该上金属层24。然而，该上晶种层22可以省略，使得该上金属层24为上内连接金属32。同样地，这些下内连接金属34位于该下介电层18的这些开口181中，且物理接触且电性连接该下内电路层14及该下最外层电路层26。在某些实施例中，该下内连接金属34包括该下晶种层28及该下金属层30。然而，该下晶种层28可以省略，使得该下金属层30为该下内连接金属34。
这些柱体36位于该上最外层电路层20上，且电性连接至该上内电路层12。每一柱体36可具有大致上圆柱的外形或大致上圆筒的外形。每一这些柱体36具有一顶面361，用以形成外部电性连接(例如：连接至一半导体管芯上的另一电性连接)，且这些柱体36的这些顶面361为平面且大致上共平面。在某些实施例中，这些柱体36的这些顶面361可利用机械加工形成共平面，以产生高良率及高可靠度。这些柱体36的这些顶面361的共平面性(Coplanarity)为±3μm。换言之，这些柱体36的高度H与所需及预期的尺寸间的偏差(Deviation)在±3μm的范围内，其中该高度H被定义为每一柱体36的顶面361与该上介电层16的上表面162间的距离。因此，这些高度H的最大值与这些高度H的最小值的差为6μm或更小，亦即这些柱体36所对应的高度H的值大致上相等。或者，这些高度H的最大值与这些高度H的最小值的差可以小于所需及预期的尺寸的10％。在某些实施例中，这些柱体36的材质为铜，且所需及预期的高度H约为60μm。
该上保护层38位于该上最外层电路层20上，且具有至少一开口381以显露部分该上最外层电路层20。这些柱体36全部位于同一开口381中。亦即，该上保护层38并不位于这些柱体36间的空间。该下保护层40位于该下最外层电路层26上，且具有数个开口401。每一开口401显露部分该下最外层电路层26，其中显露的部分可做为球垫(Ball Land)，例如一球栅阵列端点(Ball Grid Array Terminal)，以供一球栅阵列(Ball Grid Array)焊球形成于其上，如下所述。在某些实施例中，该上保护层38及该下保护层40为防焊层(SolderMask)，其由例如聚酰亚胺(Polyimide,PI)所制成。
在本实施例中，该封装基板1的这些柱体36的这些顶面361为平坦且共平面。改善这些柱体36的这些顶面361的共平面性可以在封装后形成较佳的焊料结合可靠度，尤其是当这些柱体36间之间距很小时。
参考图2至9，显示本发明封装基板的制造方法的一实施例的示意图。参考图2，提供一内层结构(Inner-layer Structure)100。该内层结构100具有该中心部10、这些导电通道11、该上内电路层12及该下内电路层14。该中心部10具有一上表面101、一下表面102及数个贯穿孔103。该中心部10可以是一预成型的预浸材(Prepreg)，其包括树脂及玻璃纤维，或其他材料。该内层结构100可利用选择性图案化一铜箔基板(Copper Clad Laminate,CCL)而成，该铜箔基板由双马来亚酰胺(Bismaleimide Triazine,BT)或FR-4/FR-5环氧树脂(Epoxies)所制成。
接着，分别形成该上介电层16及该下介电层18于该上内电路层12及该下内电路层14上。该上介电层16具有一上表面162。该上介电层16及该下介电层18的材质可以是非导电高分子，例如：聚酰亚胺(Polyimide,PI)、环氧树脂(Epoxy)或苯基环丁烯(Benzocyclobutene,BCB)。或者，也可使用无机钝化层，例如：二氧化硅(SiO2)。在某些实施例中，该上介电层16及该下介电层18可以是光敏感高分子，例如：苯基环丁烯(Benzocyclobutene,BCB)，且利用旋转涂布(Spin Coating)或喷射涂布(Spray Coating)而形成。
接着，配置该上导电箔17于该上介电层16上，且配置该下导电箔19于该下介电层18上。该上导电箔17及该下导电箔19其中之一或二者可以利用压合或其他工艺所形成。在某些实施例中，该上导电箔17及该上介电层16利用层压(Laminating)一树脂涂布铜箔(Resin Coated Copper(RCC)Foil)于该内层结构100上而同时形成。同样地，该下导电箔19及该下介电层18可利用层压(Laminating)另一树脂涂布铜箔(Resin Coated Copper(RCC)Foil)于该内层结构100上而同时形成。
接着，形成数个开口161以贯穿该上导电箔17及该上介电层16以显露部分该上内电路层12。在某些实施例中，这些开口161可利用激光钻孔所形成。形成数个开口181以贯穿该下导电箔19及该下介电层18以显露部分该下内电路层14。如上所述，该上导电箔17及该下导电箔19可以省略。
参考图3，形成该上晶种层22于该上导电箔17或该上介电层16(如果省略该上导电箔17)，且于该上介电层16的这些开口161中以接触该上内电路层12。形成该下晶种层28于该下导电箔19或该下介电层18(如果省略该下导电箔19)，且于该下介电层18的这些开口181中以接触该下内电路层14。该上晶种层22及该下晶种层28的其中之一或二者可利用无电电镀或其他工艺所形成。该上晶种层22及该下晶种层28可以是氮化钽(tantalumnitride)或钨钽(tantalum tungsten)。
接着，形成一上干膜42于该上晶种层22上。该上干膜42具有数个开口421以显露该上晶种层22，且部分这些开口421对应该上介电层16的这些开口161。形成一下干膜44于该下晶种层28上。该下干膜44具有数个开口441以显露该下晶种层28，且部分这些开口441对应该下介电层18的这些开口181。
参考图4，施加一金属，例如铜，于该上干膜42的这些开口421中以形成该上金属层24。该金属形成于该下干膜44的这些开口441中以形成该下金属层30。该上金属层24及该下金属层30的其中之一或二者可利用电镀或其他工艺所形成。
参考图5，移除该上干膜42及该下干膜44。在本步骤中，该上最外层电路层20形成于该上介电层16上，且该下最外层电路层26形成于该下介电层18上。在某些实施例中，该上最外层电路层20包括一上晶种层22及一上金属层24，且该下最外层电路层26包括一下晶种层28及一下金属层30。这些上内连接金属32形成于该上介电层16的这些开口161中，且物理接触且电性连接该上内电路层12及该上最外层电路层20。在某些实施例中，该上内连接金属32包括该上晶种层22及该上金属层24，且这些下内连接金属34位于该下介电层18的这些开口181中，且物理接触且电性连接该下内电路层14及该下最外层电路层26。在本实施例的本步骤中，该上晶种层22及该下晶种层28还未被图案化。
参考图6，分别形成一上光阻图案46及一下光阻图案48于该上最外层电路层20及该下最外层电路层26上。该上光阻图案46具有数个开口461以显露部分该上最外层电路层20。
参考图7，施加一金属，例如铜，于该上光阻图案46的这些开口461中以形成这些柱体36。这些柱体36可利用例如电镀或其他工艺所形成。因此，这些柱体36位于该最外层电路层20上，且经由该上最外层电路层20及该上内连接金属32电性连接至该上内电路层12。
参考图8，平坦化这些柱体36及上光阻图案46，使得每一柱体36具有一顶面361，且这些柱体36的这些顶面361与该上光阻图案46的上表面462大致上共平面。此平坦化步骤可以利用以下方式达成：研磨(Grinding)、抛光(Polishing)、研光(Lapping)、等离子工艺(Plasma Processing)、蚀刻(Etching)或其他工艺。在某些实施例中，此平坦化步骤利用研磨所达成，其使用陶瓷砂轮50或钻石砂轮。不论使用何种方法，其较佳地移除在之前步骤中形成在这些柱体36上的突出部分，且薄化该上光阻图案46，使得这些柱体36的这些顶面361与该上光阻图案46的上表面462位于同一平面。
参考图9，移除该上光阻图案46及该下光阻图案48。接着，移除未被该上金属层24所覆盖的该上晶种层22及部分该上导电箔17，使得该上最外层电路层20具有数个区段，这些区段具有迹线或接垫，且彼此电性绝缘。同样地，移除未被该下金属层30所覆盖的该下晶种层28及部分该下导电箔19，使得该下最外层电路层26具有数个区段，这些区段具有迹线或接垫，且彼此电性绝缘。这些步骤可以利用例如蚀刻或其他减缩工艺(ReductionProcess)而达成。
接着，形成该上保护层38于该上最外层电路层20上以围绕这些柱体36，且该上保护层38具有至少一开口381以显露部分该上最外层电路层20。这些柱体36位于同一开口381中。亦即，该上保护层38并不位于这些柱体36间的空间。形成该下保护层40于该下最外层电路层26上，且该下保护层40具有数个开口401以显露部分该下最外层电路层26。该上保护层38及该下保护层40的其中之一或二者可利用例如涂布(Coating)或其他工艺所形成。在某些实施例中，该上保护层38及该下保护层40为防焊层(Solder Mask)，例如聚酰亚胺(Polyimide,PI)。因此，制得如图1所示的该封装基板1。
参考图10，显示本发明半导体封装结构的一实施例的示意图。该半导体封装结构2包括该封装基板1、一上晶粒52、数个上焊球54、一底胶56、一封装材料58及数个下焊球60。该上晶粒52附着至该封装基板1。在某些实施例中，该上晶粒52的一表面可具有这些上焊球54，且每一这些上焊球54接合至每一这些柱体36。该上焊球54延伸至该柱体36的侧壁。该底胶56位于该上晶粒52及该封装基板1之间以保护这些上焊球54及这些柱体36。该封装材料58位于该上保护层38上以包覆该上晶粒52及该底胶56。这些下焊球60位于显露在该下保护层40的这些开口401的该下最外层电路层26以做为外部连接。
参考图11，显示本发明半导体封装结构的另一实施例的示意图。本实施例的半导体封装结构2a与图10所示的半导体封装结构2大致相同，且相同元件赋予相同标号。如图11所示的本实施例中，封装基板1a更包括数个表面处理层37(例如：镍/金)，位于这些柱体36的这些顶面361。这些表面处理层37并不延伸至这些柱体36的侧壁。
参考图12至13，显示本发明封装基板的制造方法的另一实施例的示意图。本实施例的起始步骤和图2至8相同，而不再重复叙述。参考图12，一表面处理层37(例如：镍/金)形成于每一这些柱体36的该顶面361。该表面处理层37可利用例如电镀或其他工艺所形成。
参考图13，移除该上光阻图案46及该下光阻图案48。接着，形成该上最外层电路层20及该下最外层电路层26，如图9所示。在某些实施例中，该表面处理层37仅位于该柱体36的该顶面361，而不延伸至该柱体36的侧壁。接着，形成该上保护层38于该上最外层电路层20上，且形成该下保护层40于该下最外层电路层26上。因此，制得如图11所示的该封装基板1a。
参考图14，显示本发明半导体封装结构的另一实施例的示意图。本实施例的半导体封装结构2b与图10所示的半导体封装结构2大致相同，且相同元件赋予相同标号。如图14所示的本实施例中，封装基板1b的每一这些柱体36更具有一凹陷部362，位于该柱体36的顶端。这些凹陷部362有助于固定这些焊球54以防止封装过程中这些焊球54及这些柱体36间的不对齐(Misalignment)。特言之，在封装过程的一实施例中，该管芯52置放于该封装基板1b上以形成一中间组装结构(Intermediate Assembly Structure)，且其焊球54对齐所对应的柱体36。接着，在一炉中的回焊工艺会形成焊料结合。当该中间组装结构移动至该炉时，这些凹陷部362有助于固定这些焊球54以防止这些焊球54及这些柱体36间的不对齐。该凹陷部362具有一顶边而形成一参考面363。这些柱体36的这些参考面363大致上共平面，且该高度H被定义为每一柱体36的参考面363与该上介电层16的上表面162间的距离。亦即，本实施例的该高度H相等于图10的高度H。在某些实施例中，该凹陷部362具有一弧面，例如半球状，且每一柱体36的参考面363与该凹陷部362的底部间的距离约为15μm。该焊球54填满该凹陷部362且更延伸至该柱体36的侧壁。
参考图15，显示本发明封装基板的制造方法的另一实施例的示意图。本实施例的起始步骤和图2至8相同，而不再重复叙述。参考图15，形成一上光阻层62于平坦化的该上光阻图案46的上表面462，其中该上光阻层62具有数个开口621以显露这些柱体36的这些顶面361。接着，从位于这些开口621中的这些顶面361移除这些柱体36的顶端的一部分，以形成一凹陷部362于每一这些柱体36的这些顶面361。该凹陷部362可利用例如蚀刻或其他工艺所形成。因此，每一这些柱体36的这些顶面361形成该参考面363，其由该凹陷部362的顶边所定义。接着，移除该上光阻层62，且本实施例的接续步骤与图9相同。因此，制得如图14所示的该封装基板1b。
参考图16，显示本发明半导体封装结构的另一实施例的示意图。本实施例的半导体封装结构2c与图14所示的半导体封装结构2b大致相同，且相同元件赋予相同标号。如图16所示的本实施例中，封装基板1c更包括数个表面处理层37(例如：镍/金)，仅位于这些柱体36的这些凹陷部362。亦即，这些表面处理层37并不延伸至这些柱体36的侧壁。该焊球54填满该凹陷部362但不延伸至该柱体36的侧壁。在制造方法中，该表面处理层37形成于图15的该凹陷部362上。
参考图17，显示本发明封装基板的另一实施例的示意图。本实施例的封装基板1d与图14所示的封装基板1b大致相同，且相同元件赋予相同标号。图17的封装基板1d与图14所示的封装基板1b的不同处在于，本实施例的该凹陷部362的剖面具有一V形表面。
参考图18，显示本发明封装基板的制造方法的另一实施例的示意图。本实施例的起始步骤和图2至8相同，而不再重复叙述。参考图18，提供一钻头70，其剖面具有V形头部。接着，以钻孔(Drilling)方式从这些顶面361移除这些柱体36的顶端的一部分，以形成一凹陷部362于每一这些柱体36的这些顶面361。因此，该凹陷部362具有与该钻头70形状对应的V形表面。接着，本实施例的接续步骤与图9相同。因此，制得如图17所示的该封装基板1d。
参考图19，显示本发明封装基板的另一实施例的示意图。本实施例的封装基板1e与图17所示的封装基板1d大致相同，且相同元件赋予相同标号。如图19所示的本实施例中，封装基板1e更包括数个表面处理层37(例如：镍/金)，仅位于这些柱体36的这些凹陷部362。亦即，这些表面处理层37并不延伸至这些柱体36的侧壁。
参考图20，显示本发明封装基板的另一实施例的示意图。本实施例的封装基板1f与图14所示的封装基板1b大致相同，且相同元件赋予相同标号。图20的封装基板1f与图14所示的封装基板1b的不同处在于，本实施例的该凹陷部362的剖面具有一梯形表面。
参考图21，显示本发明封装基板的制造方法的另一实施例的示意图。本实施例的起始步骤和图2至8相同，而不再重复叙述。参考图21，提供一钻头72，其剖面具有梯形头部。接着，以钻孔(Drilling)方式从这些顶面361移除这些柱体36的顶端的一部分，以形成一凹陷部362于每一这些柱体36的这些顶面361。因此，该凹陷部362具有与该钻头70形状对应的梯形表面。接着，本实施例的接续步骤与图9相同。因此，制得如图20所示的该封装基板1f。
参考图22，显示本发明封装基板的另一实施例的示意图。本实施例的封装基板1g与图20所示的封装基板1f大致相同，且相同元件赋予相同标号。如图22所示的本实施例中，封装基板1g更包括数个表面处理层37(例如：镍/金)，仅位于这些柱体36的这些凹陷部362。亦即，这些表面处理层37并不延伸至这些柱体36的侧壁。
参考图23，显示本发明半导体封装结构的另一实施例的示意图。本实施例的半导体封装结构2h与图10所示的半导体封装结构2大致相同，且相同元件赋予相同标号。如图23所示的本实施例中，封装基板1h的每一这些柱体36更具有一突出部66，其由该顶面361突出。在某些实施例中，该突出部66位于该顶面361的外缘，且该突出部66的材质与该柱体36的材质可以相同或不同。
参考图24至25，显示本发明封装基板的制造方法的另一实施例的示意图。本实施例的起始步骤和图2至8相同，而不再重复叙述。参考图24，形成一顶光阻层64于平坦化的该上光阻图案46的上表面462，其中该顶光阻层64具有数个开口641以显露这些柱体36的这些顶面361的一部分。
参考图25，电镀一金属至这些开口641中的这些顶面361，以形成该突出部66于每一这些柱体36的这些顶面361。该突出部66的材质与该柱体36的材质可以相同或不同。接着，移除该顶光阻层64，且本实施例的接续步骤与图9相同。因此，制得如图23所示的该封装基板1h。
参考图26，显示本发明半导体封装结构的另一实施例的示意图。本实施例的半导体封装结构2i与图23所示的半导体封装结构2h大致相同，且相同元件赋予相同标号。如图26所示的本实施例中，封装基板1i更包括数个表面处理层37(例如：镍/金)，仅位于这些柱体36的这些突出部66。亦即，这些表面处理层37并不延伸至这些柱体36的侧壁。在制造方法中，该表面处理层37形成于图23的该突出部66上。
参考图27，显示本发明半导体封装结构的另一实施例的示意图。本实施例的半导体封装结构2j与图10所示的半导体封装结构2大致相同，且相同元件赋予相同标号。如图27所示的本实施例中，封装基板1j的每一这些柱体36更具有一凹陷部362，其从该柱体36的顶端朝向该中心部10凹陷。该凹陷部362具有一顶边而形成一参考面363，这些柱体36的这些参考面363大致上共平面，且该高度H被定义为每一柱体36的参考面363与该上介电层16的上表面162间的距离。亦即，本实施例的该高度H相等于图10的高度H。在某些实施例中，该凹陷部362位于该柱体36的顶端的外缘，而不延伸至该柱体36的底部。该焊球54更延伸至该柱体36的侧壁。
参考图28，显示本发明封装基板的制造方法的另一实施例的示意图。本实施例的起始步骤和图2至8相同，而不再重复叙述。参考图28，形成一顶光阻层68于平坦化的该上光阻图案46的上表面462，其中该顶光阻层68具有数个开口681以显露这些柱体36的这些顶面361的部分。接着，从位于这些开口681中的这些顶面361移除这些柱体36的每一顶端的一部分，以形成该凹陷部362于这些柱体36的每一这些顶端。此步骤可利用例如蚀刻或其他工艺所达成。因此，每一这些柱体36的这些顶面361形成该参考面363，其由该凹陷部362的顶边所定义。接着，移除该顶光阻层68，且本实施例的接续步骤与图9相同。因此，制得如图27所示的该封装基板1j。
参考图29，显示本发明半导体封装结构的另一实施例的示意图。本实施例的半导体封装结构2k与图27所示的半导体封装结构2j大致相同，且相同元件赋予相同标号。如图29所示的本实施例中，封装基板1k更包括数个表面处理层37(例如：镍/金)，仅位于这些柱体36的这些凹陷部362。亦即，这些表面处理层37并不延伸至这些柱体36的侧壁。该焊球54填满该凹陷部362但不延伸至该柱体36的侧壁。在制造方法中，该表面处理层37形成于图28的该凹陷部362上。
参考图30，显示本发明封装基板的另一实施例的示意图。该封装基板1m包括一第一介电层81、一第二介电层82、一第三介电层83、一下电路层84、一第一电路层85、一第二电路层86、一第三电路层87、数个第一内连接金属851、数个第二内连接金属861、数个第三内连接金属871、数个柱体88及一上保护层89。虽然该基板1m例示为具有四层电路层，在其他实施例中，该基板1m可能具有仅有一层、二层、三层或五层或更多层电路层。
该第一介电层81的材质可以是非导电高分子，例如：聚酰亚胺(Polyimide,PI)、环氧树脂(Epoxy)或苯基环丁烯(Benzocyclobutene,BCB)。或者，也可使用无机钝化层，例如：二氧化硅(SiO2)。或者，该第一介电层81也可以是由纤维强化(Fiber-reinforced)树脂材料及/或预浸材(Prepreg,PP)所制成以加强刚性。这些纤维可以例如是玻璃纤维，或纤维(聚酰胺纤维(Aramid Fibers))。被纤维强化以使用于积层介电层材的树脂材料包含ABF(Ajinomoto Build-up Film)、双马来亚酰胺(Bismaleimide Triazine,BT)、预浸材、聚酰亚胺(Polyimide,PI)、液晶高分子(Liquid Crystal Polymer,LCP)、环氧树脂(Epoxy)、及其他树脂材料。该第一介电层81具有数个开口811以显露部分该下电路层84。
该下电路层84嵌于该第一介电层81，且显露于该第一介电层81的下表面。在本实施例中，该下电路层84的下表面与该第一介电层81的下表面为共平面。该下电路层84的显露的部分可做为球垫(Ball Land)，例如一球栅阵列端点(Ball Grid Array Terminal)，以供一球栅阵列(Ball Grid Array)焊球形成于其上。
该第一电路层85位于该第一介电层81的上表面上。这些第一内连接金属851位于该第一介电层81的这些开口811中，且物理接触且电性连接该下电路层84及该第一电路层85。
该第二介电层82位于该第一介电层81上，且具有数个开口821以显露部分该第一电路层85。该第二介电层82的材质与该第一介电层81的材质相同或不同。该第二电路层86位于该第二介电层81的上表面上。这些第二内连接金属861位于该第二介电层82的这些开口821中，且物理接触且电性连接该第一电路层85及该第二电路层86。
该第三介电层83位于该第二介电层82上，且具有数个开口831以显露部分该第二电路层86。该第三介电层82的材质与该第一介电层81的材质相同或不同。该第三电路层87位于该第三介电层83的上表面上。在本实施例中，该第三电路层87为最上层电路层。这些第三内连接金属871位于该第三介电层83的这些开口831中，且物理接触且电性连接该第二电路层86及该第三电路层87。
这些柱体88位于该第三电路层87上，且电性连接至该第二电路层86及该第一电路层85。每一柱体88具有大致上圆柱的外形或大致上圆筒的外形。每一这些柱体88具有一顶面881，用以形成外部电性连接(例如：连接至一半导体管芯上的另一电性连接)，且这些柱体88的这些顶面881为平面且大致上共平面。
该上保护层89位于该第三电路层87上，且具有至少一开口891以显露部分该第三电路层87。这些柱体88位于单一开口891中。在本实施例中，该上保护层89可以为防焊层(Solder Mask)，其由例如聚酰亚胺(Polyimide,PI)所制成。
参考图31，显示本发明封装基板的制造方法的另一实施例的示意图。提供一载体80，该载体80具有一上表面801、一下表面802、一上金属箔803及一下金属箔804，其中该上金属箔803位于该上表面801，该下金属箔804位于该下表面802。接着，形成该下电路层84于该上金属箔803及该下金属箔804上。该下电路层84的二个部分可以同时形成。接着，进行积层(Built-up)工艺，以依序形成该第一介电层81、该第一电路层85、这些第一内连接金属851、该第二介电层82、该第二电路层86、这些第二内连接金属861、该第三介电层83、该第三电路层87及这些第三内连接金属871于该载体80的二侧，以在该载体80的二侧形成二个封装基板。
接着，形成一光阻图案46于该第三电路层87上。该光阻图案46具有数个开口461以显露部分该第三电路层87。接着，施加一金属，例如铜，于该光阻图案46的这些开口461中以形成这些柱体88。这些柱体88可利用例如电镀或其他工艺所形成。接着，平坦化这些柱体88及该光阻图案46，使得每一柱体88具有一顶面881，且这些柱体88的这些顶面881与该上光阻图案46的上表面462大致上共平面。在本实施例中，此平坦化步骤可利用研磨所达成，其使用例如陶瓷砂轮或钻石砂轮。接着，该二个封装基板从该载体80卸下。
接着，移除该光阻图案46，且形成该上保护层89于该第三电路层87上以围绕这些柱体88，且该上保护层89具有至少一开口891以显露部分该第三电路层87。该上保护层89可利用例如涂布(Coating)所形成。这些柱体88位于同一开口891中。因此，制得如图30所示的该封装基板1m。
参考图32，显示本发明封装基板的另一实施例的示意图。该封装基板1n包括一第一介电层91、一第二介电层92、一第三介电层93、一下电路层94、一第一电路层95、一第二电路层96、一第三电路层97、数个第一内连接金属941、数个第二内连接金属951、数个第三内连接金属961、数个柱体98、一上保护层99及一下保护层991。虽然该基板1n例示为具有四层电路层，在其他实施例中，该基板1n可能具有仅有一层、二层、三层或五层或更多层电路层。
该第一介电层91的材质可以和图30的该第一介电层81相同，且该第一介电层91具有数个开口911。该下电路层94位于该第一介电层91的下表面，且对应这些开口911。该下保护层991位于该下电路层94上，且显露部分该下电路层94。在本实施例中，该下保护层991为防焊层(Solder Mask)，例如聚酰亚胺(Polyimide,PI)。该下电路层94的显露的部分可做为球垫(Ball Land)，例如一球栅阵列端点(Ball Grid Array Terminal)，以供一球栅阵列(Ball Grid Array)焊球形成于其上。
该第二介电层92位于该第一介电层91上，且具有数个开口921。该第二介电层92的材质与该第一介电层91的材质相同或不同。该第一电路层95位于该第二介电层92的下表面上。这些第一内连接金属941位于该第一介电层91的这些开口911中，且物理接触且电性连接该下电路层94及该第一电路层95。
该第三介电层93位于该第二介电层92上，且具有数个开口931。该第三介电层93的材质与该第一介电层91的材质相同或不同。该第二电路层96位于该第三介电层93的下表面上。这些第二内连接金属951位于该第二介电层92的这些开口921中，且物理接触且电性连接该第一电路层95及该第二电路层96。
该第三电路层97嵌于该第三介电层93，且显露于该第三介电层93的上表面。在本实施例中，该第三电路层97的上表面与该第三介电层93的上表面为共平面。在本实施例中，该第三电路层97为最上层电路层。这些第三内连接金属961位于该第三介电层93的这些开口931中，且物理接触且电性连接该第二电路层96及该第三电路层97。
这些柱体98位于该第三电路层97上，且电性连接至该第二电路层96及该第一电路层95。每一柱体98具有大致上圆柱的外形或大致上圆筒的外形。每一这些柱体98具有一顶面981，用以形成外部电性连接(例如：连接至一半导体管芯上的另一电性连接)，且这些柱体98的这些顶面981为平面且大致上共平面。每一这些柱体98的底部可具有一薄金属层9041以接触该第三电路层97。然而，该薄金属层9041可以省略。
该上保护层99位于该第三电路层97上，且具有至少一开口992以显露部分该第三电路层97。这些柱体98位于单一开口992中。在本实施例中，该上保护层99可以为防焊层(Solder Mask)，其由例如聚酰亚胺(Polyimide,PI)所制成。
参考图33至38，显示本发明封装基板的制造方法的另一实施例的示意图。参考图33，提供一载体90，该载体90具有一上表面901、一下表面902、一上金属箔903及一下金属箔904，其中该上金属箔903位于该上表面901，该下金属箔904位于该下表面902。接着，形成该第三电路层97于该上金属箔903及该下金属箔904上。该第三电路层97的二个部分可以同时形成。接着，进行积层(Built-up)工艺，以依序形成该第三介电层93、该第二电路层96、这些第三内连接金属961、该第二介电层92、该第一电路层95、这些第二内连接金属951、该第一介电层91、该下电路层94、这些第一内连接金属941及该下保护层991于该载体90的二侧，以在该载体90的二侧形成二个封装基板。
参考图34，从该载体90卸下该二个封装基板。部分该上金属箔903及该下金属箔904可能残留在该第三电路层97，以形成薄金属层9031,9041在该第三电路层97上。这些薄金属层9031,9041可以省略。
参考图35，形成一上光阻图案46于该薄金属层9041或该第三电路层97上，且形成一下光阻图案48于该下电路层94及该下保护层991。该上光阻图案46具有数个开口461以显露部分该薄金属层9041或该第三电路层97。
参考图36，施加一金属，例如铜，于该光阻图案46的这些开口461中以形成这些柱体98。这些柱体98可利用例如电镀或其他工艺所形成。参考图37，平坦化这些柱体98及该光阻图案46，使得每一这些柱体98具有一顶面981，且这些柱体98的这些顶面981与该上光阻图案46的上表面462大致上共平面。在本实施例中，此平坦化步骤可利用研磨所达成，其使用例如陶瓷砂轮50或钻石砂轮。
参考图38，移除该光阻图案46及该下光阻图案48。接着，移除该薄金属层9041未被这些柱体98所覆盖的部分。接着，以涂布方式形成该上保护层99于该第三电路层97上以围绕这些柱体98，且该上保护层99具有至少一开口992以显露部分该第三电路层97。这些柱体98位于同一开口992中。因此，制得如图32所示的该封装基板1n。
惟上述实施例仅为说明本发明的原理及其功效，而非用以限制本发明。因此，习于此技术的人士对上述实施例进行修改及变化仍不脱本发明的精神。本发明的权利范围应如权利要求书所列。

Claims (19)

1.一种半导体封装，包括：
封装基板，包括：
介电层；
第一电路层，位于所述介电层上或所述介电层内；及
数个柱体，位于所述第一电路层上，其中每一所述柱体具有在所述柱体的顶端的凹陷部；
晶粒；及
数个焊球，位于所述晶粒上，其中每一所述焊球被结合至每一所述柱体，每一所述焊球填入所述凹陷部中且延伸至所述柱体的侧壁；
位于所述第一电路层上的保护层，所述保护层具有开口以显露所述第一电路层的一部分及所述柱体。
2.如权利要求1的半导体封装，还包括围绕所述柱体的绝缘材料。
3.如权利要求1的半导体封装，其特征在于，所述第一电路层嵌于所述介电层。
4.如权利要求1的半导体封装，其特征在于，每一所述柱体具有用以形成外部电性连接的顶面，且所述柱体的所述顶面的共平面性为±3μm。
5.如权利要求1的半导体封装，其特征在于，所述凹陷部位于所述柱体的所述顶端的外缘，且所述凹陷部的剖面具有凹型弧面轮廓。
6.如权利要求1的半导体封装，其特征在于，所述柱体的所述顶端的宽度小于所述柱体的底端的宽度。
7.一种半导体封装，包括：
介电层；
第一电路层，位于所述介电层上或所述介电层内；
数个柱体，位于所述第一电路层上，其中每一所述柱体具有在所述柱体的顶端的凹陷部；
绝缘材料，围绕所述柱体；
晶粒，以数个焊球附接至所述柱体，每一所述焊球填入每一所述柱体的所述凹陷部中且延伸至所述柱体的侧壁；及
封装材料，包覆所述晶粒；
位于所述第一电路层上的保护层，所述保护层具有开口以显露所述第一电路层的一部分及所述柱体。
8.如权利要求7的半导体封裝，其特征在于，所述绝缘材料是底胶。
9.如权利要求7的半导体封裝，其特征在于，所述第一电路层嵌于所述介电层。
10.如权利要求7的半导体封裝，其特征在于，每一所述柱体具有用以形成外部电性连接的顶面，且所述柱体的所述顶面的共平面性为±3μm。
11.如权利要求7的半导体封裝，其特征在于，所述柱体从所述第一电路层延伸超过所述保护层。
12.如权利要求7的半导体封裝，其特征在于，所述凹陷部位于所述柱体的所述顶端的外缘，且所述凹陷部的剖面具有凹型弧面轮廓。
13.如权利要求7的半导体封裝，其特征在于，所述柱体的所述顶端的宽度小于所述柱体的底端的宽度。
14.一种封装基板的制造方法，包括以下步骤：
(a)提供封装基板，其中所述封装基板包括介电层及位于所述介电层上或所述介电层内的第一电路层；
(b)形成光阻图案相邻于所述第一电路层，其中所述光阻图案具有数个开口；
(c)形成数个柱体于所述光阻图案的所述开口中；
(d)移除每一所述柱体的顶端的一部分，使得每一所述柱体在所述柱体的顶端具有凹陷部；及
(e)移除所述光阻图案以显露所述柱体的侧壁；
(f)形成保护层于所述第一电路层上，所述保护层具有开口以显露所述第一电路层的一部分及所述柱体。
15.如权利要求14的制造方法，其特征在于，在步骤(c)之后，所述制造方法更包括以下步骤：
(c1)在每一所述柱体的顶面的中心部分形成顶光阻层。
16.如权利要求15的制造方法，其特征在于，在步骤(d)中，所述凹陷部形成于所述柱体的所述顶端的外缘，且所述凹陷部的剖面具有凹型弧面轮廓。
17.如权利要求15的制造方法，其特征在于，在步骤(d)中，形成空间于所述柱体的所述顶端的侧表面与所述光阻图案的所述开口的侧壁之间。
18.如权利要求14的制造方法，其特征在于，在步骤(c)中，所述柱体从所述光阻图案的顶面突出且覆盖所述光阻图案的顶面的一部分。
19.如权利要求18的制造方法，其特征在于，在步骤(d)中，借由蚀刻移除所述柱体的覆盖所述光阻图案的顶面的部分。
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