JPS54128669A - Flip chip element - Google Patents

Flip chip element

Info

Publication number
JPS54128669A
JPS54128669A JP3646978A JP3646978A JPS54128669A JP S54128669 A JPS54128669 A JP S54128669A JP 3646978 A JP3646978 A JP 3646978A JP 3646978 A JP3646978 A JP 3646978A JP S54128669 A JPS54128669 A JP S54128669A
Authority
JP
Japan
Prior art keywords
thick
bump
resin
increased
insulation layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3646978A
Inventor
Kazunori Kawamoto
Original Assignee
Nippon Denso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Denso Co Ltd filed Critical Nippon Denso Co Ltd
Priority to JP3646978A priority Critical patent/JPS54128669A/en
Publication of JPS54128669A publication Critical patent/JPS54128669A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361Physical or chemical etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask

Abstract

PURPOSE: To absorb the stress caused between the metal bump and the insulation layer with plastic nature of resin, by using resin for the insulation layer under the bump.
CONSTITUTION: On the SiO2 13 opened at the diffusion layer 121, the Al wiring 14 is formed. On it, the PIQ 15 about 3μ thick is selectively coated and Cr 16 0.3μ thick and Cu 17 0.5μ thick are evaporated. Further, it is covered with the resist mask 19 2μ thick to form the copper bump 18 40μ thick with plating. Further, after removing the films 16,17 sequentially with etching, it is processed at 410°C for 30 minutes under N2+H2 gas, the attaching strength of the bump section is increased to reduce the electric resistance. Succeedingly, after solder dip, it is sectioned into chips. With this method, the bonding of the bump is strong, the plasticity of resin is increased with the temperature rise to mitigate the stress, allowing to avoid the cracks and block the local alloying of metal due to strain.
COPYRIGHT: (C)1979,JPO&Japio
JP3646978A 1978-03-29 1978-03-29 Flip chip element Pending JPS54128669A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3646978A JPS54128669A (en) 1978-03-29 1978-03-29 Flip chip element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3646978A JPS54128669A (en) 1978-03-29 1978-03-29 Flip chip element

Publications (1)

Publication Number Publication Date
JPS54128669A true JPS54128669A (en) 1979-10-05

Family

ID=12470665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3646978A Pending JPS54128669A (en) 1978-03-29 1978-03-29 Flip chip element

Country Status (1)

Country Link
JP (1) JPS54128669A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56158456A (en) * 1980-05-12 1981-12-07 Hitachi Ltd Semiconductor element
US5162257A (en) * 1991-09-13 1992-11-10 Mcnc Solder bump fabrication method
US7427557B2 (en) 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
US8334594B2 (en) 2009-10-14 2012-12-18 Advanced Semiconductor Engineering, Inc. Chip having a metal pillar structure
US8552553B2 (en) 2009-10-14 2013-10-08 Advanced Semiconductor Engineering, Inc. Semiconductor device
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
US8698307B2 (en) 2010-09-27 2014-04-15 Advanced Semiconductor Engineering, Inc. Semiconductor package with integrated metal pillars and manufacturing methods thereof
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56158456A (en) * 1980-05-12 1981-12-07 Hitachi Ltd Semiconductor element
JPS6257101B2 (en) * 1980-05-12 1987-11-30 Hitachi Ltd
US5162257A (en) * 1991-09-13 1992-11-10 Mcnc Solder bump fabrication method
US5293006A (en) * 1991-09-13 1994-03-08 Mcnc Solder bump including circular lip
US7427557B2 (en) 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
US7834454B2 (en) 2004-03-10 2010-11-16 Unitive International Limited Electronic structures including barrier layers defining lips
US8487432B2 (en) 2004-03-10 2013-07-16 Amkor Technology, Inc. Electronic structures including barrier layers and/or oxidation barriers defining lips and related methods
US8334594B2 (en) 2009-10-14 2012-12-18 Advanced Semiconductor Engineering, Inc. Chip having a metal pillar structure
US8552553B2 (en) 2009-10-14 2013-10-08 Advanced Semiconductor Engineering, Inc. Semiconductor device
US8698307B2 (en) 2010-09-27 2014-04-15 Advanced Semiconductor Engineering, Inc. Semiconductor package with integrated metal pillars and manufacturing methods thereof
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US9224707B2 (en) 2012-07-05 2015-12-29 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US9437532B2 (en) 2012-07-05 2016-09-06 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods

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