TWI445140B - 半導體封裝基板 - Google Patents

半導體封裝基板 Download PDF

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Publication number
TWI445140B
TWI445140B TW100102608A TW100102608A TWI445140B TW I445140 B TWI445140 B TW I445140B TW 100102608 A TW100102608 A TW 100102608A TW 100102608 A TW100102608 A TW 100102608A TW I445140 B TWI445140 B TW I445140B
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TW
Taiwan
Prior art keywords
substrate
plug
layer
package substrate
plugs
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TW100102608A
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English (en)
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TW201135884A (en
Inventor
Chen Hua Yu
Hung Pin Chang
Yung Chi Lin
Chia Lin Yu
Jui Pin Hung
Chien Ling Hwang
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Taiwan Semiconductor Mfg
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Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW201135884A publication Critical patent/TW201135884A/zh
Application granted granted Critical
Publication of TWI445140B publication Critical patent/TWI445140B/zh

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description

半導體封裝基板
本發明係關於一種半導體封裝基板，更特別關於其穿透矽插塞之構形、排列、及形狀。
縮減外觀尺寸及改良電性效能為先進半導體封裝的趨勢，可讓產業及消費者使用更快、更便宜、且更小的產品。經由穿透矽通孔(TSV)或更精確的穿透矽插塞(TSP)，可提高先進半導體封裝之積體度及縮減其外觀尺寸。如名所示，半導體元件其正面及背面的電性連接可垂直組裝封裝中的多重晶片，而非習知的單一晶片。如此一來，越來越多的半導體元件可整合至越來越小的外觀尺寸中。此外，不同種類的半導體晶片亦可整合至單一封裝以形成所謂的系統級封裝(SIP)。不論如何，減少印刷電路板中多重封裝的針腳數目亦可降低最終產品的成本。由於單一基板連線可用以連接多重晶片，採用TSV作為晶片之間的內連線可大幅減少晶片與基板之間的電性連接數目，並簡化組裝製程與改善良率。此外，穿透矽通孔具有絕佳的散熱效果。
由於發光二極體(LED)具有高輸出光效率，近年來以LED作為發光元件的情況顯著提升。然而電能在通過LED的PN接面時產生的熱能無法轉換為所需的光能。若無法移除這些熱能，高溫下操作LED不只會降低其效率，還會使LED的可信度降低，甚至危害使用者安全。綜上所述，LED的熱管理非常重要。
本發明一實施例提供一種半導體封裝基板，具有穿透矽插塞以散逸被封裝的半導體晶片產生的熱，包含基板，具有穿透矽插塞於半導體封裝基板上，其中穿透矽插塞自半導體封裝基板之第一表面延伸至相反側之第二表面，其中穿透矽插塞之截面形狀為雙面梳，且其中穿透矽插塞提供半導體晶片多個散熱途徑。
本發明又一實施例提供一種半導體封裝基板，具有穿透矽插塞以散逸被封裝的半導體晶片產生的熱，包含基板，具有穿透矽插塞於半導體封裝基板上，其中穿透矽插塞自半導體封裝基板之第一表面延伸至相反側之第二表面，且其中穿透矽插塞之負載比大於或等於約50%。
可以理解的是，下述內容提供多種實施例或實例以說明本發明的多種特徵。為了簡化說明，將採用特定的實施例、單元、及組合方式說明。然而這些特例僅用以說明而非限制本發明。此外為了簡化說明，本發明在不同圖示中採用相同符號標示不同實施例的類似元件，但上述重複的符號並不代表不同實施例中的元件具有相同的對應關係。
第1A-18圖係本發明某些實施例之中間製程的剖視圖。如第1A圖所示，某些實施例之第一基板100上具有光阻圖案。第一基板100可為基體矽、掺雜或未掺雜之基板、或絕緣層上半導體(SOI)基板之主動層。一般的SOI基板含有半導體材料層如矽形成於絕緣層上。上述絕緣層可為氧化埋層(BOX)或氧化矽層。絕緣層可形成於基板(如一般矽基板或玻璃基板)上。此外，第一基板100亦可為其他基板如多層結構或組成漸變式基板。
在下述例中，第一基板100之組成為矽材料140，其上沉積有介電層101。接著在介電層101上沉積光阻層102，並圖案化光阻層102以形成開口作為後續之穿透矽通孔。介電層101在後續穿透矽通孔之蝕刻製程中，可作為保護基板表面的犧牲層。
如第1B圖所示之某些實施例中，在沉積與圖案化光阻層102前，第一基板100已具有電路190形成其上。在第1B圖中，電路190已形成於第一基板100上。電路190可為任合特定用途的電路。在一實施例中，電路190含有電子元件形成於第一基板100上，以及一或多層介電層形成於電子元件上。在介電層之間可形成金屬層以傳遞電子元件之間的電子訊號。電子元件可形成於一或多層的介電層上或介電層中。
舉例來說，電路190可具有多種n型金氧半(NMOS)及/或p型金氧半(PMOS)元件如電晶體、電容、電阻、二極體、光二極體、熔絲、或類似物，彼此以內連線相接以形成具有一或多種功能之結構如記憶結構、處理結構、感測器、放大器、功率分佈器、輸入/輸出電路、或類似物。本技藝人士應理解上述實例僅用以舉例及進一步說明本發明，並非用以侷限本發明。本發明亦可採用其他電路。
同樣在第1B圖中，接著形成蝕刻停止層191與層間介電層(ILD) 192。在某些實施例中，蝕刻停止層191之組成較佳為介電材料，其蝕刻選擇率最好與鄰接的層狀結構(比如下方的第一基板100與上方的層間介電層192)不同。在一實施例中，蝕刻停止層191之組成可為氮化矽、碳氮化矽、碳氧化矽、氮化碳、或類似物。蝕刻停止層191之沉積方法可為化學氣相沉積法(CVD)、或電漿增強式CVD(PECVD)。
層間介電層(ILD) 192之組成可為低介電常數材料如磷掺雜矽酸鹽玻璃(PSG)、硼磷掺雜矽酸鹽玻璃(BPSG)、氟化矽酸鹽玻璃(FSG)、碳氧化矽、旋塗玻璃、旋塗高分子、矽碳材料、上述之化合物、上述之複合物、上述之組合、或類似物。層間介電層192之形成方法可為本技藝已知的方法如旋轉塗佈法、CVD、或PECVD。必需注意的是，蝕刻停止層191與層間介電層192可為多層的介電層結構，且在相鄰的介電層之間可視情況夾設或不夾設額外的蝕刻停止層。
接著形成接點195穿過層間介電層192，以提供電性連接至電路190。接點195之形成方法可為微影製程如沉積並圖案化光阻材料於層間介電層192上，層間介電層192露出的部份將用以形成接點195。接著進行蝕刻製程如非等向乾蝕刻以形成開口於層間介電層192中。可將擴散阻障層及/或黏著層(未圖示)襯墊於開口中，再將導電材料填入開口。擴散阻障層較佳為一或多層的氮化鉭、鉭、氮化鈦、鈦、鈷鎢合金、或類似物，而導電材料可為銅、鎢、鋁、銀、或上述之組合、或類似物。至此形成第1B圖所示之接點195。
如第2圖所示之一實施例中，第一基板100被蝕刻出開口。雖然第2圖並未顯示第1B圖中的電路190、接點195、蝕刻停止層191、與層間介電層192，上述結構仍存在於第2圖及後續圖示。在一實施例中，時間控制的蝕刻製程如非等向乾蝕刻，可蝕刻第一基板100直到開口110所需的深度。可以理解的是，蝕刻製程可為單一蝕刻製程或多重蝕刻製程，且蝕刻製程可為乾蝕刻或濕蝕刻。
在某些實施例中，開口110的深度可介於約20μm至約200μm之間。在某些實施例中，開口寬度可介於約5μm至約100μm之間。在某些實施例中，開口為穿透矽通孔(或溝槽)。蝕刻開口的深度完全取決於光阻層102本身的物理限制。在此實施例中，先蝕刻介電層101作為圖案化遮罩層。介電層101之組成可為任何介電材料如氧化矽、氮化矽、或上述之組合。在一實例中，介電層101為PECVD沉積之氧化矽，此沉積反應之矽來源為四乙氧矽烷(TEOS)。此外，介電層101亦可為矽烷氧化膜。在某些實施例中，TEOS氧化層之厚度介於約500至約10000之間。介電層101不限於PECVD沉積的方法，亦可為旋塗介電層(SOD)或旋塗玻璃(SOG)。介電層101之沉積法(或成長法)亦可為熱製程，比如熱成長的氧化矽或熱CVD沉積之氧化膜。
在蝕刻基板形成穿透矽通孔後，將移除光阻層與犧牲介電層101。在形成開口如開口101後，可將開口填入材料。如第3圖所示之某些實施例中，先以絕緣層103與阻障層/銅晶種層104襯墊第一基板100。絕緣層103之組成為介電材料如氧化物、氮化物、或上述之組合。在一實例中，絕緣層103為PECVD沉積之氧化矽，其矽來源為矽烷或TEOS。在某些實施例中，絕緣層103之厚度介於約500至約15000之間。絕緣層103之沉積法(或成長法)亦可為熱製程，比如熱成長的氧化物或熱CVD沉積之氧化膜。在其他實施例中，絕緣層103可為掺雜膜，其掺質可為磷、或磷與硼。掺雜磷之矽玻璃(PSG)或掺雜硼磷之矽玻璃(BPSG)中的磷可吸收銅，而上述組成可填入此例之穿透矽通孔(或溝槽)的開口中。銅會擴散至矽基板中。即使穿透矽通孔已襯有後述之阻障層，阻障層對通孔底部附近側壁(如角落170)之覆蓋率可能不足。採用PSG或BPSG作為絕緣層103可進一步保護基板不受銅擴散影響。
絕緣層103之熱阻性大於矽。第1表係不同厚度之氧化物介電層與不同厚度的矽材質之第一基板100，搭配後之熱阻性模擬比較。
由第1表可知，氧化物將大幅增加熱阻性。如此一來，封裝中的介電層厚度越小越好。
在沉積絕緣層103後，將沉積阻障/晶種層104。阻障層/銅晶種層104包含至少兩層，分別為阻障層與銅晶種層。阻障層之材料可為一或多種銅阻障材料如鉭、氮化鉭、鈦、氮化鈦、鈷鎢合金、或類似物。阻障層可避免銅擴散至矽材質的第一基板100中。阻障層之沉積方法可為物理氣相沉積法(PVD)、CVD、原子層沉積(ALD)、或其他方法。在沉積阻障層後，可沉積銅晶種層。同樣地，銅晶種層之沉積方法可為PVD、CVD、ALD、或其他方法。在某些實施例中，阻障層/銅晶種層104為氮化鉭/鉭之阻障層與銅晶種層。在此實施例中，阻障層由氮化鉭層與鉭層組成。在某些實施例中，氮化鉭、鉭、與銅晶種層之沉積法均為PVD，且上述沉積均在單一PVD腔室中進行，差別僅在於靶材與濺鍍氣體。在某些實施例中，氮化鉭與鉭之厚度各自介於約100至約2000之間，而銅晶種層之厚度介於約1000至約15000之間。
在沉積阻障層/銅晶種層104後，圖案化基板以定義進行銅電鍍的區域。如第4圖所示之某些實施例中，在第一基板100上形成圖案化的光阻層105。在某些實施例中，圖案化的光阻層105之組成為一般光阻，可為液態並以旋塗製程沉積於基板上。在另一實施例中，圖案化的光阻層105為乾膜光阻(DFR)，其圖案化的方法亦可為微影製程(包含曝光)。DFR可為正光阻或負光阻。DFR係用以形成圖案，以利電路板進行後續電鍍。DFR可為日本TOK有限公司所製之MP112。當DFR壓合至第一基板100(或其上的阻障層/銅晶種層104)後，將曝光DFR以定義基板表面稍後進行銅電鍍的區域。與濕式的旋塗光阻相較，乾膜光阻的好處在於其僅壓合至基板表面。相反地，濕式旋塗光阻會流入開口如開口110中。由於穿透基板通孔(或溝槽)具有相當深度(如前所述之約20μm至約200μm之間)，卡在開口中的光阻將難以完全移除。這將使銅無法適當地電鍍至開口之側壁及底部表面上。
如第5圖所示之某些實施例中，在銅膜106電鍍至第一基板100之表面上後，可自基板表面剝除DFR。上述電鍍製程，可為一般用以形成半導體元件之金屬內連線的銅電鍍製程或無電銅電鍍製程。在某些實施例中，銅膜106之厚度小於約30μm。在其他實施例中，銅膜106之厚度小於約20μm。在又一實施例中，銅膜106之厚度小於約10μm。太厚的銅膜會導致基板翹曲。在某些實施例中，銅膜106僅填入開口(或穿透基板通孔)如第4圖所示之開口110中。在另一實施例中，銅膜106不只沉積於開口(穿透基板通孔)中，亦提供基板上封裝元件之定位墊如印刷電路板(PCB)，或用以容置半導體晶片。
在某些實施例中，銅膜106之厚度介於約10μm至約30μm之間。在電鍍形成銅膜106後，將移除圖案化的光阻層105。不論是濕式旋塗光阻或乾膜光阻，其移除方法均可為灰化法，後續輔以濕式清潔製程以完全移除基板表面上的雜質。
如第6圖所示之某些實施例中，在銅電鍍及光阻移除製程後，將移除先前被光阻覆蓋而未進行電鍍之阻障層/銅晶種層104。在上述製程後，將基板之正面黏結至第7圖所示之第二基板108。第二基板係虛置基板，其組成可為介電材料如玻璃。在其他實施例中，第二基板108之組成可為導電材料如金屬。如第7圖所示之某些實施例中，以膠層107黏結第一基板100與第二基板108。膠層107之組成特性為易於移除的材料，這在不需要虛置的第二基板108時特別有用。在某些實施例中，膠層107之組成為環氧高分子。先將液態的膠層107施加於第一基板100上，再將第二基板108置於膠層107上，接著以自然風乾或低溫加熱的方式處理膠層。在乾燥及加熱(或硬化)製程後，第一基板100將緊密貼合虛置的第二基板108。
接著研磨第一基板100之背面以移除多餘的矽層，直到露出穿透矽通孔120。在某些實施例中，在背面研磨製程後接著進行化學機械研磨(CMP)，以平坦化研磨後的基板表面。如第8圖所示之某些實施例中，移除第一基板100背面之矽層以露出穿透矽通孔120。在某些實施例中，移除矽的製程為研磨製程。在封裝製程中，一般可用研磨輪移除矽基板上多餘的矽層。上述研磨製程將進行到完全移除穿透矽通孔120底部之絕緣層103與阻障層/銅晶種層104為止。
薄化矽基板的厚度有助於改善其散熱效率。第2表係不同厚度的矽基板之熱阻性模擬比較。
由第2表之資料可知，當基板薄化至100μm時可大幅降低其熱阻性。除了穿透矽通孔(或溝槽)中的銅以外，薄化矽基板亦可增加散熱能力。
如第9圖所示之某些實施例中，在研磨基板背面後，沉積介電層150於第一基板100之背面上。與絕緣層103類似，介電層150之組成可為氧化物、氮化物、或上述之組合。在一實施例中，介電層150為PECVD沉積之氧化矽，其矽來源為矽烷。在某些實施例中，介電層150之厚度介於約5000至約20000之間。在某些實施例中，介電層150為掺雜膜，且掺質為磷、或磷與硼。如前所述，PSG或BPSG中的磷可吸收銅。
如第10圖所示之某些實施例中，在沉積介電層150後再沉積與圖案化光阻層151。光阻層150可為旋塗之濕式光阻或乾膜光阻。光阻層151之圖案開口對應後續穿透基板通孔之形成區域。圖案化光阻層所露出的介電層150將被蝕刻移除。一般應用於半導體晶片製程之介電層蝕刻可用以移除介電層150。蝕刻製程可為乾式或濕式。如第11圖所示之某些實施例中，第一基板100與第二基板之開口區域中的介電層150被蝕刻。
如第12圖所示之某些實施例中，接著沉積阻障層/銅晶種層152。阻障層/銅晶種層指的是阻障層與銅晶種層的複合層。阻障層可保護矽基板不受銅擴散的影響。如前所述，阻障層之組成可為鉭、氮化鉭、鈦、氮化鈦、鈷鎢合金、或上述之組合。在某些實施例中，阻障層之組成為厚度介於約500至約5000之鈦層。薄銅晶種層之沉積厚度介於約1000至約10000之間。用以沉積阻障層與銅晶種層之方法已陳述於上，在此不贅述。
如第13圖所示之某些實施例中，在沉積阻障層/銅晶種層152後，沉積與圖案化光阻層151以定義後續進行銅電鍍的區域。如前所述，光阻層可為旋塗之濕式光阻或乾膜光阻。在圖案化光阻層後，先電鍍銅層154於基板未被光阻層覆蓋的露出區域。如前所述，銅層154之電鍍製程可為電化學電鍍製程(ECP)或無電銅電鍍製程。在某些實施例中，銅層154之厚度小於30μm以避免前述的基板翹曲問題。在某些實施例中，銅層154之厚度介於約10μm至約20μm之間。之後沉積擴散阻障層155於銅層154上。在下述段落中，擴散阻障層155最後會容納焊料層與一或多個積體電路(IC)晶片。擴散阻障層155可避免銅層154之銅擴散至位於TSV基板上的IC晶片。在某些實施例中，擴散阻障層155之沉積方法亦可為電鍍如ECP或無電電鍍法。在某些實施例中，擴散阻障層155之組成為化學鍍鎳浸金層(ENIG)。然而，擴散阻障層亦可採用任何合適之擴散阻障材料。
在沉積擴散阻障層155後，可移除光阻層153與其下的阻障層/銅晶種層152。如第14圖所示之某些實施例中，第一基板100不具有光阻層153與其下之阻障層/銅晶種層152。此時第一基板100已準備好容納半導體晶片。不同的半導體晶片可嵌置於第一基板100上，其嵌置流程僅有些許差異。在某些實施例中，半導體晶片為發光二極體或類似的發光元件。
在上述步驟後，可採用共熔接合層157將半導體晶片156固定至擴散阻障層155。在某些實施例中，共熔接合層157之組成為焊料。如第15圖所示之實施例中，半導體晶片156為發光二極體(LED)。LED晶片係置於p型接點159上，且LED晶片經由焊線158電性連接至n型接點160。焊線接合步驟可用以連接LED的半導體晶片156至n型接點160。如第15圖所示之某些實施例中，置於第一基板100上的LED的半導體晶片156，經由共熔接合層157接合至第一基板100，且經由焊線158接合至n型接點。由於擴散阻障層155與p型接點159之表面等高，LED的晶片156可直接位於第一基板100上而不需導電凸塊。
第13-15圖所示之銅層154可提供頂部之LED的半導體晶片156電性連接與熱接點。銅層154亦稱之為金屬墊，且不必由銅組成。在某些實施例中，金屬墊之組成為焊料。金屬墊之沉積方法可為前述之電鍍製程，或在圖案化光阻層153後施加焊料膏於基板表面上。焊料膏可填入光阻層153之開口中，且殘留於光阻層153上的焊料膏非常少，不太影響後續光阻層的移除製程。在某些實施例中，若採用焊料作為金屬墊，則不需阻障層/銅晶種層152中的銅晶種層部份。若以電鍍法形成焊料層，則需要焊料晶種層或非焊料材料組成的晶種層。然而，採用焊料膏形成於基板上可省略晶種層。
如第15圖所示，部份的穿透矽通孔120與銅層(或金屬墊)154延伸超過LED的半導體晶片156之邊緣。封裝基板(如第一基板100)其電性及/或熱連接(如穿透基板通孔120與銅層154)超過半導體晶片(如LED)156邊界之延伸部份可稱作扇出封裝，這可提供再佈線與散熱的額外區域。銅層(或金屬墊)154超出LED的半導體晶片156邊緣之延伸部份可提供水平方向的散熱通路區域。穿透矽通孔120超出LED的半導體晶片156邊緣之延伸部份可提供額外的穿透矽通孔120空間，這可提供垂直方向的散熱通路區域。上述水平與垂直方向的通路區域均影響並改善散熱效率。
如第16圖所示之某些實施例中，在LED的半導體晶片156接合至基板及焊線接合LED的半導體晶片156後，封裝LED的半導體晶片156。在某些實施例中，可沉積螢光膜161於LED的半導體晶片156上。LED晶片可設計為發紅光、藍光、或綠光，且通常搭配組合以發出白光。螢光膜可用以發出白光。在某些實施例中，螢光膜161係塗佈於LED的半導體晶片156上。不過螢光膜161並非必要元件，可視情況決定是否採用。在某些實施例中，可在發出不同顏色(或光波波長)的LED上塗佈不同的螢光膜。在某些實施例中，可省略螢光膜如螢光膜161。
接著可沉積成型材料162以包圍LED的半導體晶片156、p型接點159、與n型接點160。在某些實施例中，成型材料之組成為透明的環氧樹脂。透明的成型材料較適用於LED。若半導體晶片156不是LED，則成型材料不一定非得為透明組成不可。
如第17圖所示之某些實施例中，成型之LED的半導體晶片156係置於膠帶163上。膠帶(有時稱作藍帶)163在準備分離(或脫離)第二基板108時，可穩定支撐LED的半導體晶片156之成型材料162與第一基板100。在化學與機械移除第二基板108與膠層107後，將切割第一基板100以物理分隔第一基板100上的晶粒。上述每一晶粒均具有LED的半導體晶片156、n型接點160、與p型接點159。如第18圖所示之某些實施例中，移除虛置的第二基板108與膠層107後，膠帶163支撐住單一封裝晶片180。之後可進行其他製程，比如將封裝晶片180置於印刷電路板上、移除膠帶163、或類似製程。
上述流程顯示如何將半導體晶片封裝至具有穿透矽通孔之基板以提高散熱效果。此外，由於上述封裝晶片之矽基板厚度已薄化至約20μm至約200μm之間，因此散熱效果超過其他穿透矽通孔技術。
上述之晶片封裝方法與結構可用於非LED的半導體晶片。當這些晶片封裝方法與結構用於非LED的晶片時，製程會有些許不同，特別是在採用LED的製程步驟之後(比如第15圖以後的製程)。
半導體晶片下的穿透矽通孔可具有多種形狀與尺寸。舉例來說，穿透矽通孔之形狀可為圓柱。第19A圖為本發明某些實施例中，穿透矽插塞(或穿透矽通孔) 401之上視圖。穿透矽插塞401為圓柱，其直徑為D1。如前所述，直徑D1介於約5μm至約100μm之間。當小型晶片之上表面面積與穿透矽插塞401之表面積類似時，可採用單一穿透矽插塞(如穿透矽插塞401)。然而，半導體晶片其上表面積通常遠大於單一穿透矽插塞之表面積。舉例來說，LED晶片之表面積可為0.6×0.6mm2 、1×1mm2 、或更大面積。上述數字僅用以舉例。此外，半導體晶片之上表面並不必然為方形，亦可為矩形或其他形狀。
穿透矽插塞之長度不應太長(或其截面積不應太大)，以避免孔洞填充時間過長或其他問題。如第19B圖所示之實施例中，多重穿透矽插塞(或穿透矽通孔) 402、403、404、與405可提供位於其上的半導體晶片散熱途徑。雖然第19B圖僅顯示四個穿透矽插塞，但上述結構中的矽插塞數目可大於四個或小於四個(比如兩個或三個)。在某些實施例中，第19B圖中的每一穿透矽插塞的直徑D2介於約5μm至約100μm之間。第19B圖中兩個穿透矽插塞之間的最短距離為D3。在某些實施例中，穿透矽插塞之間的距離D3大於或等於穿透矽插塞之直徑D2。穿透矽插塞之間的距離必需大到足以確定彼此之間的電性絕緣與結構強度。如前述流程，基板將進行後續機械製程如研磨背面與視情況添加之CMP，這會施加大量應力於基板上。若穿透矽插塞之間的介電層的機械支撐力不足，基板將會碎裂及/或基板中具有穿透矽插塞之層狀結構會碎裂或剝離。
在某些實施例中，穿透矽插塞(或穿透矽通孔)之構形可為同心環與中心圓柱，如第19C圖所示。同心環之數目可為一或多個。第19C圖顯示一個同心環407環繞一中心圓柱406。在某些實施例中，穿透矽通孔406具有直徑D4，而穿透矽插塞407之寬度D6介於約5μm至約100μm之間。在某些實施例中，穿透矽插塞之間的距離D5大於或等於穿透矽通孔之直徑D4或穿透矽插塞之寬度D6。如前所述，絕緣層需有足夠支撐。
穿透矽插塞並不必然為圓形，亦可為其他形狀如三角形、方形、矩形、卵形、或六角形等等。如第19D圖所示之某些實施例中，顯示多個矩形的穿透矽插塞，比如穿透矽插塞408與409。矩形的穿透矽插塞(或穿透矽溝槽)408與409均具有寬度L1及長度L2，且兩者相隔之間距為L3。在某些實施例中，矩形穿透矽插塞之寬度L1介於約5μm至約100μm之間。在某些實施例中，矩形穿透矽插塞之間距L3大於或等於矩形穿透矽插塞之寬度L1。矩形穿透插塞之數目可為一或多個。
在某些實施例中，穿透矽插塞可為第19E圖所示之圖案。第19E圖顯示穿透矽插塞圖案410具有多個開口(比如開口411)位於其中。第19E圖中的開口411之截面為方形。然而，開口亦可為矩柱、圓柱、或其他形狀的柱狀物。在某些實施例中，開口411之間距L5可小於或等於開口411之寬度L4。
如第20A及20B圖所示之某些實施例中，穿透矽插塞具有兩種其他構形。第20A及20B圖所示之某些實施例中的構形類似，均為雙面梳狀。第20B圖之穿透矽插塞的雙面梳比第20A圖之穿透矽插塞的雙面梳長。在某些實施例中，第20A及20B圖之穿透矽插塞之寬度均為L6，且L6之範圍介於約5μm至約100μm之間。在某些實施例中，第20A及20B圖中的梳齒間距L7、L8、及L9大於或等於穿透矽插塞之寬度L6，且梳齒間距L7、L8、及L9介於約5μm至約100μm之間。第20A圖中的穿透矽插塞結構A1、A2、A3、及A4具有寬度W1及高度H1。在第20A圖中，穿透矽插塞結構A1之寬度加上間距的距離為W1’，其高度加上間距的距離為H1’。在第20B圖中的穿透矽插塞結構B1及B2具有寬度W2及高度H2。在第20B圖中，穿透矽插塞結構B1之寬度加上間距的距離為W2’。穿透矽插塞結構A1其一側的梳齒數目為3，但梳齒可為任何數目如1、2、...、至N。N為整數，可為10或更大數目。穿透矽插塞結構B1其一側的梳齒數目可多到延伸至整個半導體晶片156(如LED)之長度或寬度。上述晶片係位於穿透矽插塞基板如第一基板100上。在某些實施例中，第20A或20B圖之穿透矽插塞結構A1或B1可重複直到蓋滿整個半導體晶片之長度或寬度。在某些實施例中，第20A或20B圖之穿透矽插塞結構A1或B1可重複直到蓋滿整個半導體晶片之長度或寬度，並延伸出半導體晶片之長度或寬度。舉例來說，封裝基板之穿透矽插塞區域大於半導體晶片之區域。穿透矽插塞結構其寬度與高度之設計最好能提供半導體晶片足夠的散熱性。
第20A圖之穿透矽插塞結構A1、A2、A3、及A4，與第20B圖之穿透矽插塞結構B1及B2之圖案設計均可讓穿透矽插塞具有最大截面積。但第20A及20B圖中的穿透矽插塞均非單一大型穿透矽插塞，比如第19A圖所示之穿透矽插塞401。多重圖案可避免製程問題，比如過長的電鍍時間、結構支撐力不足、或其他問題。穿透矽插塞之截面積越大，越能提供較多的熱傳導途徑與區域。如前所述，某些半導體晶片如LED晶片所產生的大量熱能需能有效散熱。若基板具有較大截面積之穿透矽插塞，可提供較多的散熱途徑。負載比可用以定性具有穿透矽插塞之基板其熱傳導途徑量。負載比的定義為傳導面積(比如穿透矽插塞之截面積)除以晶片(置於傳導區上的晶片如LED晶片)的總截面積，如第1式所示。
負載比=傳導面積/晶片總截面積　(第1式)
與具有低負載比之封裝相較，具有高負載比之半導體封裝(或基板)可提供較高散熱率。第20A圖之實施例中，穿透矽插塞之構形具有四個分開的穿透矽插塞結構A1、A2、A3、及A4。第20B圖之實施例中，穿透矽插塞之構形具有兩個分開的穿透矽插塞結構B1及B2。若第20A及20B圖的穿透矽插塞結構之梳狀物具有相同寬度與間距，則第20B圖之穿透矽插塞構形之負載比高於第20A圖之穿透矽插塞構形。與第20B圖之構形相較，第20A圖之構形中的穿透矽插塞結構A1與A3之間(A2與A4之間)具有額外空隙。如此一來，第20A圖之構形的負載比必然小於第20B圖之構形。若第20B圖中穿透矽插塞梳狀物的寬度與間距相同，即L6=L7=L9，則穿透矽插塞之截面積占總截面積的50%或更高。若穿透矽插塞結構延伸出半導體晶片的邊緣(扇出封裝)，其負載比將大於50%。
如第21A圖所示之某些實施例，係半導體晶片450置於封裝基板460頂部上的上視圖。封裝基板460之穿透矽插塞結構延伸出半導體晶片450之寬度與長度。如第21A圖所示，封裝晶片的負載比大於50%。如第21A圖所示之某些實施例中，若半導體晶片450為LED晶片，則穿透矽插塞463為n型接點的一部份。在這種情況下的某些實施例中，位於p型接點上的LED之半導體晶片450將經由焊線462連接至n型接點。
如前所述，金屬層如第15-18圖之銅層154可提供半導體晶片與穿透矽插塞之間的連線。金屬層之延伸區域465超出半導體晶片450的範圍，可提供半導體晶片465水平的散熱途徑。第21B圖係第21A圖中O-O切線之剖視圖。封裝基板460之穿透矽插塞可提供垂直的散熱途徑。
第19D、19E、20A、及20B圖之穿透矽插塞結構均具有垂直的邊角。在基板製程中，圖案化步驟可圓潤化上述結構之邊角。第20B圖之穿透矽插塞結構的邊角可圓潤化如第22圖所示。如第23A圖所示之某些實施例中，將第23A圖中兩個邊角圓潤化之穿透矽插塞結構C1相接，即形成第22圖之邊角圓潤化之穿透矽插塞結構。在某些實施例中，穿透矽插塞結構C1之高度H介於約150μm至約125μm之間。在某些實施例中，穿透矽插塞結構C1之梳齒的寬度與間距均為約25μm。以某些半導體晶片如LED晶片為例，其面積約為0.6×0.6mm2 。藉由將16個穿透矽插塞結構C1以4×4的方式排列，可填滿半導體晶片下的面積。穿透矽插塞結構C1之寬度W為約125μm，而兩個穿透矽插塞結構C1的間距W0為約25μm。第23B圖中的16個穿透矽插塞結構C1填滿封裝基板其0.6×0.6mm2 的面積，用以幫助面積為0.6×0.6mm2 之半導體晶片散熱。在穿透矽插塞結構C1之間的間距W0為約25μm。
如第23C圖所示之某些實施例中，與第23A圖的穿透矽插塞結構C1類似之穿透矽插塞C2，其長度為約300μm且寬度為約250μm。在某些實施例中，穿透矽插塞結構C2之梳齒的寬度與間距均為約50μm。以某些半導體晶片如LED晶片為例，其面積約為0.6×0.6mm2 。藉由將4個穿透矽插塞結構C1以2×2的方式排列，可填滿半導體晶片的面積。第23D圖顯示4個穿透矽插塞結構C2的排列方式。在穿透矽插塞結構C2之間的間距為約50μm。在某些實施例中，每一雙面梳狀物如穿透矽插塞結構C1、C2、與C3之寬度介於約100μm至約300μm之間。在某些實施例中，每一雙面梳狀物如穿透矽插塞結構C1、C2、與C3之長度介於約100μm至約300μm之間。
當半導體晶片的面積增大，可採用額外的穿透矽插塞結構以提供高負載比及高散熱性。在某些實施例中，半導體晶片之尺寸為約1×1mm2 。如第23E圖所示之某些實施例中，排列方式為7×7的穿透矽插塞結構C1可覆蓋大部份晶片下的面積。在其他實施例中，排列方式為4×3的穿透矽插塞結構C2可覆蓋1×1mm2 之晶片下的主要面積。如第23F圖所示，封裝基板460’上排列有4×3的穿透矽插塞結構C2，其位於1×1mm2 之半導體晶片450’下。除了第23A及23C圖所示之穿透矽插塞結構，仍有其他的穿透矽插塞結構。如第24A圖所示之某些實施例中，穿透矽插塞結構C3與穿透矽插塞結構C1及C2類似。穿透矽插塞結構C3之高度為約120μm，其寬度為約100μm。穿透矽插塞結構C3之梳齒寬度與間距均為約20μm。在某些實施例中，封裝基板中採用排列方式為3×3的9個穿透矽插塞結構C3，以覆蓋1×1mm2 之半導體晶片的所有面積。如第24B圖所示之某些實施例中，封裝基板460”中穿透矽插塞結構C3的排列方式可覆蓋1×1mm2 之半導體晶片。
在第20A、20B、21A、23B、23D、23E、23F、及24B圖中，雙面梳結構的穿透矽插塞依序排列，且平行排列的穿透矽插塞結構之梳齒互相對準。如第25A圖所示之某些實施例中，平行排列的穿透矽插塞結構之梳齒可彼此交錯。在第25A圖中，梳狀物S1與S2之梳齒並未互相對準，而是互相交錯。第25B圖為第25A圖之區域P之放大圖，顯示梳狀物S1之梳齒T1與梳狀物S2之梳齒T2並非位於相同水平線上。如前述的某些實施例中，梳齒的第一寬度S3與第二寬度S4大致相同。如第20A、20B、21A、23B、23D、23E、23F、及24B圖所示的某些實施例中，兩個分開的梳狀物之間距S5與梳齒的第一寬度S3及第二寬度S4大致相同。梳狀物之間需有足夠間距，才能提供穿透矽插塞足夠的結構支撐力。然而梳狀物S1與S2彼此交錯，兩相鄰之梳狀物的梳齒間距S6約為1.4倍的S5。若S6、S3、及S4相等，S5可小於S3與S4，且S5約為0.71倍的S3(或S4)。當S5小於S3或S4時，梳狀物的排列可更緊密。當梳狀物之間的間距縮小，可增加封裝基板之負載比。
雖然具有穿透矽插塞之封裝基板需大於半導體晶片以增加其負載比至50%以上，穿透矽插塞結構所占的空間最好不要增加封裝半導體晶片的基板面積。為了增加封裝尺寸，較大的穿透矽插塞面積亦需較多金屬填入穿透矽插塞結構，即增加製程成本。在某些實施例中，duty率最好能控制在小於或等於65%。
如上所述，用於半導體晶片(如LED晶片)之封裝基板，其決定散熱量之duty率越高越好。但有時duty率小於50%(比如20%至30%)即足以用於半導體晶片散熱。在某些實施例中，穿透矽插塞之duty率大於或等於30%。綜上所述，Duty率取決於被封裝的半導體晶片種類。
如上所述的某些實施例中，半導體晶片可為LED晶片。LED晶片可含有多種LED。單一LED可發紅光、黃光、或藍光。為了發出白光，可組合一組或多組三個上述的LED。
上述圖示及描述的穿透矽插塞結構與圖案僅用以舉例。穿透矽通孔或穿透矽插塞之形狀、圖案、與排列亦可為其他未提及於上述段落圖示之變化。具有上述不同圖案之穿透矽插塞可位於一或多個案半導體晶片下以增加散熱性，而穿透矽插塞可依製程考量如銅電鍍時間或結構強度製備。
上述具有穿透矽插塞(或通孔)之封裝基板，可提供需要熱管理之半導體晶片水平與垂直的散熱途徑。具有高負載比之穿透矽插塞設計可有效提供散熱途徑。當穿透矽插塞採用雙面梳設計時，將具有高負載比如大於或等於50%。具有高負載比之封裝基板，可應用於產生大量熱的半導體晶片如LED晶片。
在一實施例中，具有穿透矽插塞之半導體封裝基板可用以封裝半導體晶片以幫助其散熱。半導體封裝基板含有基板與位於其上的穿透矽插塞，且穿透矽插塞自半導體封裝基板的第一表面延伸至相反側的第二表面。穿透矽插塞之截面圖案可為雙面梳，且穿透矽插塞可提供半導體晶片散熱途徑。
在另一實施例中，具有穿透矽插塞之半導體封裝基板可用以封裝半導體晶片以幫助其散熱。半導體封裝基板含有基板與位於其上的穿透矽插塞，且穿透矽插塞自半導體封裝基板的第一表面延伸至相反側的第二表面。穿透矽插塞之duty率大於或等於約50%。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
A1、A2、A3、A4、B1、B2、C1、C2、C3．．．穿透矽插塞結構
D1、D2．．．穿透矽插塞之直徑
D3．．．插塞之間的最短距離
D4．．．穿透矽通孔之直徑
D5．．．穿透矽插塞之間距
D6．．．穿透矽插塞之寬度
H、H1、H2．．．穿透矽插塞結構之高度
H1’．．．穿透矽插塞結構之高度加上間距
L1．．．矩形穿透矽插塞之寬度
L2．．．矩形穿透矽插塞之長度
L3．．．矩形穿透矽插塞之間距
L4．．．開口寬度
L5．．．開口間距
L6．．．穿透矽插塞寬度
L7、L8、L9．．．梳齒間距
O-O．．．切線
P．．．區域
S1、S2．．．梳狀物
S3．．．梳齒的第一寬度
S4．．．梳齒的第二寬度
S5．．．兩個分開的梳狀物之間距
S6．．．兩相鄰之梳狀物的梳齒間距
T1、T2．．．梳齒
W、W1、W2．．．穿透矽插塞結構之寬度
W0．．．穿透矽插塞結構之間距
W1’．．．穿透矽插塞結構之寬度加上間距
100．．．第一基板
101、150．．．介電層
102．．．光阻層
103．．．絕緣層
104、152．．．阻障層/銅晶種層
105．．．圖案化的光阻層
106．．．銅膜
107．．．膠層
108．．．第二基板
110．．．開口
140．．．矽材料
154．．．銅層
155．．．擴散阻障層
156、450、450’．．．半導體晶片
157．．．共熔接合層
158、462．．．焊線
159．．．p型接點
160．．．n型接點
161．．．螢光膜
162．．．成型材料
163．．．膠帶
180．．．封裝晶片
190．．．電路
191．．．蝕刻停止層
192．．．層間介電層
195．．．接點
401、402、403、404、405、407、463．．．穿透矽插塞
406．．．穿透矽通孔
410．．．穿透矽插塞圖案
411．．．開口
460、460’、460”．．．封裝基板
465．．．延伸區域
第1A、1B、2-18圖係本發明某些實施例中，封裝半導體晶粒之流程與對應之結構剖視圖；
第19A-19E圖係本發明某些實施例中，不同設計之穿透矽插塞的上視圖；
第20A及20B圖係本發明某些實施例中，兩種設計之穿透矽插塞的上視圖；
第21A圖係本發明某些實施例中，位於封裝基板上的半導體晶片之上視圖；
第21B圖係第21A圖之側視圖；
第22圖係具有圓潤邊角之第20B圖的結構；
第23A-23F、24A及24B圖係本發明某些實施例中，封裝基板上的穿透矽插塞；以及
第25A及25B係本發明某些實施例中，具有雙面梳狀設計之穿透矽插塞。
O-O．．．切線
450．．．半導體晶片
460．．．封裝基板
462．．．焊線
463．．．穿透矽插塞
465．．．金屬層之延伸區域

Claims (9)

  1. 一種半導體封裝基板，具有多個穿透矽插塞以散逸被封裝的一半導體晶片產生的熱，包含：一基板，具有該些穿透矽插塞於該半導體封裝基板上；其中該些穿透矽插塞自該半導體封裝基板之一第一表面延伸至相反側之一第二表面，其中該些穿透矽插塞之截面形狀為雙面梳，且其中該些穿透矽插塞提供該半導體晶片多個散熱途徑。
  2. 如申請專利範圍第1項所述之半導體封裝基板，其中該些穿透矽插塞之負載比大於或等於約50%。
  3. 如申請專利範圍第1項所述之半導體封裝基板，其中該半導體晶片係一發光二極體晶片。
  4. 如申請專利範圍第1項所述之半導體封裝基板，其中每一該些雙面梳之長度介於約100μm至約300μm之間，且每一該些雙面梳之寬度介於約100μm至約300μm之間。
  5. 如申請專利範圍第3項所述之半導體封裝基板，其中該些穿透矽插塞之截面積，大於該發光二極體晶片對應該半導體封裝基板之表面的面積。
  6. 如申請專利範圍第3項所述之半導體封裝基板，其中該發光二極體晶片與該些穿透矽插塞之間夾設一金屬層，且其中該金屬層提供該發光二極體晶片多個水平方向的散熱途徑。
  7. 如申請專利範圍第1項所述之半導體封裝基板，其中相鄰的兩個該雙面梳以交錯方式排列。
  8. 一種半導體封裝基板，具有多個穿透矽插塞以散逸被封裝的一半導體晶片產生的熱，包含：一基板，具有該些穿透矽插塞於該半導體封裝基板上；其中該些穿透矽插塞自該半導體封裝基板之一第一表面延伸至相反側之一第二表面，且其中該些穿透矽插塞之負載比大於或等於約50%，其中該些穿透矽插塞之截面形狀為雙面梳，且其中該些穿透矽插塞提供該半導體晶片多個散熱途徑。
  9. 如申請專利範圍第8項所述之半導體封裝基板，其中該半導體晶片係一發光二極體晶片。
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US20110241040A1 (en) 2011-10-06
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TW201135884A (en) 2011-10-16
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US8507940B2 (en) 2013-08-13
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US20160197014A1 (en) 2016-07-07
US8946742B2 (en) 2015-02-03
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US20150147834A1 (en) 2015-05-28
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US10049931B2 (en) 2018-08-14
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