CN102214617A - 半导体封装基板 - Google Patents

半导体封装基板 Download PDF

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Publication number
CN102214617A
CN102214617A CN2011100381813A CN201110038181A CN102214617A CN 102214617 A CN102214617 A CN 102214617A CN 2011100381813 A CN2011100381813 A CN 2011100381813A CN 201110038181 A CN201110038181 A CN 201110038181A CN 102214617 A CN102214617 A CN 102214617A
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China
Prior art keywords
silicon
penetrate
substrate
layer
connector
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CN2011100381813A
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CN102214617B (zh
Inventor
余振华
张宏宾
林咏淇
余佳霖
洪瑞斌
黄见翎
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供的半导体封装基板具有穿透硅插塞(或通孔)可提供需要热管理的半导体芯片水平与垂直的散热途径。具有高负载比设计的穿透硅插塞能有效增加散热性。当穿透硅插塞采用双面梳图案时，其负载比可高达大于或等于50％。具有高负载比的封装基板可用于产生大量热的半导体芯片。举例来说，半导体芯片可为发光二极管芯片。

Description

半导体封装基板
技术领域
本发明涉及一种半导体封装基板，更特别涉及其穿透硅插塞的构形、排列、及形状。
背景技术
缩减外观尺寸及改良电性效能为先进半导体封装的趋势，可让产业及消费者使用更快、更便宜、且更小的产品。经由穿透硅通孔(TSV)或更精确的穿透硅插塞(TSP)，可提高先进半导体封装的集成度及缩减其外观尺寸。如名所示，半导体元件其正面及背面的电性连接可垂直组装封装中的多重芯片，而非公知的单一芯片。如此一来，越来越多的半导体元件可整合至越来越小的外观尺寸中。此外，不同种类的半导体芯片也可整合至单一封装以形成所谓的系统级封装(SIP)。不论如何，减少印刷电路板中多重封装的针脚数目也可降低最终产品的成本。由于单一基板连线可用以连接多重芯片，采用TSV作为芯片之间的内连线可大幅减少芯片与基板之间的电性连接数目，并简化组装工艺与改善良率。此外，穿透硅通孔具有绝佳的散热效果。
由于发光二极管(LED)具有高输出光效率，近年来以LED作为发光元件的情况显著提升。然而电能在通过LED的PN结时产生的热能无法转换为所需的光能。若无法移除这些热能，高温下操作LED不只会降低其效率，还会使LED的可信度降低，甚至危害使用者安全。综上所述，LED的热管理非常重要。
发明内容
为了解决现有技术中存在的上述问题，本发明一实施例提供一种半导体封装基板，具有穿透硅插塞以散逸被封装的半导体芯片产生的热，包含基板，具有穿透硅插塞于半导体封装基板上，其中穿透硅插塞自半导体封装基板的第一表面延伸至相反侧的第二表面，其中穿透硅插塞的截面形状为双面梳，且其中穿透硅插塞提供半导体芯片多个散热途径。
本发明又一实施例提供一种半导体封装基板，具有穿透硅插塞以散逸被封装的半导体芯片产生的热，包含基板，具有穿透硅插塞于半导体封装基板上，其中穿透硅插塞自半导体封装基板的第一表面延伸至相反侧的第二表面，且其中穿透硅插塞之负载比大于或等于约50％。
本发明实施例提供的半导体封装基板具有穿透硅插塞(或通孔)可提供需要热管理的半导体芯片水平与垂直的散热途径。具有高负载比设计的穿透硅插塞能有效增加散热性。当穿透硅插塞采用双面梳图案时，其负载比可高达大于或等于50％。具有高负载比的封装基板可用于产生大量热的半导体芯片。
附图说明
图1A、图1B、图2-图18为本发明某些实施例中，封装半导体裸片的流程与对应的结构剖视图；
图19A-图19E为本发明某些实施例中，不同设计的穿透硅插塞的俯视图；
图20A及图20B为本发明某些实施例中，两种设计的穿透硅插塞的俯视图；
图21A为本发明某些实施例中，位于封装基板上的半导体芯片的俯视图；
图21B为图21A的侧视图；
图22为具有圆润边角的图20B的结构；
图23A-图23F、图24A及图24B为本发明某些实施例中，封装基板上的穿透硅插塞；以及
图25A及25B为本发明某些实施例中，具有双面梳状设计的穿透硅插塞。
主要附图标记说明：
A1、A2、A3、A4、B1、B2、C1、C2、C3～穿透硅插塞结构；D1、D2～穿透硅插塞的直径；D3～插塞之间的最短距离；D4～穿透硅通孔的直径；D5～穿透硅插塞的间距；D6～穿透硅插塞的宽度；H、H1、H2～穿透硅插塞结构的高度；H1’～穿透硅插塞结构的高度加上间距；L1～矩形穿透硅插塞的宽度；L2～矩形穿透硅插塞的长度；L3～矩形穿透硅插塞的间距；L4～开口宽度；L5～开口间距；L6～穿透硅插塞宽度；L7、L8、L9～梳齿间距；O-O～切线；P～区域；S1、S2～梳状物；S3～梳齿的第一宽度；S4～梳齿的第二宽度；S5～两个分开的梳状物的间距；S6～两相邻的梳状物的梳齿间距；T1、T2～梳齿；W、W1、W2～穿透硅插塞结构的宽度；W0～穿透硅插塞结构的间距；W1’～穿透硅插塞结构的宽度加上间距；100～第一基板；101、150～介电层；102～光致抗蚀剂层；103～绝缘层；104、152～阻挡层/铜晶种层；105～图案化的光致抗蚀剂层；106～铜膜；107～胶层；108～第二基板；110～开口；140～硅材料；154～铜层；155～扩散阻挡层；156、450、450’～半导体芯片；157～共熔接合层；158、462～焊线；159～p型接点；160～n型接点；161～萤光膜；162～成型材料；163～胶带；180～封装芯片；190～电路；191～蚀刻停止层；192～层间介电层；195～接点；401、402、403、404、405、407、463～穿透硅插塞；406～穿透硅通孔；410～穿透硅插塞图案；411～开口；460、460’、460”～封装基板；465～延伸区域；
具体实施方式
可以理解的是，下述内容提供多种实施例或实例以说明本发明的多种特征。为了简化说明，将采用特定的实施例、单元、及组合方式说明。然而这些特例仅用以说明而非限制本发明。此外为了简化说明，本发明在不同图示中采用相同附图标记标示不同实施例的类似元件，但上述重复的附图标记并不代表不同实施例中的元件具有相同的对应关系。
图1A-图18为本发明某些实施例的中间工艺的剖视图。如图1A所示，某些实施例的第一基板100上具有光致抗蚀剂图案。第一基板100可为基体硅、掺杂或未掺杂的基板、或绝缘层上半导体(SOI)基板的有源层。一般的SOI基板含有半导体材料层如硅形成于绝缘层上。上述绝缘层可为氧化埋层(BOX)或氧化硅层。绝缘层可形成于基板(如一般硅基板或玻璃基板)上。此外，第一基板100也可为其他基板如多层结构或组成渐变式基板。
在下述例中，第一基板100的组成为硅材料140，其上沉积有介电层101。接着在介电层101上沉积光致抗蚀剂层102，并图案化光致抗蚀剂层102以形成开口作为后续的穿透硅通孔。介电层101在后续穿透硅通孔的蚀刻工艺中，可作为保护基板表面的牺牲层。
如图1B所示的某些实施例中，在沉积与图案化光致抗蚀剂层102前，第一基板100已具有电路190形成其上。在图1B中，电路190已形成于第一基板100上。电路190可为任何特定用途的电路。在一实施例中，电路190含有电子元件形成于第一基板100上，以及一或多层介电层形成于电子元件上。在介电层之间可形成金属层以传递电子元件之间的电子信号。电子元件可形成于一或多层的介电层上或介电层中。
举例来说，电路190可具有多种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)元件如晶体管、电容、电阻、二极管、光二极管、熔丝、或类似物，彼此以内连线相接以形成具有一或多种功能的结构如记忆结构、处理结构、传感器、放大器、功率分布器、输入/输出电路、或类似物。本领域普通技术人员应理解上述实例仅用以举例及进一步说明本发明，并非用以局限本发明。本发明也可采用其他电路。
同样在图1B中，接着形成蚀刻停止层191与层间介电层(ILD)192。在某些实施例中，蚀刻停止层191的组成较佳为介电材料，其蚀刻选择率最好与邻接的层状结构(比如下方的第一基板100与上方的层间介电层192)不同。在一实施例中，蚀刻停止层191的组成可为氮化硅、碳氮化硅、碳氧化硅、氮化碳、或类似物。蚀刻停止层191的沉积方法可为化学气相沉积法(CVD)、或等离子体增强式CVD(PECVD)。
层间介电层(ILD)192的组成可为低介电常数材料如磷掺杂硅酸盐玻璃(PSG)、硼磷掺杂硅酸盐玻璃(BPSG)、氟化硅酸盐玻璃(FSG)、碳氧化硅、旋涂玻璃、旋涂高分子、硅碳材料、上述的化合物、上述的复合物、上述的组合、或类似物。层间介电层192的形成方法可为本技术领域已知的方法如旋转涂布法、CVD、或PECVD。必需注意的是，蚀刻停止层191与层间介电层192可为多层的介电层结构，且在相邻的介电层之间可视情况夹设或不夹设额外的蚀刻停止层。
接着形成接点195穿过层间介电层192，以提供电性连接至电路190。接点195的形成方法可为光刻工艺如沉积并图案化光致抗蚀剂材料于层间介电层192上，层间介电层192露出的部份将用以形成接点195。接着进行蚀刻工艺如非等向干蚀刻以形成开口于层间介电层192中。可将扩散阻挡层和/或粘着层(未图示)衬垫于开口中，再将导电材料填入开口。扩散阻挡层较佳为一或多层的氮化钽、钽、氮化钛、钛、钴钨合金、或类似物，而导电材料可为铜、钨、铝、银、或上述的组合、或类似物。至此形成图1B所示的接点195。
如图2所示的一实施例中，第一基板100被蚀刻出开口。虽然图2并未显示图1B中的电路190、接点195、蚀刻停止层191、与层间介电层192，上述结构仍存在于图2及后续图示。在一实施例中，时间控制的蚀刻工艺如非等向干蚀刻，可蚀刻第一基板100直到开口110所需的深度。可以理解的是，蚀刻工艺可为单一蚀刻工艺或多重蚀刻工艺，且蚀刻工艺可为干蚀刻或湿蚀刻。
在某些实施例中，开口110的深度可介于约20μm至约200μm之间。在某些实施例中，开口宽度可介于约5μm至约100μm之间。在某些实施例中，开口为穿透硅通孔(或沟槽)。蚀刻开口的深度完全取决于光致抗蚀剂层102本身的物理限制。在此实施例中，先蚀刻介电层101作为图案化遮罩层。介电层101的组成可为任何介电材料如氧化硅、氮化硅、或上述的组合。在一实例中，介电层101为PECVD沉积的氧化硅，此沉积反应的硅来源为四乙氧硅烷(TEOS)。此外，介电层101也可为硅烷氧化膜。在某些实施例中，TEOS氧化层的厚度介于约至约
Figure BSA00000435044500052
之间。介电层101不限于PECVD沉积的方法，也可为旋涂介电层(SOD)或旋涂玻璃(SOG)。介电层101的沉积法(或成长法)也可为热工艺，比如热成长的氧化硅或热CVD沉积的氧化膜。
在蚀刻基板形成穿透硅通孔后，将移除光致抗蚀剂层与牺牲介电层101。在形成开口如开口101后，可将开口填入材料。如图3所示的某些实施例中，先以绝缘层103与阻挡层/铜晶种层104衬垫第一基板100。绝缘层103的组成为介电材料如氧化物、氮化物、或上述的组合。在一实例中，绝缘层103为PECVD沉积的氧化硅，其硅来源为硅烷或TEOS。在某些实施例中，绝缘层103的厚度介于约
Figure BSA00000435044500053
至约之间。绝缘层103的沉积法(或成长法)也可为热工艺，比如热成长的氧化物或热CVD沉积的氧化膜。在其他实施例中，绝缘层103可为掺杂膜，其掺质可为磷、或磷与硼。掺杂磷的硅玻璃(PSG)或掺杂硼磷的硅玻璃(BPSG)中的磷可吸收铜，而上述组成可填入此例的穿透硅通孔(或沟槽)的开口中。铜会扩散至硅基板中。即使穿透硅通孔已衬有后述的阻挡层，阻挡层对通孔底部附近侧壁(如角落170)的覆盖率可能不足。采用PSG或BPSG作为绝缘层103可进一步保护基板不受铜扩散影响。
绝缘层103的热阻性大于硅。表1为不同厚度的氧化物介电层与不同厚度的硅材质的第一基板100，搭配后的热阻性模拟比较。
表1
  硅基板(μm)/氧化物(μm)   热阻性(K/Watt)
  100/0   1.81
  100/1.5   6.37
  50/0   0.92
  50/1.5   5.95
由表1可知，氧化物将大幅增加热阻性。如此一来，封装中的介电层厚度越小越好。
在沉积绝缘层103后，将沉积阻挡/晶种层104。阻挡层/铜晶种层104包含至少两层，分别为阻挡层与铜晶种层。阻挡层的材料可为一或多种铜阻挡材料如钽、氮化钽、钛、氮化钛、钴钨合金、或类似物。阻挡层可避免铜扩散至硅材质的第一基板100中。阻挡层的沉积方法可为物理气相沉积法(PVD)、CVD、原子层沉积(ALD)、或其他方法。在沉积阻挡层后，可沉积铜晶种层。同样地，铜晶种层的沉积方法可为PVD、CVD、ALD、或其他方法。在某些实施例中，阻挡层/铜晶种层104为氮化钽/钽的阻挡层与铜晶种层。在此实施例中，阻挡层由氮化钽层与钽层组成。在某些实施例中，氮化钽、钽、与铜晶种层的沉积法均为PVD，且上述沉积均在单一PVD腔室中进行，差别仅在于靶材与溅镀气体。在某些实施例中，氮化钽与钽的厚度各自介于约至约
Figure BSA00000435044500062
之间，而铜晶种层的厚度介于约
Figure BSA00000435044500063
至约
Figure BSA00000435044500064
之间。
在沉积阻挡层/铜晶种层104后，图案化基板以定义进行铜电镀的区域。如图4所示的某些实施例中，在第一基板100上形成图案化的光致抗蚀剂层105。在某些实施例中，图案化的光致抗蚀剂层105的组成为一般光致抗蚀剂，可为液态并以旋涂工艺沉积于基板上。在另一实施例中，图案化的光致抗蚀剂层105为干膜光致抗蚀剂(DFR)，其图案化的方法也可为光刻工艺(包含曝光)。DFR可为正光致抗蚀剂或负光致抗蚀剂。DFR用以形成图案，以便电路板进行后续电镀。DFR可为日本TOK有限公司所制的MP112。当DFR压合至第一基板100(或其上的阻挡层/铜晶种层104)后，将曝光DFR以定义基板表面稍后进行铜电镀的区域。与湿式的旋涂光致抗蚀剂相较，干膜光致抗蚀剂的好处在于其仅压合至基板表面。相反地，湿式旋涂光致抗蚀剂会流入开口如开口110中。由于穿透基板通孔(或沟槽)具有相当深度(如前所述的约20μm至约200μm之间)，卡在开口中的光致抗蚀剂将难以完全移除。这将使铜无法适当地电镀至开口的侧壁及底部表面上。
如图5所示的某些实施例中，在铜膜106电镀至第一基板100的表面上后，可自基板表面剥除DFR。上述电镀工艺，可为一般用以形成半导体元件的金属内连线的铜电镀工艺或无电铜电镀工艺。在某些实施例中，铜膜106的厚度小于约30μm。在其他实施例中，铜膜106的厚度小于约20μm。在又一实施例中，铜膜106的厚度小于约10μm。太厚的铜膜会导致基板翘曲。在某些实施例中，铜膜106仅填入开口(或穿透基板通孔)如图4所示的开口110中。在另一实施例中，铜膜106不只沉积于开口(穿透基板通孔)中，也提供基板上封装元件的定位垫如印刷电路板(PCB)，或用以容置半导体芯片。
在某些实施例中，铜膜106的厚度介于约10μm至约30μm之间。在电镀形成铜膜106后，将移除图案化的光致抗蚀剂层105。不论是湿式旋涂光致抗蚀剂或干膜光致抗蚀剂，其移除方法均可为灰化法，后续辅以湿式清洁工艺以完全移除基板表面上的杂质。
如图6所示的某些实施例中，在铜电镀及光致抗蚀剂移除工艺后，将移除先前被光致抗蚀剂覆盖而未进行电镀的阻挡层/铜晶种层104。在上述工艺后，将基板的正面粘结至图7所示的第二基板108。第二基板为虚置基板，其组成可为介电材料如玻璃。在其他实施例中，第二基板108的组成可为导电材料如金属。如图7所示的某些实施例中，以胶层107粘结第一基板100与第二基板108。胶层107的组成特性为易于移除的材料，这在不需要虚置的第二基板108时特别有用。在某些实施例中，胶层107的组成为环氧高分子。先将液态的胶层107施加于第一基板100上，再将第二基板108置于胶层107上，接着以自然风干或低温加热的方式处理胶层。在干燥及加热(或硬化)工艺后，第一基板100将紧密贴合虚置的第二基板108。
接着研磨第一基板100的背面以移除多余的硅层，直到露出穿透硅通孔120。在某些实施例中，在背面研磨工艺后接着进行化学机械研磨(CMP)，以平坦化研磨后的基板表面。如图8所示的某些实施例中，移除第一基板100背面的硅层以露出穿透硅通孔120。在某些实施例中，移除硅的工艺为研磨工艺。在封装工艺中，一般可用研磨轮移除硅基板上多余的硅层。上述研磨工艺将进行到完全移除穿透硅通孔120底部的绝缘层103与阻挡层/铜晶种层104为止。
薄化硅基板的厚度有助于改善其散热效率。表2为不同厚度的硅基板的热阻性模拟比较。
表2
  硅基板(μm)   热阻性(K/Watt)
  500   4.82
  200   3.18
  100   1.81
  50   0.92
由表2的数据可知，当基板薄化至100μm时可大幅降低其热阻性。除了穿透硅通孔(或沟槽)中的铜以外，薄化硅基板也可增加散热能力。
如图9所示的某些实施例中，在研磨基板背面后，沉积介电层150于第一基板100的背面上。与绝缘层103类似，介电层150的组成可为氧化物、氮化物、或上述的组合。在一实施例中，介电层150为PECVD沉积的氧化硅，其硅来源为硅烷。在某些实施例中，介电层150的厚度介于约
Figure BSA00000435044500081
至约
Figure BSA00000435044500082
之间。在某些实施例中，介电层150为掺杂膜，且掺质为磷、或磷与硼。如前所述，PSG或BPSG中的磷可吸收铜。
如图10所示的某些实施例中，在沉积介电层150后再沉积与图案化光致抗蚀剂层151。光致抗蚀剂层150可为旋涂的湿式光致抗蚀剂或干膜光致抗蚀剂。光致抗蚀剂层151的图案开口对应后续穿透基板通孔的形成区域。图案化光致抗蚀剂层所露出的介电层150将被蚀刻移除。一般应用于半导体芯片工艺的介电层蚀刻可用以移除介电层150。蚀刻工艺可为干式或湿式。如图11所示的某些实施例中，第一基板100与第二基板的开口区域中的介电层150被蚀刻。
如图12所示的某些实施例中，接着沉积阻挡层/铜晶种层152。阻挡层/铜晶种层指的是阻挡层与铜晶种层的复合层。阻挡层可保护硅基板不受铜扩散的影响。如前所述，阻挡层的组成可为钽、氮化钽、钛、氮化钛、钴钨合金、或上述的组合。在某些实施例中，阻挡层的组成为厚度介于约
Figure BSA00000435044500091
至约的钛层。薄铜晶种层的沉积厚度介于约
Figure BSA00000435044500093
至约
Figure BSA00000435044500094
之间。用以沉积阻挡层与铜晶种层的方法已陈述于上，在此不赘述。
如图13所示的某些实施例中，在沉积阻挡层/铜晶种层152后，沉积与图案化光致抗蚀剂层151以定义后续进行铜电镀的区域。如前所述，光致抗蚀剂层可为旋涂的湿式光致抗蚀剂或干膜光致抗蚀剂。在图案化光致抗蚀剂层后，先电镀铜层154于基板未被光致抗蚀剂层覆盖的露出区域。如前所述，铜层154的电镀工艺可为电化学电镀工艺(ECP)或无电铜电镀工艺。在某些实施例中，铜层154的厚度小于30μm以避免前述的基板翘曲问题。在某些实施例中，铜层154的厚度介于约10μm至约20μm之间。之后沉积扩散阻挡层155于铜层154上。在下述段落中，扩散阻挡层155最后会容纳焊料层与一或多个集成电路(IC)芯片。扩散阻挡层155可避免铜层154的铜扩散至位于TSV基板上的IC芯片。在某些实施例中，扩散阻挡层155的沉积方法也可为电镀如ECP或无电电镀法。在某些实施例中，扩散阻挡层155的组成为化学镀镍浸金层(ENIG)。然而，扩散阻挡层也可采用任何合适的扩散阻挡材料。
在沉积扩散阻挡层155后，可移除光致抗蚀剂层153与其下的阻挡层/铜晶种层152。如图14所示的某些实施例中，第一基板100不具有光致抗蚀剂层153与其下的阻挡层/铜晶种层152。此时第一基板100已准备好容纳半导体芯片。不同的半导体芯片可嵌置于第一基板100上，其嵌置流程仅有些许差异。在某些实施例中，半导体芯片为发光二极管或类似的发光元件。
在上述步骤后，可采用共熔接合层157将半导体芯片156固定至扩散阻挡层155。在某些实施例中，共熔接合层157的组成为焊料。如图15所示的实施例中，半导体芯片156为发光二极管(LED)。LED芯片置于p型接点159上，且LED芯片经由焊线158电性连接至n型接点160。焊线接合步骤可用以连接LED的半导体芯片156至n型接点160。如图15所示的某些实施例中，置于第一基板100上的LED的半导体芯片156，经由共熔接合层157接合至第一基板100，且经由焊线158接合至n型接点。由于扩散阻挡层155与p型接点159的表面等高，LED的芯片156可直接位于第一基板100上而不需导电凸块。
图13-图15所示的铜层154可提供顶部的LED的半导体芯片156电性连接与热接点。铜层154也称之为金属垫，且不必由铜组成。在某些实施例中，金属垫的组成为焊料。金属垫的沉积方法可为前述的电镀工艺，或在图案化光致抗蚀剂层153后施加焊料膏于基板表面上。焊料膏可填入光致抗蚀剂层153的开口中，且残留于光致抗蚀剂层153上的焊料膏非常少，不太影响后续光致抗蚀剂层的移除工艺。在某些实施例中，若采用焊料作为金属垫，则不需阻挡层/铜晶种层152中的铜晶种层部份。若以电镀法形成焊料层，则需要焊料晶种层或非焊料材料组成的晶种层。然而，采用焊料膏形成于基板上可省略晶种层。
如图15所示，部份的穿透硅通孔120与铜层(或金属垫)154延伸超过LED的半导体芯片156的边缘。封装基板(如第一基板100)其电性和/或热连接(如穿透基板通孔120与铜层154)超过半导体芯片(如LED)156边界的延伸部份可称作扇出封装，这可提供再布线与散热的额外区域。铜层(或金属垫)154超出LED的半导体芯片156边缘的延伸部份可提供水平方向的散热通路区域。穿透硅通孔120超出LED的半导体芯片156边缘的延伸部份可提供额外的穿透硅通孔120空间，这可提供垂直方向的散热通路区域。上述水平与垂直方向的通路区域均影响并改善散热效率。
如图16所示的某些实施例中，在LED的半导体芯片156接合至基板及焊线接合LED的半导体芯片156后，封装LED的半导体芯片156。在某些实施例中，可沉积萤光膜161于LED的半导体芯片156上。LED芯片可设计为发红光、蓝光、或绿光，且通常搭配组合以发出白光。萤光膜可用以发出白光。在某些实施例中，萤光膜161涂布于LED的半导体芯片156上。不过萤光膜161并非必要元件，可视情况决定是否采用。在某些实施例中，可在发出不同颜色(或光波波长)的LED上涂布不同的萤光膜。在某些实施例中，可省略萤光膜如萤光膜161。
接着可沉积成型材料162以包围LED的半导体芯片156、p型接点159、与n型接点160。在某些实施例中，成型材料的组成为透明的环氧树脂。透明的成型材料较适用于LED。若半导体芯片156不是LED，则成型材料不一定非得为透明组成不可。
如图17所示的某些实施例中，成型的LED的半导体芯片156置于胶带163上。胶带(有时称作蓝带)163在准备分离(或脱离)第二基板108时，可稳定支撑LED的半导体芯片156的成型材料162与第一基板100。在化学与机械移除第二基板108与胶层107后，将切割第一基板100以物理分隔第一基板100上的裸片。上述每一裸片均具有LED的半导体芯片156、n型接点160、与p型接点159。如图18所示的某些实施例中，移除虚置的第二基板108与胶层107后，胶带163支撑住单一封装芯片180。之后可进行其他工艺，比如将封装芯片180置于印刷电路板上、移除胶带163、或类似工艺。
上述流程显示如何将半导体芯片封装至具有穿透硅通孔的基板以提高散热效果。此外，由于上述封装芯片的硅基板厚度已薄化至约20μm至约200μm之间，因此散热效果超过其他穿透硅通孔技术。
上述的芯片封装方法与结构可用于非LED的半导体芯片。当这些芯片封装方法与结构用于非LED的芯片时，工艺会有些许不同，特别是在采用LED的工艺步骤之后(比如图15以后的工艺)。
半导体芯片下的穿透硅通孔可具有多种形状与尺寸。举例来说，穿透硅通孔的形状可为圆柱。图19A为本发明某些实施例中，穿透硅插塞(或穿透硅通孔)401的俯视图。穿透硅插塞401为圆柱，其直径为D1。如前所述，直径D1介于约5μm至约100μm之间。当小型芯片的上表面面积与穿透硅插塞401的表面积类似时，可采用单一穿透硅插塞(如穿透硅插塞401)。然而，半导体芯片其上表面积通常远大于单一穿透硅插塞的表面积。举例来说，LED芯片的表面积可为0.6×0.6mm2、1×1mm2、或更大面积。上述数字仅用以举例。此外，半导体芯片的上表面并不必然为方形，也可为矩形或其他形状。
穿透硅插塞的长度不应太长(或其截面积不应太大)，以避免孔洞填充时间过长或其他问题。如图19B所示的实施例中，多重穿透硅插塞(或穿透硅通孔)402、403、404、与405可提供位于其上的半导体芯片散热途径。虽然图19B仅显示四个穿透硅插塞，但上述结构中的硅插塞数目可大于四个或小于四个(比如两个或三个)。在某些实施例中，图19B中的每一穿透硅插塞的直径D2介于约5μm至约100μm之间。图19B中两个穿透硅插塞之间的最短距离为D3。在某些实施例中，穿透硅插塞之间的距离D3大于或等于穿透硅插塞的直径D2。穿透硅插塞之间的距离必需大到足以确定彼此之间的电性绝缘与结构强度。如前述流程，基板将进行后续机械工艺如研磨背面与视情况添加的CMP，这会施加大量应力于基板上。若穿透硅插塞之间的介电层的机械支撑力不足，基板将会碎裂和/或基板中具有穿透硅插塞的层状结构会碎裂或剥离。
在某些实施例中，穿透硅插塞(或穿透硅通孔)的构形可为同心环与中心圆柱，如图19C所示。同心环的数目可为一或多个。图19C显示一个同心环407环绕一中心圆柱406。在某些实施例中，穿透硅通孔406具有直径D4，而穿透硅插塞407的宽度D6介于约5μm至约100μm之间。在某些实施例中，穿透硅插塞之间的距离D5大于或等于穿透硅通孔的直径D4或穿透硅插塞的宽度D6。如前所述，绝缘层需有足够支撑。
穿透硅插塞并不必然为圆形，也可为其他形状如三角形、方形、矩形、卵形、或六角形等等。如图19D所示的某些实施例中，显示多个矩形的穿透硅插塞，比如穿透硅插塞408与409。矩形的穿透硅插塞(或穿透硅沟槽)408与409均具有宽度L1及长度L2，且两者相隔的间距为L3。在某些实施例中，矩形穿透硅插塞的宽度L1介于约5μm至约100μm之间。在某些实施例中，矩形穿透硅插塞的间距L3大于或等于矩形穿透硅插塞的宽度L1。矩形穿透插塞的数目可为一或多个。
在某些实施例中，穿透硅插塞可为图19E所示的图案。图19E显示穿透硅插塞图案410具有多个开口(比如开口411)位于其中。图19E中的开口411的截面为方形。然而，开口也可为矩柱、圆柱、或其他形状的柱状物。在某些实施例中，开口411的间距L5可小于或等于开口411的宽度L4。
如图20A及图20B所示的某些实施例中，穿透硅插塞具有两种其他构形。图20A及图20B所示的某些实施例中的构形类似，均为双面梳状。图20B的穿透硅插塞的双面梳比图20A的穿透硅插塞的双面梳长。在某些实施例中，图20A及图20B的穿透硅插塞的宽度均为L6，且L6的范围介于约5μm至约100μm之间。在某些实施例中，图20A及图20B中的梳齿间距L7、L8、及L9大于或等于穿透硅插塞的宽度L6，且梳齿间距L7、L8、及L9介于约5μm至约100μm之间。图20A中的穿透硅插塞结构A1、A2、A3、及A4具有宽度W1及高度H1。在图20A中，穿透硅插塞结构A1的宽度加上间距的距离为W1’，其高度加上间距的距离为H1’。在图20B中的穿透硅插塞结构B1及B2具有宽度W2及高度H2。在图20B中，穿透硅插塞结构B1的宽度加上间距的距离为W2’。穿透硅插塞结构A1其一侧的梳齿数目为3，但梳齿可为任何数目如1、2、…、至N。N为整数，可为10或更大数目。穿透硅插塞结构B1其一侧的梳齿数目可多到延伸至整个半导体芯片156(如LED)的长度或宽度。上述芯片位于穿透硅插塞基板如第一基板100上。在某些实施例中，图20A或图20B的穿透硅插塞结构A1或B1可重复直到盖满整个半导体芯片的长度或宽度。在某些实施例中，图20A或图20B的穿透硅插塞结构A1或B 1可重复直到盖满整个半导体芯片的长度或宽度，并延伸出半导体芯片的长度或宽度。举例来说，封装基板的穿透硅插塞区域大于半导体芯片的区域。穿透硅插塞结构其宽度与高度的设计最好能提供半导体芯片足够的散热性。
图20A的穿透硅插塞结构A1、A2、A3、及A4，与图20B的穿透硅插塞结构B1及B2的图案设计均可让穿透硅插塞具有最大截面积。但图20A及图20B中的穿透硅插塞均非单一大型穿透硅插塞，比如图19A所示的穿透硅插塞401。多重图案可避免工艺问题，比如过长的电镀时间、结构支撑力不足、或其他问题。穿透硅插塞的截面积越大，越能提供较多的热传导途径与区域。如前所述，某些半导体芯片如LED芯片所产生的大量热能需能有效散热。若基板具有较大截面积的穿透硅插塞，可提供较多的散热途径。负载比可用以定性具有穿透硅插塞的基板其热传导途径量。负载比的定义为传导面积(比如穿透硅插塞的截面积)除以芯片(置于传导区上的芯片如LED芯片)的总截面积，如式1所示。
负载比＝传导面积/芯片总截面积(式1)
与具有低负载比的封装相较，具有高负载比的半导体封装(或基板)可提供较高散热率。图20A的实施例中，穿透硅插塞的构形具有四个分开的穿透硅插塞结构A1、A2、A3、及A4。图20B的实施例中，穿透硅插塞的构形具有两个分开的穿透硅插塞结构B1及B2。若图20A及图20B的穿透硅插塞结构的梳状物具有相同宽度与间距，则图20B的穿透硅插塞构形的负载比高于图20A的穿透硅插塞构形。与图20B的构形相较，图20A的构形中的穿透硅插塞结构A1与A3之间(A2与A4之间)具有额外空隙。如此一来，图20A的构形的负载比必然小于图20B的构形。若图20B中穿透硅插塞梳状物的宽度与间距相同，即L6＝L7＝L9，则穿透硅插塞的截面积占总截面积的50％或更高。若穿透硅插塞结构延伸出半导体芯片的边缘(扇出封装)，其负载比将大于50％。
如图21A所示的某些实施例，为半导体芯片450置于封装基板460顶部上的俯视图。封装基板460的穿透硅插塞结构延伸出半导体芯片450的宽度与长度。如图21A所示，封装芯片的负载比大于50％。如图21A所示的某些实施例中，若半导体芯片450为LED芯片，则穿透硅插塞463为n型接点的一部份。在这种情况下的某些实施例中，位于p型接点上的LED的半导体芯片450将经由焊线462连接至n型接点。
如前所述，金属层如图15-图18的铜层154可提供半导体芯片与穿透硅插塞之间的连线。金属层的延伸区域465超出半导体芯片450的范围，可提供半导体芯片465水平的散热途径。图21B为图21A中O-O切线的剖视图。封装基板460的穿透硅插塞可提供垂直的散热途径。
图19D、图19E、图20A、及图20B的穿透硅插塞结构均具有垂直的边角。在基板工艺中，图案化步骤可圆润化上述结构的边角。图20B的穿透硅插塞结构的边角可圆润化如图22所示。如图23A所示的某些实施例中，将图23A中两个边角圆润化的穿透硅插塞结构C1相接，即形成图22的边角圆润化的穿透硅插塞结构。在某些实施例中，穿透硅插塞结构C1的高度H介于约150μm至约125μm之间。在某些实施例中，穿透硅插塞结构C1的梳齿的宽度与间距均为约25μm。以某些半导体芯片如LED芯片为例，其面积约为0.6×0.6mm2。借由将16个穿透硅插塞结构C1以4×4的方式排列，可填满半导体芯片下的面积。穿透硅插塞结构C1的宽度W为约125μm，而两个穿透硅插塞结构C1的间距W0为约25μm。图23B中的16个穿透硅插塞结构C1填满封装基板其0.6×0.6mm2的面积，用以帮助面积为0.6×0.6mm2的半导体芯片散热。在穿透硅插塞结构C1之间的间距W0为约25μm。
如图23C所示的某些实施例中，与图23A的穿透硅插塞结构C1类似的穿透硅插塞C2，其长度为约300μm且宽度为约250μm。在某些实施例中，穿透硅插塞结构C2的梳齿的宽度与间距均为约50μm。以某些半导体芯片如LED芯片为例，其面积约为0.6×0.6mm2。借由将4个穿透硅插塞结构C1以2×2的方式排列，可填满半导体芯片的面积。图23D显示4个穿透硅插塞结构C2的排列方式。在穿透硅插塞结构C2之间的间距为约50μm。在某些实施例中，每一双面梳状物如穿透硅插塞结构C1、C2、与C3的宽度介于约100μm至约300μm之间。在某些实施例中，每一双面梳状物如穿透硅插塞结构C1、C2、与C3的长度介于约100μm至约300μm之间。
当半导体芯片的面积增大，可采用额外的穿透硅插塞结构以提供高负载比及高散热性。在某些实施例中，半导体芯片的尺寸为约1×1mm2。如图23E所示的某些实施例中，排列方式为7×7的穿透硅插塞结构C1可覆盖大部份芯片下的面积。在其他实施例中，排列方式为4×3的穿透硅插塞结构C2可覆盖1×1mm2的芯片下的主要面积。如图23F所示，封装基板460’上排列有4×3的穿透硅插塞结构C2，其位于1×1mm2的半导体芯片450’下。除了图23A及图23C所示的穿透硅插塞结构，仍有其他的穿透硅插塞结构。如图24A所示的某些实施例中，穿透硅插塞结构C3与穿透硅插塞结构C1及C2类似。穿透硅插塞结构C3的高度为约120μm，其宽度为约100μm。穿透硅插塞结构C3的梳齿宽度与间距均为约20μm。在某些实施例中，封装基板中采用排列方式为3×3的9个穿透硅插塞结构C3，以覆盖1×1mm2的半导体芯片的所有面积。如图24B所示的某些实施例中，封装基板460”中穿透硅插塞结构C3的排列方式可覆盖1×1mm2的半导体芯片。
在图20A、图20B、图21A、图23B、图23D、图23E、图23F、及图24B中，双面梳结构的穿透硅插塞依序排列，且平行排列的穿透硅插塞结构的梳齿互相对准。如图25A所示的某些实施例中，平行排列的穿透硅插塞结构的梳齿可彼此交错。在图25A中，梳状物S1与S2的梳齿并未互相对准，而是互相交错。图25B为图25A的区域P的放大图，显示梳状物S1的梳齿T1与梳状物S2的梳齿T2并非位于相同水平线上。如前述的某些实施例中，梳齿的第一宽度S3与第二宽度S4大致相同。如图20A、图20B、图21A、图23B、图23D、图23E、图23F、及图24B所示的某些实施例中，两个分开的梳状物的间距S5与梳齿的第一宽度S3及第二宽度S4大致相同。梳状物之间需有足够间距，才能提供穿透硅插塞足够的结构支撑力。然而梳状物S1与S2彼此交错，两相邻的梳状物的梳齿间距S6约为1.4倍的S5。若S6、S3、及S4相等，S5可小于S3与S4，且S5约为0.71倍的S3(或S4)。当S5小于S3或S4时，梳状物的排列可更紧密。当梳状物之间的间距缩小，可增加封装基板的负载比。
虽然具有穿透硅插塞的封装基板需大于半导体芯片以增加其负载比至50％以上，穿透硅插塞结构所占的空间最好不要增加封装半导体芯片的基板面积。为了增加封装尺寸，较大的穿透硅插塞面积也需较多金属填入穿透硅插塞结构，即增加工艺成本。在某些实施例中，duty率(负载比)最好能控制在小于或等于65％。
如上所述，用于半导体芯片(如LED芯片)的封装基板，其决定散热量的duty率越高越好。但有时duty率小于50％(比如20％至30％)即足以用于半导体芯片散热。在某些实施例中，穿透硅插塞的duty率大于或等于30％。综上所述，Duty率取决于被封装的半导体芯片种类。
如上所述的某些实施例中，半导体芯片可为LED芯片。LED芯片可含有多种LED。单一LED可发红光、黄光、或蓝光。为了发出白光，可组合一组或多组三个上述的LED。
上述图示及描述的穿透硅插塞结构与图案仅用以举例。穿透硅通孔或穿透硅插塞的形状、图案、与排列也可为其他未提及于上述段落图示的变化。具有上述不同图案的穿透硅插塞可位于一或多个案半导体芯片下以增加散热性，而穿透硅插塞可依工艺考量如铜电镀时间或结构强度制备。
上述具有穿透硅插塞(或通孔)的封装基板，可提供需要热管理的半导体芯片水平与垂直的散热途径。具有高负载比的穿透硅插塞设计可有效提供散热途径。当穿透硅插塞采用双面梳设计时，将具有高负载比如大于或等于50％。具有高负载比的封装基板，可应用于产生大量热的半导体芯片如LED芯片。
在一实施例中，具有穿透硅插塞的半导体封装基板可用以封装半导体芯片以帮助其散热。半导体封装基板含有基板与位于其上的穿透硅插塞，且穿透硅插塞自半导体封装基板的第一表面延伸至相反侧的第二表面。穿透硅插塞的截面图案可为双面梳，且穿透硅插塞可提供半导体芯片散热途径。
在另一实施例中，具有穿透硅插塞的半导体封装基板可用以封装半导体芯片以帮助其散热。半导体封装基板含有基板与位于其上的穿透硅插塞，且穿透硅插塞自半导体封装基板的第一表面延伸至相反侧的第二表面。穿透硅插塞的duty率大于或等于约50％。
虽然本发明已以数个较佳实施例揭示如上，然而其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的改变与润饰，因此本发明的保护范围应当视随附的权利要求书所界定的范围为准。

Claims (10)

1.一种半导体封装基板，具有多个穿透硅插塞以散逸被封装的一半导体芯片产生的热，包含：
一基板，具有该些穿透硅插塞于该半导体封装基板上，
其中该些穿透硅插塞自该半导体封装基板的一第一表面延伸至相反侧的一第二表面，其中该些穿透硅插塞的截面形状为双面梳，且其中该些穿透硅插塞提供该半导体芯片多个散热途径。
2.如权利要求1所述的半导体封装基板，其中该些穿透硅插塞的负载比大于或等于约50％。
3.如权利要求1所述的半导体封装基板，其中该半导体芯片为一发光二极管芯片。
4.如权利要求1所述的半导体封装基板，其中每一该些双面梳的长度介于约100μm至约300μm之间，且每一该些双面梳的宽度介于约100μm至约300μm之间。
5.如权利要求3所述的半导体封装基板，其中该些穿透硅插塞的截面积，大于该发光二极管芯片对应该半导体封装基板的表面的面积。
6.如权利要求3所述的半导体封装基板，其中该发光二极管芯片与该些穿透硅插塞之间夹设一金属层，且其中该金属层提供该发光二极管芯片多个水平方向的散热途径。
7.如权利要求1所述的半导体封装基板，其中相邻的两个该双面梳以交错方式排列。
8.一种半导体封装基板，具有多个穿透硅插塞以散逸被封装的一半导体芯片产生的热，包含：
一基板，具有该些穿透硅插塞于该半导体封装基板上，
其中该些穿透硅插塞自该半导体封装基板的一第一表面延伸至相反侧的一第二表面，且其中该些穿透硅插塞的负载比大于或等于约50％。
9.如权利要求8所述的半导体封装基板，其中该些穿透硅插塞的截面形状为双面梳，且其中该些穿透硅插塞提供该半导体芯片多个散热途径。
10.如权利要求8所述的半导体封装基板，其中该半导体芯片为一发光二极管芯片。
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