CN103367297A - 具有带状打线的封装结构 - Google Patents

具有带状打线的封装结构 Download PDF

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CN103367297A
CN103367297A CN2012100931451A CN201210093145A CN103367297A CN 103367297 A CN103367297 A CN 103367297A CN 2012100931451 A CN2012100931451 A CN 2012100931451A CN 201210093145 A CN201210093145 A CN 201210093145A CN 103367297 A CN103367297 A CN 103367297A
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CN103367297B (zh
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陈逸男
徐文吉
叶绍文
刘献文
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Nanya Technology Corp
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Abstract

本发明公开了一种封装结构，包含有一第一芯片、一第二芯片以及一带状打线，其中带状打线连接第一芯片与第二芯片，且带状打线具有实质上为矩形的剖面。本发明的封装结构能有效解决高频下集肤效应所带来电阻过大的问题。

Description

具有带状打线的封装结构
技术领域
本发明是关于一种封装结构，特别是一种具有带状打线的封装结构，能有效解决高频下集肤效应所带来电阻过大的问题。
背景技术
在现代的资讯社会中，由集成电路(integrated circuit，IC)所构成的微处理系统早已被普遍运用于生活的各个层面，例如自动控制的家电用品、行动通讯设备、个人计算机等，都有集成电路的使用。而随着科技的日益精进，以及人类社会对于电子产品的各种想象，使得集成电路也往更多元、更精密、更小型的方向发展。
一般所称集成电路，是通过现有半导体工艺中所生产的晶粒(die)而形成。制造晶粒的过程，是由生产一晶圆(wafer)开始：首先，在一片晶圆上区分出多个区域，并在每个区域上，通过各种半导体工艺如沉积、光刻、蚀刻或平坦化工艺，以形成各种所需的电路路线，接着，再对晶圆上的各个区域进行切割而成各个晶粒，并加以封装成芯片(chip)，最后再将芯片电连至一电路板，如一印刷电路板(printed circuit board，PCB)，使芯片与印刷电路板的接脚(pin)电性连结后，便可执行各种程式化的处理。
为了提高芯片功能与效能，增加集成度以便在有限空间下能容纳更多半导体元件，相关厂商开发出许多半导体晶片的堆叠技术，包括了覆晶封装(flip-chip)技术、多晶片封装(multi-chip package，MCP)技术、封装堆迭(packageon package，PoP)技术、封装内藏封装体(package in package，PiP)技术等，都可以通过晶片或封装体间彼此的堆叠来增加单位体积内半导体元件的集成度。
在公知的技术中，现有的电子元件，特别是在高频的电子元件中有种称为集肤效应(skin effect)的问题。集肤效应是指在高频时导线中的电流密度会集中向导体的表面，造成于电流的分部不均并使得导体的阻抗变高，这也会造成传输过程中电压衰减以及讯号上升时间拉长。集肤效应会使得高密度封装存储器在高频的效能时会有讯号发生错误的问题。
因此，还需要一种设计良好的存储器封装结构，特别是在高频设计的存储器封装结构，考量到了集肤效应的影响，并具有相对应的结构设计。
发明内容
本发明于是提供了一种封装结构，特别是一种具有带状打线的封装结构，能有效公知技艺中解决高频下集肤效应所带来电阻过大的问题。
根据本发明的一个实施例，本发明提供了一种封装结构，包含有一第一芯片、一第二芯片以及一带状打线，其中带状打线连接第一芯片与第二芯片，且带状打线具有实质上为矩形的剖面。
根据本发明的另一个实施例，本发明提供了一种封装结构，包含有一第一芯片、一第二芯片、以及接触垫。第一穿硅通孔通过接触垫与第二穿硅通孔电性连接，且第一穿硅通孔与第一穿硅通孔的剖面实质上为矩形。
本发明由于考量到了高频情况下集肤效应的影响，以导线在运作下实质的截面积作为判断的标准，故采用了矩形剖面的打线，可以增加导线实质上的导通电流，进而降低阻抗。
附图说明
图1与图2所示为现有金导线与考量到集肤效应的金导线的示意图。
图3与图4为本发明带状打线与考量到集肤效应的带状导线的示意图。
图5所示为本发明的一个实施例中具有带状打线的封装结构示意图。
图6所示为本发明另一个实施例中具有带状穿硅通孔的封装结构示意图。
其中，附图标记说明如下：
100    圆形打线            400    封装结构
300    带状打线            402    第一芯片
302    封装结构            404    第二芯片
304    第一芯片            406    第一穿硅通孔
306    第二芯片            408    第二穿硅通孔
308    第一接触垫          410    接触垫
310    第二接触垫
具体实施方式
为使本发明所属技术领域的技术人员能进一步了解本发明，以下的说明举出了本发明几个优选实施方式，并配合附图与说明，以详细说明本发明的内容及所欲实现的效果。
在现有的技术中，我们可以知道导线的电阻与导线的截面积息息相关。请参考式(1)，
R = ρ L A - - - ( 1 )
其中R为电阻，ρ是指导体的电阻率，L表示导线长度，A表示导线的截面积。根据式(1)，我们可以知道导线的截面积越大，会使得导线的电阻越小，即R与A成反比。
然而，如上文的描述，在现有的电子元件中，特别是高频的电子元件中，会存在着集肤效应的问题。集肤效应会使导体真正导通的区域集中在导体的表面，而使得导体的导通的实质截面积并不等于导体的截面积。在集肤效应的影响下，我们还必须考虑到导体导通的实质截面积。
请参考下式(2)，
δ s = ρ πμf - - - ( 2 )
其中δs是指集肤深度(skin depth)，是指电流密度降低为导体表面的1/e(约37％)时的深度；ρ是指导体的电阻率；μ是指电磁率；f是指频率。由式(2)可以知道，频率f越大，集肤深度越小，意即在高频的时候，电流更会集中在导体表面，使得集肤效应会越发明显。举例而言，当频率f约等于10GHZ时，δs(铝)约为0.81毫米(μm)；δs(铜)约为0.66毫米；δs(金)约为0.79毫米；δs(银)约为0.64毫米。
因此，若考虑到集肤效应的影响，可以知道导线的实质面积会变小，因此导线的设计相对也必须一起改变。请参考图1与图2，图1与图2所示为现有金导线与考量到集肤效应的金导线的示意图。如图1所示，现有使用在存储器封装结构中的打线，例如是圆形打线100，其材质例如是金，其大概具有25.4毫米的直径，其面积大概为506.45平方毫米。然而根据前文的计算，在高频的情况下，例如是10GHZ的情况下，集肤深度约为0.79毫米。如图2所示，电流会大多数聚集在圆形打线100表面以下0.79毫米的地方，也就是斜线部位的区域，此区域的面积大约为61.05平方毫米。因此，在高频的情况下，导线的导通面积从506.45平方毫米下降至61.05平方毫米，因此可以了解到集肤效应在高频运作的元件中影响的严重性。
因此，本发明提出了一种打线的结构，可以降低集肤效应的影响。请参考图3与图4，图3与图4为本发明带状打线与考量到集肤效应的带状打线的示意图。如图3所示，本发明所提出的带状打线(tape bonding)300大体上具有矩形的截面，其长宽比例约为1比4，例如长为50.8毫米，而宽为12.7毫米，而具有645.16平方毫米的截面积为。而在集肤效应的影响下，如图4所示，电流在高频情况下，例如是10GHZ的情况下，电流会大多数聚集在带状打线300表面以下0.79毫米的地方，也就是斜线部位的区域，此区域的面积大约97.84平方毫米。
由上文描述可以知道，虽然本发明所提出的带状打线300，其表面积相较公知的圆形打线100多出了138.45平方毫米，但是在高频的情况下，其打线实质的面积会从圆形打线100的61.05平方毫米，增加为97.84平方毫米，面积增进效益为60.2％。因此，本发明所提供的带状打线300，可以有效降低电子元件在高频情况下集肤效应的影响。
请参考图5，所示为本发明应用带状打线的封装结构示意图。如图5所示，封装结构302包含有一第一芯片304与一第二芯片306，其中第一芯片304上具有一第一接触垫310，第二芯片308上具有一第二接触垫308，其中，第一接触垫310与第二接触垫308可以通过本发明所提供的带状打线300所电性连接，而完成了封装结构302的立体堆迭结构。于本发明其他实施例中，除了带状打线300具有类似于矩形的剖面外，其他的电路连接装置，例如是第一接触垫310或是第二接触垫310也可以具有矩形的剖面。
此外，本发明的带状打线亦可以应用于其余的封装结构，例如具有矩形剖面的穿硅通孔(through silicon via，TSV)等结构。如图6所示，封装结构400包含第一芯片402与第二芯片404，其中第一芯片402具有一第一穿硅通孔406，第二芯片404具有一第二穿硅通孔408，而第一穿硅通孔406与第二穿硅通孔408则通过接触垫410，例如是锡垫，彼此电性连接，以形成一封装结构。于本发明的优选实施例中，第一穿硅通孔406与第二穿硅通孔408具有例如是矩形的剖面，且其长宽比例如是1∶4。
本发明由于考量到了高频情况下集肤效应的影响，以导线在运作下实质的截面积作为判断的标准，故采用了矩形剖面的打线，可以增加导线实质上的导通电流，进而降低阻抗。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种封装结构，其特征在于，包括：
一第一芯片；
一第二芯片；及
一带状打线连接所述第一芯片与所述第二芯片，其中所述带状打线具有实质上为矩形的剖面。
2.根据权利要求1所述的封装结构，其特征在于所述第一芯片具有一第一接触垫，所述第二芯片具有一第二接触垫，且所述第一接触垫通过所述带状打线与所述第二接触垫电性连接。
3.根据权利要求1所述的封装结构，其特征在于所述带状打线的矩形的剖面长宽比为1∶4。
4.根据权利要求1所述的封装结构，其特征在于所述带状打线包含金。
5.根据权利要求1所述的封装结构，其特征在于所述封装结构是在一高频情况下运作。
6.根据权利要求5所述的封装结构，其特征在于所述高频情况是频率大于10GHZ。
7.一种封装结构，其特征在于，包括：
一第一芯片，具有一第一穿硅通孔；
一第二芯片，具有一第二穿硅通孔；及
接触垫，其中第一穿硅通孔通过所述接触垫与所述第二穿硅通孔电性连接，且所述第一穿硅通孔与所述第二穿硅通孔的剖面实质上为矩形。
8.根据权利要求7所述的封装结构，其特征在于所述带状打线的矩形的长宽比为1∶4。
9.根据权利要求7所述的封装结构，其特征在于所述封装结构是在一高频情况下运作。
10.根据权利要求9所述的封装结构，其特征在于所述高频情况是频率大于10GHZ。
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CN105895606A (zh) * 2014-12-29 2016-08-24 飞思卡尔半导体公司 具有带状线的封装半导体器件

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