CN110581121A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN110581121A
CN110581121A CN201910499196.6A CN201910499196A CN110581121A CN 110581121 A CN110581121 A CN 110581121A CN 201910499196 A CN201910499196 A CN 201910499196A CN 110581121 A CN110581121 A CN 110581121A
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CN
China
Prior art keywords
semiconductor
semiconductor package
package
semiconductor chip
chip
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CN201910499196.6A
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English (en)
Inventor
金吉洙
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN110581121A publication Critical patent/CN110581121A/zh
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Abstract

一种半导体封装包括：第一半导体封装；所述第一半导体封装上的第二半导体封装；以及所述第一半导体封装与所述第二半导体封装之间的多个连接端子。第一半导体封装可以包括：封装衬底；半导体芯片，位于所述封装衬底上并且具有彼此面对的第一表面和第二表面，所述第一表面邻近所述第二半导体封装；多个连接焊盘，位于所述半导体芯片的第一表面与所述连接端子之间；以及模制层，位于所述封装衬底上并且覆盖所述半导体芯片的侧表面，所述模制层与所述连接端子间隔开。

Description

半导体封装
相关申请的交叉引用
于2018年6月11日在韩国知识产权局提交的标题为“Semiconductor Package”的韩国专利申请No.10-2018-0066715通过引用整体并入本文中。
技术领域
实施例涉及一种半导体封装。
背景技术
半导体器件由于其尺寸小、多功能性和/或制造成本低而广泛用于电子工业。半导体器件可以包括用于存储数据的存储器器件、用于处理数据的逻辑器件以及用于同时执行各种功能的混合器件。
随着电子工业的先进发展，半导体器件越来越需要高集成度。随着电子工业的先进发展，半导体器件越来越需要高速度。
发明内容
实施例涉及一种半导体封装，包括：第一半导体封装；所述第一半导体封装上的第二半导体封装；以及所述第一半导体封装与所述第二半导体封装之间的多个连接端子。第一半导体封装可以包括：封装衬底；半导体芯片，位于所述封装衬底上并且具有彼此面对的第一表面和第二表面，所述第一表面邻近所述第二半导体封装；多个连接焊盘，位于所述半导体芯片的第一表面与所述连接端子之间；以及模制层，位于所述封装衬底上并且覆盖所述半导体芯片的侧表面，所述模制层与所述连接端子间隔开。
实施例还涉及一种半导体封装，包括：第一半导体封装；所述第一半导体封装上的第二半导体封装；以及所述第一半导体封装与所述第二半导体封装之间的多个连接端子。第一半导体封装可以包括：封装衬底；半导体芯片，位于所述封装衬底上，并且具有彼此面对的第一表面和第二表面；多个芯片端子，位于所述封装衬底与所述半导体芯片的第二表面之间；以及多个连接焊盘，位于所述半导体芯片的第一表面与所述连接端子之间。所述半导体芯片可以包括：第一部分，所述连接焊盘设置在所述第一部分上；以及第二部分，位于所述第一部分与所述半导体芯片的侧表面之间，所述半导体芯片的所述第二部分从所述半导体芯片的所述第一部分的第一表面凹进。
附图说明
通过参考附图详细描述示例实施例，特征对于本领域技术人员将变得显而易见，在附图中：
图1示出了示出根据示例实施例的第一半导体封装的平面图。
图2示出了示出根据示例实施例的半导体封装的横截面图。
图3示出了示出根据示例实施例的半导体封装的横截面图。
图4示出了示出根据示例实施例的半导体封装的横截面图。
图5示出了部分示出根据示例实施例的芯片衬底的平面图。
图6至图10示出了示出根据示例实施例的制造半导体封装的方法的横截面图。
具体实施方式
图1示出了示出根据示例实施例的第一半导体封装的平面图。图2示出了示出根据示例实施例的半导体封装的横截面图。
参考图1和图2，半导体封装1可以包括第一半导体封装100、第一半导体封装100上的第二半导体封装200、以及第一半导体封装100和第二半导体封装200之间的连接端子300。第一半导体封装100和第二半导体封装200可以彼此竖直堆叠。
第一半导体封装100可以包括第一封装衬底101、第一半导体芯片111、芯片端子131、连接焊盘151、接合焊盘153、连接图案155、第一接合线161和第一模制层171。
第一半导体芯片111可以设置在第一封装衬底101上。第一封装衬底101可以是或包括例如印刷电路板(PCB)。
第一封装衬底101可以包括第一焊盘103。第一焊盘103可以用于例如线接合。第一焊盘103可以设置在第一封装衬底101的顶表面上。第一焊盘103可以设置在第一封装衬底101的相对边缘的顶表面上。当在平面中观察时，如图1所示，第一焊盘103可以跨第一半导体芯片111在第一方向X上彼此面对。例如，第一封装衬底101可以具有彼此面对的第一侧表面101a和第二侧表面101b，并且与第一侧表面101a相邻的第一焊盘103和与第二侧表面101b相邻的第一焊盘103可以在第一方向X上彼此面对。第一焊盘103可以在与第一方向X交叉的第二方向Y上线性排列。在另一实现中，第一焊盘103可以设置在第一封装衬底101的周边的顶表面上。例如，在第一封装衬底101的顶表面上，第一焊盘103可以沿第一封装衬底101的四个侧表面布置。
外部端子109可以设置在第一封装衬底101的底表面上，该底表面与第一封装衬底101的顶表面相对。外部端子109可以将第一封装衬底101电连接至外部装置。外部端子109可以包括例如焊料凸块或焊球。
其上具有第一半导体芯片111的第一封装衬底101的顶表面可以具有暴露的第一焊盘103。第一半导体芯片111可以具有第一表面113和与第一表面113相对的第二表面115。第一表面113可以与第二半导体封装200相邻，并且第二表面115可以与第一封装衬底101相邻。
在示例实施例中，第一半导体芯片111的第一表面113可以是非有源表面，并且第一半导体芯片111的第二表面115可以是有源表面。有源表面可以是在其上设置有连接端子(例如，焊球或接合线)的表面，该连接端子将第一半导体芯片111连接至第一封装衬底101。
第一半导体芯片111可以具有第一侧表面121和与第一侧表面121相对的第二侧表面123。第一半导体芯片111的第一侧表面121和第一封装衬底101的第一侧表面101a可以彼此相邻并且彼此平行。第一半导体芯片111的第二侧表面123和第一封装衬底101的第二侧表面101b可以彼此相邻并且彼此平行。
第一半导体芯片111可以包括半导体层117和集成电路结构119。半导体层117可以设置在集成电路结构119的顶表面处。第一半导体芯片111的第一表面113可以对应于半导体层117的顶表面，并且第一半导体芯片111的第二表面115可以对应于集成电路结构119的底表面。半导体层117可以是或包括例如硅层。集成电路结构119可以包括堆叠在半导体层117的底表面上的绝缘层，该底表面与半导体层117的顶表面相对，并且集成电路结构119还可以包括设置在半导体层117的底表面上的至少一个晶体管。至少一个晶体管可以是控制电路和/或电源电路的组成部分。在示例实施例中，第一半导体芯片111可以是半导体逻辑芯片。
第一半导体芯片111可以包括第一部分PA1、第一部分PA1的一侧上的第二部分PA2、以及在第一部分PAl的相对侧上的第三部分PA3，并且第一部分PA1可以在第二部分PA2和第三部分PA3之间。第二部分PA2可以在第一半导体芯片111的第一侧表面121和第一部分PA1的侧壁之间。第三部分PA3可以在第一半导体芯片111的第二侧表面123和第一部分PA1的相对侧壁之间。第二部分PA2和第三部分PA3可以从第一部分PA1的第一表面113凹进。例如，相对于第一半导体芯片111的第二表面115，第二部分PA2和第三部分PA3中的每一个的第一表面113可以比第一部分PA1的第一表面113更靠近第一半导体芯片111的第二表面115。
芯片端子131可以设置在第一封装衬底101和第一半导体芯片111的第二表面115之间。芯片端子131可以电连接至半导体层117的底表面上的至少一个晶体管。芯片端子131可以将第一半导体芯片111连接至第一封装衬底101。例如，芯片端子131可以将第一半导体芯片111连接至外部端子109。芯片端子131可以是或包括例如焊球。
连接焊盘151可以设置在第一半导体芯片111的第一表面113上。例如，连接焊盘151可以设置在第一半导体芯片111的第一部分PA1的第一表面113上。连接焊盘151可以在第一方向X和第二方向Y上彼此间隔开。
接合焊盘153可以设置在第一半导体芯片111的第二部分PA2和第三部分PA3中的每一个的第一表面113上。接合焊盘153可以在第二方向Y上线性布置。在另一实现中，接合焊盘153可以沿着第一半导体芯片111的周边设置在第一表面113上。
第一绝缘层154可以设置在第一半导体芯片111的第一表面113上。第一绝缘层154可以暴露连接焊盘151和接合焊盘153。第一绝缘层154可以由单个层或多个层形成。第一绝缘层154可以包括例如氧化硅层、氮化硅层和氧氮化硅层中的一种或多种。
连接图案155可以设置在第一半导体芯片111的第一表面113上。例如，连接图案155可以设置在第一绝缘层154上。连接图案155可以彼此间隔开。连接图案155可以设置为对应于连接焊盘151，并且可以朝向接合焊盘153延伸。例如，连接图案155可以具有与连接焊盘151中的一个接触的一端和与连接焊盘153中的一个接触的另一端，并且一个连接图案155可以将一个连接焊盘151电连接至一个接合焊盘153。每个连接图案155可以包括单个金属层或多个金属层。每个连接图案155可以包括例如铝(Al)、镍(Ni)和铜(Cu)中的一种或多种。
第二绝缘层156可以设置在第一绝缘层154上。第二绝缘层156可以覆盖设置在第一绝缘层154上的连接图案155。第二绝缘层156可以暴露连接焊盘151和接合焊盘153。第二绝缘层156可以由单个层或多个层形成。第二绝缘层156可以包括例如氧化硅层、氮化硅层和氧氮化硅层中的一种或多种。
第一接合线161可以设置在第一封装衬底101和第一半导体芯片111的第一表面113之间。第一接合线161可以设置在第一半导体芯片111的第二部分PA2和第三部分PA3上。第一接合线161可以沿第二方向Y布置。每个第一接合线161可以设置在一个接合焊盘153和一个第一焊盘103之间。第一接合线161可以将接合焊盘153电连接至第一焊盘103。第一接合线161可以通过接合焊盘153和连接图案155连接至连接焊盘151。
第一模制层171可以设置在第一封装衬底101上。第一模制层171可以填充第一封装衬底101和第一半导体芯片111的第二表面115之间的空间。第一模制层171可以覆盖第一接合线161和第一半导体芯片111的侧表面。第一模制层171可以具有与第二绝缘层156的顶表面共面的顶表面。第一模制层171可以与第一半导体芯片111的第二部分PA2和第三部分PA3竖直地重叠，并且可以在第一半导体芯片111的第一表面113处不与第一半导体芯片111的第一部分PA1竖直地重叠。第一模制层171可以是或包括例如环氧模制料(EMC)。
第二半导体封装200可以设置在第一半导体封装100上。第二半导体封装200可以竖直堆叠在第一半导体封装100上。第二半导体封装200可以包括第二封装衬底201、一个或多个第二半导体芯片211、第二接合线221和第二模制层231。
第二封装衬底201可以设置在第一半导体封装100上。第二封装衬底201可以是或包括例如印刷电路板(PCB)。多个第二半导体芯片211可以顺序堆叠在第二封装衬底201的顶表面上。粘合剂层213可以用于将第二半导体芯片211附接到第二封装衬底201的顶表面。第二接合线221可以设置在第二封装衬底201和第二半导体芯片211之间。第二接合线221可以将第二半导体芯片211电连接至第二封装衬底201。
第二模制层231可以设置在第二封装衬底201上。第二模制层231可以覆盖第二半导体芯片211和第二接合线221。第二模制层231可以是或包括例如环氧模制料(EMC)。在示例实施例中，第二半导体封装200的宽度W2可以小于第一半导体封装100的宽度W1(W2＜W1)。
连接端子300可以设置在第一半导体封装100和第二半导体封装200之间。连接端子300可以设置在连接焊盘151和第二封装衬底201的底表面之间，该底表面与第二封装衬底201的顶表面相对。连接端子300可以与第一模制层171间隔开。连接端子300可以与连接焊盘151接触并连接至连接焊盘151。例如，第二半导体芯片211可以通过连接端子300、连接焊盘151、连接图案155、第一接合线161和第一封装衬底101连接至第一半导体芯片111和/或外部端子109。
根据示例实施例，连接端子300可以设置在连接焊盘151上，连接焊盘151设置在第一表面113上，第一表面113用作第一半导体芯片111的非有源表面，并且第一半导体封装100和第二半导体封装200可以通过连接端子300和连接焊盘151彼此连接，其中在第一半导体封装100和第二半导体封装200之间没有任何结构。因此，可以增加第一半导体芯片111的厚度，并且第一半导体封装100可以具有改善的热辐射。
在示例实施例中，第二半导体封装200可以通过连接端子300、连接焊盘151、连接图案155和第一接合线161连接至第一半导体封装100，使得可以设置多个信号端子(例如，接合线)而不增加第一半导体封装100的宽度。
图3示出了示出根据示例实施例的半导体封装的横截面图。在下面的实施例中，为了简化描述，省略了与上面参考图1和图2讨论的半导体封装的技术特征重复的技术特征。
参考图3，无源器件400或多个无源器件400可以设置在第一封装衬底101的顶表面上。无源器件400可以连接至设置在第一封装衬底101的顶表面上的第二焊盘104。无源器件400可以包括选自电阻器、电容器、电感器、热敏电阻器、振荡器、铁氧体磁珠、天线、变阻器、晶体振荡器(X-TAL)或其他无源器件中的一个或多个。无源器件400可以例如用于过滤信号噪声和/或增加诸如第一半导体芯片111的有源器件的信号处理速度。在示例实施例中，第一接合线161可以帮助确保用于第一封装衬底101的边缘的空间。无源器件400可以设置在第一封装衬底101的边缘上的所确保空间上，这可以引起半导体封装1的电特性的改善。
第一模制层171可以设置在第一封装衬底101的顶表面上，并且可以覆盖无源器件400、第一接合线161和第一半导体芯片111的侧表面。如上所述，第一模制层171可以与第一半导体芯片111的第二部分PA2和第三部分PA3竖直地重叠，并且可以在第一半导体芯片111的第一表面113处不与第一半导体芯片111的第一部分PA1竖直地重叠。第一模制层171可以与连接端子300间隔开。在示例实施例中，第一模制层171的顶表面可以位于比第二绝缘层156的顶表面的高度更高的高度处。在示例实施例中，当在第一半导体封装100和第二半导体封装200之间充分提供空间时，第一半导体芯片111的第二部分PA2和第三部分PA3可以不从第一半导体芯片111的第一部分PA1的第一表面113凹进。在这种情况下，第一半导体芯片111的第一部分PA1的第一表面113可以与第一半导体芯片111的第二部分PA2和第三部分PA3中的每一个的第一表面113共面。
图4示出了示出根据示例实施例的半导体封装的横截面图。在下面的描述中，为了简洁起见，可以省略上面参考图1、图2和图3讨论的技术特征的描述。
参考图4，根据示例实施例，第一半导体封装100的宽度W1可以与第二半导体封装200的宽度W2相同(W1＝W2)。
图5示出了部分示出根据示例实施例的芯片衬底的平面图。图6至图10示出了示出根据示例实施例的制造半导体封装的方法的横截面图。
参考图5和图6，可以没置芯片衬底11。芯片衬底11可以包括器件区DR、和器件区DR之间的划线区SR。划线区SR可以包括在第一方向X上延伸的第一区段RG1、和在与第一方向X交叉的第二方向Y上延伸的第二区段RG2。可以在后续过程中沿划线区SR切割芯片衬底11。当切割芯片衬底11时，每个器件区DR可以用作半导体芯片。划线区SR的每个第二区段RG2可以具有宽度W4。划线区SR的每个第一区段RG1可以具有与宽度W4相同或相似的宽度。
芯片衬底11可以包括半导体层117和集成电路结构119。半导体层117可以是或包括晶片或裸晶片。半导体层117可以是例如硅衬底、锗衬底或硅锗衬底。集成电路结构119可以设置在半导体层117的底表面处。集成电路结构119可以包括堆叠在半导体层117的底表面上的电介质层，并且可以包括设置在半导体层117的底表面上的至少一个晶体管。在示例实施例中，芯片衬底11可以具有彼此面对的第一表面113和第二表面115。芯片衬底11的第一表面113可以对应于半导体层117的顶表面，并且芯片衬底11的第二表面115可以对应于集成电路结构119的底表面。第一表面113可以对应于芯片衬底11的非有源表面，并且第二表面115可以对应于芯片衬底11的有源表面。
芯片端子131可以形成在芯片衬底11的第二表面115上。芯片端子131可以包括例如铜(Cu)、银(Ag)、铂(Pt)和铝(Al)中的一种或多种。例如，芯片端子131可以通过溅射工艺、诸如脉冲镀覆或直流镀覆的镀覆工艺、焊接工艺或附接工艺来形成。支撑构件500可以设置在芯片衬底11的第二表面115上。支撑构件500可以覆盖芯片端子131。支撑构件500可以是或包括处理芯片衬底11的晶片支撑系统。支撑构件500可以包括粘合剂材料，例如，环氧树脂、硅基绝缘层或带。
参考图7，可以在芯片衬底11中形成凹进区域RR。凹进区域RR可以沿着划线区SR的第二区段RG2形成。凹进区域RR可以不形成在划线区SR的第一区段RG1上。凹进区域RR可以具有地板表面，每个地板表面比芯片衬底11的器件区DR的第一表面113更靠近芯片衬底11的第二表面115。凹进区域RR的宽度W3可以大于划线区SR的第二区段RG2或每个第一区段RG1的宽度W4(W3＞W4)。
在凹进区域RR的形成中，可以执行蚀刻工艺，使得芯片衬底11的第一表面113蚀刻在划线区SR的第二区段RG2上。凹进区域RR可以通过例如干法蚀刻工艺或激光蚀刻工艺形成。在一个实现中，蚀刻工艺可以形成凹进区域RR。用于形成凹进区域RR的蚀刻工艺可以蚀刻芯片衬底11的器件区DR的边缘部分，该边缘部分与划线区SR的第二区段RG2相邻。因此，每个凹进区域RR可以朝向器件区域DR的侧面扩展，该侧面邻接凹进区域RR并且在第一方向X上彼此面对。
参考图8，连接焊盘151和接合焊盘153可以形成在芯片衬底11的第一表面113上。连接焊盘151可以形成在芯片衬底11的器件区DR的第一表面113上，并且接合焊盘153可以形成在凹进区域RR的地板表面上(即，在凹进区域RR的第一表面113上)。连接焊盘151和接合焊盘153的形成可以包括：在芯片衬底11的第一表面113上形成金属层，然后图案化金属层。
第一绝缘层154可以形成在芯片衬底11的第一表面113上。第一绝缘层154的形成可以包括：在芯片衬底11的第一表面113上形成绝缘层，然后图案化绝缘层以暴露连接焊盘151和接合焊盘153。第一绝缘层154可以由单个层或多个层形成。第一绝缘层154可以包括例如氧化硅层、氮化硅层和氧氮化硅层中的一种或多种。
连接图案155可以形成在第一绝缘层154上。连接图案155的形成可以包括：在第一绝缘层154上形成金属层，然后图案化金属层。连接图案155可以将连接焊盘151连接至接合焊盘153。每个连接图案155可以由单个层或多个层形成。每个连接图案155可以包括例如铝(A1)、镍(Ni)和铜(Cu)中的一种或多种。
第二绝缘层156可以形成在连接图案155上。第二绝缘层156的形成可以包括：形成绝缘层以覆盖连接图案155和第一绝缘层154，然后图案化绝缘层以暴露连接焊盘151和接合焊盘153。第二绝缘层156可以覆盖第一绝缘层154和连接图案155。第二绝缘层156可以由单个层或多个层形成。第二绝缘层156可以包括例如氧化硅层、氮化硅层和氧氮化硅层中的一种或多种。
参考图9，可以执行切割工艺以切割芯片衬底11。切割工艺可以沿着划线区SR切割芯片衬底11。切割工艺可以依次切割形成在芯片衬底11的划片区SR上的第二绝缘层156、形成在芯片衬底11的划片区SR上的第一绝缘层154、芯片衬底11、和形成在芯片衬底11的划线区SR上的支撑构件500。切割工艺可以将芯片衬底11分离成多个第一半导体芯片111。在示例实施例中，第一半导体芯片111可以是半导体逻辑芯片。
可以在切割工艺之后去除覆盖芯片端子131的支撑构件500。在另一实现中，可以在切割工艺之前移除支撑构件500。
参考图10，可以制备第一封装衬底101。第一封装衬底101可以是或包括例如印刷电路板(PCB)。第一封装衬底101可以包括第一焊盘103，第一焊盘103可以设置在第一封装衬底101的顶表面上。外部端子109可以形成在第一封装衬底101的底表面上，该底表面与第一封装衬底101的顶表面相对。外部端子109可以包括例如焊球或焊料凸块。
第一半导体芯片111中的至少一个可以安装在第一封装衬底101上。芯片端子131可以设置在第一封装衬底101的顶表面上。第一半导体芯片111可以倒装芯片接合到第一封装衬底101。第一接合线161可以形成为位于接合焊盘153和第一焊盘103之间，并且电连接接合焊盘153和第一焊盘103。第一接合线161可以包括例如金(Au)。
第一模制层171可以形成在第一封装衬底101上。第一模制层171的形成可以包括：在第二绝缘层156的顶表面上提供与第一封装衬底101平行的模制框架，然后将模制材料填充到模制框架与第一封装衬底101之间的空间中。第一模制层171可以填充第一封装衬底101和第一半导体芯片111的第二表面115之间的空间，同时覆盖第一接合线161、接合焊盘153、和第一封装衬底101的侧表面。例如，第一模制层171可以具有与第二绝缘层156的顶表面共面的顶表面。又例如，第一模制层171的顶表面可以高于第二绝缘层156的顶表面。第一模制层171可以包括例如绝缘聚合材料，例如环氧模制料。
可以通过上面参考图6至图10讨论的工艺制造第一半导体封装100。下面将描述第二半导体封装的制造(参见图2的200)、以及包括第一半导体封装100和第二半导体封装200的半导体封装(参见图2的1)。
返回参考图2，可以制造第二半导体封装200。第二半导体封装P200可以包括第二封装衬底201、第二半导体芯片211和第二模制层231。第二封装衬底201可以是或包括例如印刷电路板(PCB)。第二半导体芯片211可以安装在第二封装衬底201的顶表面上。粘合剂层213可以用于将第二半导体芯片211附接到第二封装衬底201的顶表面。第二半导体芯片211可以是例如半导体存储器芯片。
第二接合线221可以形成为将第二半导体芯片211连接至第二封装衬底201。第二接合线221可以包括例如金(Au)。第二模制层231可以形成在第二封装衬底201上。第二模制层231可以覆盖第二半导体芯片211、第二接合线221、和第二封装衬底201的顶表面。第二模制层231可包括例如绝缘聚合材料，例如环氧模制料。
连接端子300可以设置在第二封装衬底201的底表面处，该底表面与第二封装衬底201的顶表面相对。连接端子300可以设置在连接焊盘151上。
可以通过在第二封装衬底201的顶表面上执行的焊接工艺来形成连接端子300。在另一实现中，连接端子300可以形成在连接焊盘151上。例如，可以在连接焊盘151上执行用于形成连接端子300的焊接工艺。
第一半导体封装100可以安装在其上形成有连接端子300的第二半导体封装200上。将第二半导体封装200安装在第一半导体封装100上可以制造半导体封装1。半导体封装1可以是封装叠层(POP)类型。
如上所述，实施例涉及具有改善的电特性的半导体封装。
根据示例实施例，竖直堆叠的第一半导体封装和第二半导体封装之间的连接端子可以设置在连接焊盘上，所述连接焊盘设置在第一半导体封装中包括的第一半导体芯片的非有源表面上。第一半导体封装和第二半导体封装可以通过连接端子和连接焊盘彼此连接，而在第一半导体封装和第二半导体封装之间没有任何结构。因此，可以增加第一半导体芯片的厚度，并且第一半导体封装可以提供改善的热辐射。
根据示例实施例，第二半导体封装可以通过连接端子、连接焊盘、和第一封装衬底与第一半导体芯片的非有源表面之间的接合线而连接至第一半导体封装。因此，可以在不增加第一半导体封装的宽度的情况下提供多个信号端子(例如，接合线)，结果，可以改善半导体封装的电特性。
本文已经公开了示例实施例，并且尽管采用了特定术语，但是它们仅用于且将被解释为一般的描述性意义，而不是为了限制的目的。在一些情况下，截至本申请递交之时，本领域技术人员清楚，除非另有明确说明，否则结合特定实施例描述的特征、特性和/或元素可以单独使用或与结合其他实施例描述的特征、特性和/或元素相结合。因此，本领域技术人员将理解，在不脱离如所附权利要求中阐述的本发明的精神和范围的前提下，可以进行形式和细节上的各种改变。

Claims (20)

1.一种半导体封装，包括：
第一半导体封装；
所述第一半导体封装上的第二半导体封装；以及
所述第一半导体封装与所述第二半导体封装之间的多个连接端子，其中：
所述第一半导体封装包括：
封装衬底；
半导体芯片，位于所述封装衬底上并且具有彼此面对的第一表面和第二表面，所述第一表面邻近所述第二半导体封装；
多个连接焊盘，位于所述半导体芯片的第一表面与所述连接端子之间；以及
模制层，位于所述封装衬底上并且覆盖所述半导体芯片的侧表面，所述模制层与所述连接端子间隔开。
2.根据权利要求1所述的半导体封装，其中，所述第一半导体封装还包括在所述封装衬底与所述半导体芯片的第二表面之间的多个芯片端子。
3.根据权利要求1所述的半导体封装，其中，所述半导体芯片包括：
第一部分，所述连接焊盘设置在所述第一部分上；以及
第二部分，位于所述第一部分与所述半导体芯片的侧表面之间，所述半导体芯片的所述第二部分从所述半导体芯片的所述第一部分的所述第一表面凹进。
4.根据权利要求3所述的半导体封装，其中，所述第一半导体封装还包括在所述封装衬底与所述半导体芯片的所述第一表面之间的多条接合线，所述接合线设置在所述半导体芯片的所述第二部分上。
5.根据权利要求1所述的半导体封装，其中，所述第一半导体封装还包括在所述封装衬底与所述半导体芯片的所述第一表面之间的多条接合线，所述模制层覆盖所述接合线。
6.根据权利要求1所述的半导体封装，其中，所述连接端子与所述连接焊盘接触。
7.根据权利要求1所述的半导体封装，其中，所述第一半导体封装还包括：
多条接合线，位于所述封装衬底与所述半导体芯片的所述第一表面之间；以及
多个连接图案，位于所述半导体芯片的所述第一表面上，并且将所述连接焊盘连接至所述接合线。
8.根据权利要求1所述的半导体封装，其中，所述第一半导体封装还包括所述封装衬底上的无源器件。
9.根据权利要求1所述的半导体封装，其中，所述第一半导体封装还包括所述半导体芯片的所述第一表面上的绝缘层，所述绝缘层暴露所述连接焊盘，所述模制层的顶表面与所述绝缘层的顶表面共面。
10.根据权利要求1所述的半导体封装，其中，所述第一半导体封装还包括所述半导体芯片的所述第一表面上的绝缘层，所述绝缘层暴露所述连接焊盘，所述模制层的顶表面位于比所述绝缘层的顶表面的高度更高的高度处。
11.根据权利要求1所述的半导体封装，其中，所述第二半导体封装的宽度等于或小于所述第一半导体封装的宽度。
12.根据权利要求1所述的半导体封装，其中：
所述半导体芯片的所述第一表面是非有源表面，并且
所述半导体芯片的所述第二表面是有源表面。
13.一种半导体封装，包括：
第一半导体封装；
所述第一半导体封装上的第二半导体封装；以及
所述第一半导体封装与所述第二半导体封装之间的多个连接端子，其中：
所述第一半导体封装包括：
封装衬底；
半导体芯片，位于所述封装衬底上，并且具有彼此面对的第一表面和第二表面；
多个芯片端子，位于所述封装衬底与所述半导体芯片的所述第二表面之间；以及
多个连接焊盘，位于所述半导体芯片的所述第一表面与所述连接端子之间，并且
所述半导体芯片包括：
第一部分，所述连接焊盘设置在所述第一部分上；以及
第二部分，位于所述第一部分与所述半导体芯片的侧表面之间，所述半导体芯片的所述第二部分从所述半导体芯片的所述第一部分的所述第一表面凹进。
14.根据权利要求13所述的半导体封装，其中，所述连接焊盘在彼此交叉的第一方向和第二方向上彼此间隔开。
15.根据权利要求13所述的半导体封装，其中，所述第一半导体封装还包括模制层，所述模制层位于所述封装衬底上并且覆盖所述半导体芯片的侧表面，所述模制层与所述连接端子间隔开。
16.根据权利要求13所述的半导体封装，其中，所述第一半导体封装还包括在所述封装衬底与所述半导体芯片的所述第一表面之间的多条接合线，所述接合线设置在所述半导体芯片的所述第二部分上。
17.根据权利要求13所述的半导体封装，其中：
所述第一半导体封装还包括模制层，所述模制层覆盖所述半导体芯片的侧表面，
所述模制层不与所述第一部分重叠，并且
所述模制层与所述第二部分重叠。
18.根据权利要求13所述的半导体封装，其中，所述第一半导体封装还包括所述半导体芯片的所述第一表面上的多个连接图案，所述连接图案设置为对应于所述连接焊盘。
19.根据权利要求13所述的半导体封装，其中，所述第一半导体封装还包括：
模制层，覆盖所述半导体芯片的侧表面；以及
绝缘层，位于所述半导体芯片的所述第一表面上并且暴露所述连接焊盘，所述模制层的顶表面与所述绝缘层的顶表面共面。
20.根据权利要求13所述的半导体封装，其中：
所述半导体芯片的所述第一表面是非有源表面，并且
所述半导体芯片的所述第二表面是有源表面。
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