CN102214621A - 半导体装置封装体及其制造方法 - Google Patents

半导体装置封装体及其制造方法 Download PDF

Info

Publication number
CN102214621A
CN102214621A CN2011100708971A CN201110070897A CN102214621A CN 102214621 A CN102214621 A CN 102214621A CN 2011100708971 A CN2011100708971 A CN 2011100708971A CN 201110070897 A CN201110070897 A CN 201110070897A CN 102214621 A CN102214621 A CN 102214621A
Authority
CN
China
Prior art keywords
layer
silicon
substrate
wearing
bronze medal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011100708971A
Other languages
English (en)
Other versions
CN102214621B (zh
Inventor
余振华
余佳霖
黄见翎
张宏宾
林咏淇
洪瑞斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Epistar Corp
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102214621A publication Critical patent/CN102214621A/zh
Application granted granted Critical
Publication of CN102214621B publication Critical patent/CN102214621B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0054—Processes for devices with an active region comprising only group IV elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/641—Heat extraction or cooling elements characterized by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/644—Heat extraction or cooling elements in intimate contact or integrated with parts of the device other than the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32505—Material outside the bonding interface, e.g. in the bulk of the layer connector
    • H01L2224/32506—Material outside the bonding interface, e.g. in the bulk of the layer connector comprising an eutectic alloy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48233—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a potential ring of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Led Device Packages (AREA)

Abstract

本发明提供一种半导体装置封装体及其制造方法，其中，具有穿硅插塞(或导孔)的基板可不需使用导电凸块。工艺流程非常简单且有成本效益。本结构将个别的硅穿孔、重分布层及导电凸块结构结合至单一结构中。经由结合个别的结构，可以得到一具有高散热能力的低电阻电性连接。另外，具有穿硅插塞(或导孔，或沟槽)的基板也使得多个芯片可以封装在一起。穿硅沟槽可围绕一个或多个芯片，以在工艺中避免铜扩散到邻近装置。另外，多个具有相似或相异功能的芯片可整合在硅穿孔基板上。具不同图案的穿硅插塞可用在一半导体芯片之下以增进散热及解决工艺问题。

Description

半导体装置封装体及其制造方法
技术领域
本发明涉及一种半导体芯片的封装，特别是涉及一种利用硅穿孔的半导体芯片封装。
背景技术
先进半导体封装的趋势是在增进电性表现的同时降低尺寸因子。如此的趋势使得提供给工业及消费者的产品能更快速、更便宜及更小。硅穿孔(through silicon via，TSV)，或更精确地说，穿硅插塞(through silicon plug，TSP)，为先进半导体封装提供了一个能达到更高集成度及更大幅度尺寸因子降低的方式。由于一半导体装置前面与背面的电性连接，在一封装体中，可有多个芯片被垂直式地组装，不同于以往只能存在一个芯片的情形。因此，更多的半导体装置可被整合成一较小的尺寸因子。除此之外，不同的半导体芯片也可被整合在单个封装体里，成为一系统级封装(system in a package，SIP)。不论方法为何，多重封装体在印刷电路板中的所占体积减少了，因此也减少了最终产品成本。最后，利用硅穿孔内连接芯片可降低至基板所必需的电性连接的数目，因为一基板的连接可用于多个芯片。由此也可简化组装工艺及提高良率。
除此之外，硅穿孔提供了优越的散热机制。使用硅穿孔的封装为一新科技。各界仍在持续改进制造硅穿孔的结构及方法，这也是本公开起源的背景。
发明内容
本发明有关一种半导体装置封装体，包括：一基板，其具有从该基板的一第一表面延伸至与该第一表面相反的一第二表面的多个穿硅插塞，其中一隔离层及一第一铜阻挡层内衬于该一个或多个穿硅插塞的侧壁，且一第一铜层填入所述多个穿硅插塞，其中所述多个穿硅插塞具有第一端及第二端，且其中第二端具有该第一铜层延伸于该基板的第一表面之上，而第一端具有该第一铜层填充至该基板的第二表面；一第二铜层，形成于所述多个穿硅插塞的第一端上，其中该第二铜层定义出一区域以接收一半导体芯片，其中具有一第二铜阻挡层分离所述多个穿硅插塞第一端上的该第一铜层与该第二铜层；及该半导体芯片置于该第二铜层所定义出的区域之上。
本发明也有关一种半导体装置封装体，包括：至少三个发光装置，其中所述多个发光装置发射多于一种波长的光；一基板，具有一个或多个穿硅插塞从该基板的一第一表面延伸至该第一表面对面的一第二表面，其中一隔离层及一第一铜阻挡层内衬于该一个或多个穿硅插塞的侧壁，一第一铜层填入该一个或多个穿硅插塞，其中该一个或多个穿硅插塞具有第一端及第二端，其中所述多个第二端具有该第一铜层延伸于该基板的第一表面之上，而所述多个第一端具有该第一铜层填充至该基板的第二表面；一第二铜层，形成于所述多个穿硅插塞的所述多个第一端之上，其中一第二铜层定义出一区域以接收所述这些至少三个发光装置，其中具有一第二铜阻挡层，将该一个或多个穿硅插塞的第一端上的该第一铜层与该第二铜层分离，其中所述这些至少三个发光装置被放置于由该第二铜层所定义出的区域上；其中所述多个穿硅插塞的其中一者为一沟槽状，环绕所述这些至少三个发光装置及所述多个置于所述这些至少三个发光装置之下的穿硅插塞，其中该沟槽中的该第一阻挡层避免来自被该沟槽环绕的所述多个穿硅插塞的铜扩散。
本发明还有关一种半导体装置封装体的制造方法，包括：提供一第一基板；形成多个穿硅插塞于该第一基板内，所述多个穿硅插塞从该第一基板的一第一表面延伸，其中一隔离层及一第一铜阻挡层内衬于所述多个穿硅插塞，其中一第一铜层填入所述多个穿硅插塞；移除该第一基板上多余的硅，以暴露埋藏于该第一基板中的所述多个穿硅插塞的所述多个第一端；形成一第二铜层于所述多个穿硅插塞的所述多个第一端上，其中在形成该第二铜层之前，沉积一第二铜阻挡层于所述多个穿硅插塞的所述多个第一端；及放置该半导体芯片于所述多个第一端上的第二铜层的表面上。
本发明实施例提供的具有穿硅插塞(或导孔)的基板可不需使用导电凸块。工艺流程非常简单且有成本效益。本结构将个别的硅穿孔、重分布层及导电凸块结构结合至单一结构中。经由结合个别的结构，可以得到一具有高散热能力的低电阻电性连接。另外，具有穿硅插塞(或导孔，或沟槽)的基板也使得多个芯片可以封装在一起。穿硅沟槽可围绕一个或多个芯片，以在工艺中避免铜扩散到邻近装置。另外，多个具有相似或相异功能的芯片可整合在硅穿孔基板上。具不同图案的穿硅插塞可用在一半导体芯片之下以增进散热及解决工艺问题。
附图说明
图1A、图1B、图2～图18说明本发明实施例中形成半导体裸片封装体的工艺流程中的结构及中间工艺。
图19A显示一N接点205环绕三个发光装置芯片的俯视图。
图19B显示经过简化的图19A的剖面图。
图20A显示三个发光装置芯片连接到一P电极的示意图。
图20B显示图20A的剖面图。
图20C显示图19B的剖面图，。
图21显示利用硅穿孔技术封装发光装置芯片的剖面图。
图22A～图22G显示穿硅插塞的各类实施例。
【主要附图标记说明】
100～第一基板
101～介电层
102～光致抗蚀剂层
103～隔离层
104～阻挡/铜籽晶层
105～已图案化的光致抗蚀剂层
106～铜膜
107～胶着层
108～第二基板(虚设基板)
110～开口
120～硅穿孔
140～硅材质
150～介电层
151～光致抗蚀剂层
152～阻挡/铜籽晶层
154～铜层(或金属垫)
155～扩散阻挡层
156～发光装置芯片
157～共晶接合层
158～导线
159～P接点
160～N接点
161～荧光层
162～模封
163～粘着胶带
170～边角
180～封装芯片
190～电路
191～蚀刻阻挡层
192～层间介电层
195～接点
201、202’、202、202’、203、203’、211、212、213～发光装置芯片
204～导线
205、215～N接点
208～导孔
216～铜阻挡层
217～铜
218～硅穿孔
401、402、403、404、405～穿硅插塞
406～硅穿孔
407、408、409、410～穿硅插塞(或硅穿孔)
411～开口
412、413～穿硅插塞
D1～穿硅插塞401的直径
D2～各穿硅插塞的直径
D3～两个穿硅插塞之间的最小距离
D4～406的直径
D6～穿硅插塞(或硅穿孔)407的宽度
L1～408及409的宽度
L2～408及409的长度
L3～穿硅插塞的间距
L4～411的宽度
L5～411的间距
具体实施方式
应能理解的是，本公开提供了为实施本发明不同特征的许多不同的实施例或举例。为简化本公开，以下会叙述特定元件及配置的例子，但仅当作举例而不具有限制性。除此之外，本公开可能在不同的例子里重复元件符号。重复的目的在于简化及说明清楚，并不代表讨论的各实施例及/或结构之间有关系。
图1A～图18显示本公开一些实施例的中间工艺剖面示意图。图1A显示实施例中具有一光致抗蚀剂图案的第一基板100。第一基板100可包括例如硅块材(bulk silicon)、已掺杂、未掺杂，或一半导体覆绝缘体(semiconductor-on-insulator，SOI)的一有源层。通常一SOI基板包括一半导体材质层，例如硅，形成于一绝缘层之上。绝缘层可为，举例来说，一埋藏氧化(buried oxide，BOX)层或一氧化硅(silicon oxide)层。提供绝缘层在一基板上，通常为一硅或玻璃基板。也可为其他材质，例如多层或梯度基板。
在此例中，第一基板100为一硅材质140。沉积一介电层101于硅材质140之上。接着沉积一光致抗蚀剂层102于介电层101之上，且图案化光致抗蚀剂层102使其具有开口，例如硅穿孔的开口。介电层101是作为一牺牲层，以在硅穿孔的蚀刻工艺中保护基板。
在一些实施例中，在沉积及图案化光致抗蚀剂层102之前，第一基板100就已具有一内建电路190，如图1B所示。图1B显示已在第一基板100上形成的一电路190。电路190可为任一种适合一特定应用的电路。在一实施例中，电路包括形成于基板上且具有一个或多个介电层覆于其上的多个电性装置。可在介电层之间形成金属层以在电性装置之间传递电性信号。可形成电性装置于一个或多个介电层中。
举例来说，电路190可包括各样N型金属氧化物半导体及/或P型金属氧化物半导体装置，例如晶体管、电容、电阻、二极管、光电二极管、熔丝及其相似物，上述装置内连接以执行一个或多个功能。这些功能可包括记忆结构，处理结构，感测器，放大器，电力分配，输入/输出电路或相似物。本领域技术人员应可了解的是，上述举例的目的仅为说明用，以说明本发明的应用，且对于本发明不具限制性。只要适合被用在一特定应用中，也可使用其他的电路。
同样显示在图1B的是一蚀刻阻挡层191及一层间介电层(inter-layer dielectric，ILD)192。在一些实施例中，蚀刻阻挡层191最好为一具有与其相邻层不同蚀刻选择率(etch selectivity)的介电材料，也就是说，其下的第一基板100及其上的ILD层192。在一实施例中，蚀刻阻挡层191可为利用化学气相沉积(chemical vapor deposition，CVD)或等离子体增强式化学气相沉积(plasma-enhanced CVD，PECVD)所沉积的SiN、SiCN、SiCO、CN、上述任意组合或其相似物。
可以例如一低介电常数介电材质，例如氧化硅、磷玻(phosphosilicate glass，PSG)、硼磷硅玻璃(borophosphosilicate glass，BPSG)、SiOxCy、旋涂式玻璃、旋涂式聚合物、碳硅材料(carbon silicon)、上述任意组合的化合物、上述任意组合的聚合物、上述任意组合或其相似物，并使用任何现有的方法例如旋转涂布、CVD及PECVD技术形成ILD层192。应注意的是，蚀刻阻挡层191及ILD层192都可各自包括多个介电层，且可具有或不具有一形成于相邻介电层之间的蚀刻阻挡层。
接点195穿过ILD层192形成，以当作提供电性连接至电路190的接点。接点195的形成可利用光刻技术在ILD层192上沉积及图案化一光致抗蚀剂材料，以暴露ILD层192即将形成接点195的部分。可使用一蚀刻工艺，例如一非等向性干蚀刻工艺，以在ILD层192形成多个开口。所述多个开口最好具有一扩散阻挡层及/或一粘着层(未显示)为内衬层，且填入一导电材质。扩散阻挡层最好包括一层或多层的TaN、Ta、TiN、Ti、CoW或其相似物，而导电材质包括铜、钨、铝、银及上述任意组合，或其相似物，由此形成图1B中所示的接点195。
图2显示实施例中蚀刻完开口之后的第一基板100。虽然图2中未显示图1B中的电路190、接触插塞195，及介电层191及192，上述特征可存在于图2中及之后的图。在一实施例中，进行一控制时间的蚀刻工艺，例如一非等向性干蚀刻工艺，直到第一基板100中的开口110达到一想要的深度。应能理解的是，在此叙述的蚀刻工艺可为一次性蚀刻工艺或多次性蚀刻工艺。蚀刻工艺可为一干蚀刻工艺或湿蚀刻工艺。
在一些实施例中，开口的深度可为约20～200微米。在一些实施例中，开口110可为约5～100微米。在一些实施例中，开口100为硅穿孔(或沟槽)。若只借着光致抗蚀剂层102来蚀刻，要达到具有上述深度的开口会较具挑战性。在本实施例中，先蚀刻打开介电层101，并将其用作一图案化掩模。介电层101的材质可为任何介电材质，例如二氧化硅、氮化硅或为上述两个材质的膜的组合。介电层101所属材质的一个例子为通过PECVD所沉积的氧化硅，其中以TEOS(tetraethyl orthosilicate)作为硅来源。也可使用PECVD硅烷氧化物(silane oxide)膜。在一些实施例中，TEOS氧化物的厚度约500～10000埃。不一定需要通过PECVD沉积介电层101。介电层101可为一旋涂式介电质(spin-on dielectric，SOD)或一旋涂式玻璃(spin-on glass，SOG)。也可经由一热工艺来沉积(或生长)介电层101，例如一热生长二氧化硅或一经由热CVD所沉积的氧化膜。
在蚀刻硅穿孔后，移除光致抗蚀剂及牺牲介电层101。在形成开口(例如开口110)之后，进行开口的填充。图3显示先用一隔离层103及一阻挡/铜籽晶层104内衬于基板。隔离层103为一介电材质，例如氧化物、氮化物或上述两者的组合。隔离层103的材质的一个例子为由PECVD，利用硅烷或TEOS所沉积的氧化硅(silicon oxide)。在一些实施例中，隔离层具有约500～15000埃的厚度。可经由一热工艺沉积(或生长)隔离层103，例如一热生长氧化物或一热CVD氧化物。或者，介电隔离层103可为一掺杂层，其中使用例如磷，或硼加上磷的掺质。磷硅玻璃或硼磷硅玻璃中的磷可阻挡用来填入开口中的铜，以避免铜扩散进入基板，在此实施例中，该开口指的是硅穿孔(或沟槽)。虽然硅穿孔内衬有一阻挡层，其会在下面叙述，但在导孔侧壁上且靠近底部(例如边角170)的阻挡范围可能不够大。使用磷硅玻璃或硼磷硅玻璃材质的隔离层103可提供额外的保护避免铜扩散。
介电层比硅具有更高热阻。表I比较了具有不同厚度氧化介电层的硅基板的热阻模拟结果。
  硅/氧化物(μm/μm)   热阻(K/Watt)
  100/0   1.81
  100/1.5   6.37
  50/0   0.92
  50/1.5   5.95
表I：不同硅/氧化物厚度的热阻比较
表I的数据显示氧化物可大幅提高热阻。因此最好将封装体里介电层的厚度降到最低。
在沉积隔离层103之后，沉积一阻挡/铜籽晶层104。阻挡/铜籽晶层104包括至少两个次层、一阻挡层及一铜籽晶层。阻挡层为一个或更多的铜阻挡材质，例如Ta、TaN、Ti、TiN、CoW或其相似物。阻挡层避免铜扩散进入硅基板100。可经由物理气相沉积(physical vapor deposition，PVD)、CVD、原子层沉积(atomic layer deposition，ALD)或其他合适的方法沉积阻挡层。在沉积阻挡层之后，沉积一铜籽晶层。相似地，可经由PVD、CVD、ALD或其他合适的方法沉积铜籽晶层。在一些实施例中，阻挡/铜籽晶层104为TaN/Ta阻挡及一铜籽晶层。本实施例中的阻挡层104为两个次层，一TaN层及一Ta层。在一些实施例中，TaN、Ta、Cu籽晶全都是经由PVD沉积，并且都是以不同的标靶及溅镀气体在单个PVD室(chamber)完成。在一些实施例中，每个TaN及Ta的厚度都约为100～2000埃，而铜籽晶的厚度约为1000～15000埃。
在沉积阻挡/铜籽晶层104之后，图案化基板以定义出即将接收镀铜的不同的区域。图4显示一已图案化的光致抗蚀剂层105形成于第一基板100上方。在一些实施例中，已图案化的光致抗蚀剂层105为传统的光致抗蚀剂材质，其为液状且经由一旋转涂布工艺沉积。在另一实施例中，已图案化的光致抗蚀剂层105为一干膜光致抗蚀剂(dry film resist，DFR)，其可利用光刻达成图案化(也就是有曝光)。DFR可为一正光致抗蚀剂或负光致抗蚀剂。一直以来，DFR被用在电路板的铜电镀中以建立图案。DFR的一例子为日本的TOK CO.LTD.所制造的MP112。在DFR被层叠在第一基板100上方(或在层104上)之后，曝光DFR，且在曝光时使用一图案，其定义出即将被镀铜的不同的区域。比起使用湿式旋转涂布光致抗蚀剂，使用干膜光致抗蚀剂的优点是干膜光致抗蚀剂只层叠在基板表面。相反地，湿式旋转涂布光致抗蚀剂会流入开口，例如开口110。因为硅穿孔的开口较深，为上述的约20～200微米之间，所以较难完全移除填入内部的湿式旋转涂布光致抗蚀剂，使得铜不能被正确地镀在开口的侧壁及底部。
图5显示一铜膜106被镀在第一基板100，及DRF在电镀之后从基板表面被剥除。可使用于半导体装置工艺中用来制作金属内连线的电镀铜(electrical copper plating，ECP)工艺或无电镀铜工艺。在一些实施例中，铜膜106的厚度小于约40微米。在其他实施例中，铜膜106的厚度小于约30微米。在其他一些实施例中，铜膜106的厚度小于约25微米。一过厚的铜膜可造成基板翘曲。在一些实施例中，沉积铜层106的目的仅为填入开口(或硅穿孔)，例如图4所示的开口110。在另一实施例中，沉积铜膜106的目的不仅为了填入(硅穿孔)开口，也为已完成封装的装置在一基板上提供接着垫(landing pads)，例如一印刷电路板，或是用以接收半导体芯片。
在一些实施例中，膜106的厚度为约10～30微米。在电镀铜膜106之后，移除光致抗蚀剂层105。可经由灰化工艺移除湿式旋转涂布光致抗蚀剂及干膜光致抗蚀剂，而通常会在移除光致抗蚀剂之后实施一湿式清洁工艺以完全去除基板表面的杂质。
在电镀铜及移除光致抗蚀剂后，移除未接受电镀的区域中的阻挡/铜籽晶层104，如图6所示。用来移除为TaN、Ta、Ti、TiN、CoW或上述任意组合的膜材质的阻挡层的工艺皆为业界所知。用来移除介电隔离层103的(多个)工艺亦然。在实施上述操作之后，将基板的前端胶着至一第二基板108。第二基板108为一虚设基板，且可为一介电材质例如玻璃。或者，第二基板108可为一导电材质，例如金属。图7显示基板100通过一胶着层107被胶着至第二基板108。当不需要虚设基板108时，胶着层107的材质应可被轻易移除。在一些实施例中，胶着层107的材质为一环氧树脂聚合物。先将液态胶着层107涂布于第一基板100上。在第二基板108被放置于胶着层107上之后，可让热胶着层自行干燥或低温加热。在干燥及加热(或固化)后，基板100被紧实地胶着至虚设基板108。
之后，晶背研磨第一基板100以移除多余的硅及暴露硅穿孔120。在一些实施例中，会在晶背研磨之后实施一化学机械抛光(chemical mechanical polish，CMP)工艺以平坦化被研磨的基板表面。图8显示移除背面的硅以暴露硅导孔120之后的第一基板100。在一些实施例中，硅移除工艺为一研磨工艺，封装工艺中经常使用研磨轮以移除硅基板上多余的硅。持续实施研磨直到硅穿孔120底部的隔离层103及阻挡/铜籽晶层104完全被移除。
减少硅基板的厚度可增进硅基板的散热效率。表格II比较了不同厚度的硅基板的热阻模拟结果。
  厚度(μm)   热阻(K/Watt)
  500   4.82
  200   3.18
  100   1.81
  50   0.92
表II：不同厚度的硅基板的热阻比较
结果显示在基板厚度减少至100微米时，热阻大幅地降低。除了位于硅穿孔(或沟槽)内的铜所提供的散热，较薄的硅厚度可提供额外的散热。
在晶背研磨后，沉积一介电层150至第一基板100背面，如图9所示。介电层150与隔离层103相似，可为氧化物、氮化物及上述两者的一组合。可为介电层150材质的一个例子为利用PECVD所沉积的氧化硅(silicon oxide)，其中利用硅烷为硅来源。在一些实施例中，隔离层的厚度约为5000～20000埃。在一些实施例中，介电层150也可为利用例如磷，或硼及磷的掺质的一掺杂膜。如先前提到，PSG及BPSG膜中的磷可阻挡铜。
在沉积介电层150之后，以一光致抗蚀剂层151沉积及图案化基板，如图10所示。可经由一湿式旋转涂布或一干膜光致抗蚀剂沉积光致抗蚀剂层151。图案在硅穿孔(或沟槽)的区域有开口，以移除这些区域的介电层150。在形成光致抗蚀剂图案后，经由蚀刻移除在图案下被暴露的介电层150。可使用在半导体芯片制造中的介电蚀刻工艺来达成移除。蚀刻工艺可为干蚀刻或湿蚀刻。图11显示在开口区域中的介电层150被蚀刻后的第一基板100及第二基板108。
之后，沉积一阻挡/铜籽晶层152，如图12所示。阻挡/铜籽晶层152为一聚合层，其包括一阻隔层及一铜籽晶层。阻挡层可避免铜扩散进入硅基板。如上所述，Ta、TaN、Ti、TiN、CoW或上述任意组合的膜可用来当作阻挡。在一些实施例中，阻挡材质为Ti，且沉积厚度约为500～5000埃。沉积一薄铜籽晶层，其厚度约为1000～10000埃。阻挡层及铜籽晶层的沉积方法已在之前叙述。
在沉积阻挡/铜籽晶层152之后，以一光致抗蚀剂层153图案化基板以定义出将接收镀铜的区域，如图13所示。如上所述，光致抗蚀剂可为一旋转涂布光致抗蚀剂(湿式)或一DFR。在光致抗蚀剂图案化之后，先电镀一铜层154于基板的暴露区域上(未被光致抗蚀剂覆盖)。如上所述，铜层154的电镀工艺可为ECP或一无电镀铜工艺。在一些实施例中，因担心上述的基板翘曲发生，铜层154的厚度小于30微米。在一些实施例中，铜层154的厚度约为10～20微米。之后，沉积一扩散阻挡层155于层154之上。扩散阻挡层155终会接收一焊层及一集成电路(integrated circuit，IC)芯片(将在下叙述)。扩散阻挡层155避免层154的铜扩散进入置于TSV基板上的IC芯片。在一些实施例中，可经由电镀沉积扩散阻挡层155，例如ECP或无电极电镀。在一些实施例中，扩散阻挡层155为化镍浸金(nickel immersion gold，ENIG)材质。尽管如此，可使用任何合适的扩散阻挡材质。
在沉积扩散阻挡层155之后，移除光致抗蚀剂层153及光致抗蚀剂层153之下的阻挡/铜籽晶层152。图14显示不具有光致抗蚀剂层153及其下的阻挡/铜籽晶层152的基板100。在此时，第一基板100准备接收半导体芯片。可经由稍微不同的操作将不同的半导体芯片置于第一基板100上。在一些实施例中，半导体芯片为发光装置(light-emitting devices，LEDs)。
在上述操作之后，利用一共晶接合层157将一半导体芯片156被牢固地连接至扩散阻挡层155。在一些实施例中，共晶接合层157为焊锡材质。在图15所示的实施例中，半导体芯片156为一发光装置(LED)。放置LED芯片于P接点159上，而LED芯片经由一导线158电性连接至N接点160上。实施一打线接合操作以连接LED芯片156至N接点160。图15显示放置LED芯片156于第一基板100上，芯片经由共晶接合层157被接合至基板100，也经由一导线158接合至N接点。因为层155的P接点159的表面大抵平坦，LED芯片156不需导电凸块即可被直接放置在第一基板100上。
图13～图15所示的铜层154提供电性连接及热接点至放置于其上的半导体芯片(例如一LED芯片)156。铜层154也可称为一金属垫，且不需为铜材质。在一些实施例中，金属垫154可为焊锡，其可在图案化光致抗蚀剂层153之后，经由一电镀(如上所述)工艺或涂布一焊锡膏沉积于基板表面之上。焊锡膏会填入光致抗蚀剂层153形成的开口，且只有极少量会残留于光致抗蚀剂层153上。光致抗蚀剂层153上所残留的少量焊锡膏对于光致抗蚀剂层153的移除工艺仅会有非常小的影响。如果使用焊锡膏于层154(当作一金属垫)，则不需要阻挡/铜籽晶层152的铜籽晶层部分。如果是电镀焊锡层，可使用一焊锡籽晶层或一非焊锡材质籽晶层。如果是涂布焊锡层于基板上，则不需要使用一籽晶层。
如图15所示，硅穿孔120及层(或金属垫)154的一部分延伸超过LED芯片156的边缘。一封装基板(例如基板100)的电性及/或热连接(例如硅穿孔120及层154)超过半导体芯片(例如LED156)的延伸可被称为扇出式封装(fan-out packaging)，其可提供额外的区域以重新导引及散热。金属层154超过LED芯片156边缘的延伸可为散热提供水平路径及区域。硅穿孔120超过LED芯片156的延伸可提供空间给更多的硅穿孔120，为散热提供垂直路径及区域。水平和垂直路径及区域会影响并改善散热效率。
在连结LED芯片156至基板及打线接合之后，封装LED芯片156如图16所示。在一些实施例中，沉积一层荧光层161于LED芯片156之上。一LED芯片被设计为发出红、蓝或绿光。发射出红、蓝及绿光的多个LED芯片通常被放置在一起以发出白光。荧光层可用来使LED发出白光。在一些实施例中，荧光层161被涂布在LED芯片156上。尽管如此，荧光层161的涂布为选择性的。在一些实施例中，不同的荧光层被涂布在不同颜色(或不同放射波长)的多个LED上。在一些其他实施例中，不需要一荧光层，如膜161。
之后，放置一模封材质162，其环绕LED芯片156、P接点159及N接点160。在一些实施例中，模封为一透明环氧树脂。模封材质是否为透明与LED相关。如果半导体芯片不是一LED，则模封不需要为透明。
图17显示模封LED芯片156的一面被放置于一粘着胶带163上。粘着胶带(或蓝胶带)163牢固地支撑LED芯片156的模封162及第一基板100，以准备分离第二基板108。在以化学及机械方法移除第二基板108及胶着层107之后，用锯子实体分离第一基板100上的各裸片，其中各裸片具有一LED芯片156、N接点及P接点。图18显示虚设基板108及胶着层107已被移除及支撑一单封装芯片180的粘着胶带164。可在之后实施其他工艺操作，例如放置封装芯片180在一印刷电路板上，移除粘着胶带层163等等。第二基板的移除也可介由移除粘着胶带，此法第二基板则可重复利用。
上述的示范性的工艺流程图显示如何封装具有硅穿孔基板的半导体芯片以增进散热。另外，因为硅基板的厚度已薄至大约20～200微米，上述封装芯片的散热优于其他硅穿孔技术。
上述的芯片封装方法及结构可被用在非LED的半导体芯片。当封装方法及结构被用在非LED的芯片，图15之后的工艺流程图可能会不同。
图15～图18显示单一半导体装置(一LED装置)的剖面示意图。或者，一封装体可乘载多于一个装置。一封装体通常具有3个、6个或甚至更多的LED芯片。图19A显示单个N接点205包围三个LED芯片201、202、203于其中，且所述多个芯片通过导线，例如导线204，连接至N接点(或电极)205。图19B显示图19A沿PP切线的简化剖面图。图中并未显示出封装体里所有的层。在一些实施例中，设计三个LED201、202、203为可发射不同波长光，例如蓝、绿及红色。在每个LED芯片下，有至少一个硅穿孔，例如在图1～图19显示的例子中，每个LED芯片下有两个硅穿孔。在本实施例中，N接点(或N电极)205为一圆形硅穿沟槽(或导孔)。
图20A显示另一实施例中三个LED芯片211、212、213与单个N接点215连接的示意图。图20B显示图20A沿RR切线的简化剖面图。假使LED芯片212的硅穿孔218的侧壁未被足够的铜阻挡层216所覆盖，则在导孔218中的铜217可扩散到邻近结构(未显示)且造成漏电流问题。图20C显示图19B的剖面图的另一实施例。当导孔208中的铜因铜阻挡层的阶梯覆盖不佳而向外扩散，N电极205的铜阻挡层216会阻档扩散出的铜。因此在装置下有足够的硅沟槽环绕硅穿孔(沟槽)，可提供额外的保护阻止铜扩散。
图21显示上述利用硅穿孔技术封装LED芯片的另一实施例。6个LED芯片，201、201’、202、202’、203、203’被放置于一封装体中，且被一长方形N接点(或N电极)经由导线环绕。6个LED芯片可为2个蓝光LED、2个绿光LED及2个红光LED。
半导体芯片之下的穿硅插塞(或导孔或沟槽)可为各式形状及大小。例如硅穿孔可为圆柱状。图22A显示在一半导体芯片之下一TSP(或TSV)401(圆柱体)的俯视图。如上所述，TSP401的直径为D1。如上所述，D1可为约5～100微米。对于具有与TSP401表面约相同的表面积(或顶部表面积)的小芯片来说，可使用单个TSP，例如TSP401。但通常半导体芯片的表面积(或顶部表面积)远大于单个TSP的表面积。举例来说，一LED芯片的表面积可为0.6x0.6平方毫米，1x1平方毫米或更大。应注意的是这些数字仅为举例。另外，半导体芯片的顶部表面不需为正方形。顶部表面可为长方形或其他形状。
TSP的尺寸不能太大(或具有太大的剖面)，以避免间隙被大量填入及其他问题。图22B显示TSP的一实施例，其具有多个TSP，例如402、403、404及405，为置于TSP上的半导体芯片提供足够的散热能力。图22B仅显示4个TSP。尽管如此，可有多于或少于4个TSP(例如2个或3个)。在一些实施例中，各TSP的直径D2约为5～100微米。D3是图22B中两个TSP之间的最小距离。在一些实施例中，D3等于或大于D2。
在一些实施例中，TSP(或TSV)可为同心圆形状如图22C所示。可有一个或多个的同心圆。图22C显示围绕一中心圆柱406的一同心圆407。在一些实施例中，TSV 406的直径D4约为5～100微米。在一些实施例中，图22B中TSP(或TSV)407的宽度D6约为5～100微米。在一些实施例中，TSP之间的距离D5等于或大于D4或D6。
TSP不需为圆形。图22D显示多个TSP，例如TSP408及409。TSP(或TSV)408及409为具有宽度L1及长度L2的长方形，且相距一距离L3。在一些实施例中，宽度L1约为5～100微米。在一些实施例中，TSP之间的距离L3等于或大于L1。长方形TSP的数目可为一个或多个。
在一些实施例中，TSP可为一图案，如图22E所示。图22E显示被图案化且在图案中具有多个开口(例如开口411)的TSP410。图22E中的开口411为正方形。尽管如此，开口也可为长方柱或圆柱。在一些实施例中，开口411之间的距离为L5，且L5等于或小于开口的宽度L4。图22F及图22G显示两个不同版本的TSP。图22F的TSP412及图22G的TSP413的图案使得TSP有大的表面积。尽管如此，图22F及图22G的TSP并不是连续的一大块。如此的图案可避免工艺问题，例如需要长时间电镀或是其他问题。在此未提到的其他的TSV或TSP的形状、图案及排列或以上所述结构的变化也是可能的。在一些实施例中，图22D、E、F、及G中所示的图案的边角为圆的。
可在一个或更多半导体芯片之下使用上述具有不同图案的TSP的实施例，以增进散热及解决工艺问题，例如需长时间电镀铜。
以上所述的实施例为具硅穿孔(或沟槽)的半导体装置封装体提供方法及结构。具有硅穿孔的基板可经由穿硅插塞(或导孔)为半导体芯片提供极佳的散热，且不会产生传统封装结构所遭遇的热应力、散热不佳、低可靠度、低产品寿命、电性隔绝及高花费的问题。
上述具有穿硅插塞(或导孔)的基板可不需使用导电凸块。工艺流程非常简单及具有成本效益。本结构将个别的TSV、重分布层及导电凸块结构结合至单一结构中。经由结合个别的结构，可以得到一具有高散热能力的低电阻电性连接。另外，具有穿硅插塞(或导孔，或沟槽)的基板也使得多个芯片可以封装在一起。穿硅沟槽可围绕一个或更多芯片，以在工艺中避免铜扩散到邻近装置。另外多个具有相似或相异功能的芯片可整合在TSV基板上。具不同图案的穿硅插塞可用在一半导体芯片之下以增进散热及解决工艺问题。
在一实施例中，提供一半导体装置封装体。该封装体包括一具穿硅插塞的基板，其中穿硅插塞从该基板的一第一表面延伸至与该第一表面相反的一第二表面。一隔离层及一第一铜阻挡层内衬于一个或多个穿硅插塞的侧壁。以一第一铜层填入穿硅插塞，其中所述多个穿硅插塞具有第一端及第二端。第二端具有第一铜层延伸于基板的第一表面之上，而第一端具有一第一铜层填充至基板的第二表面。该封装体也包括一第二铜层，形成于穿硅插塞的第一端上。第二铜层定义出一区域以接收半导体芯片，而有一第二铜阻挡层分离硅穿孔第一端上的第一铜层与第二铜层。该封装体还包括半导体芯片，放置于第二铜层所定义的区域上。
在另一实施例中，提供一半导体装置封装体。该封装体包括至少三个发光装置，上述至少三个发光装置发射多于一种波长的光。该封装体还包括一基板，其具有一个或多个穿硅插塞的，其中穿硅插塞从基板的一第一表面延伸至与第一表面相反的一第二表面。一隔离层及一第一铜阻挡层内衬于一个或多个穿硅插塞的侧壁，且以一第一铜层填入上述一个或多个穿硅插塞。一个或多个穿硅插塞具有第一端及第二端，其中第二端有第一铜层延伸于基板的第一表面之上，而第一端有第一铜层填充至基板的第二表面。该封装体还包括一第二铜层，形成于穿硅插塞的第一端上。第二铜层定义出一区域以接收这些至少三个发光装置，而有一第二铜隔离层分离该一个或多个穿硅插塞的第一端上的第一铜层与第二铜层。至少三个发光装置放置于被第二铜层所定义出的区域。穿硅插塞的其中一者为一沟槽状，其环绕该至少三个发光装置及这些发光装置下的穿硅插塞。在沟槽中的第一阻挡层避免来自被沟槽环绕的穿硅插塞的铜扩散。
在另一实施例中，提供半导体封装体的一制造方法。方法包括一操作，其中提供一第一基板，及另一操作，其中在第一基板中形成从第一基板的一第一表面开始延伸的穿硅插塞。一隔离层及一第一铜阻挡层内衬于穿硅插塞，且一第一铜层填入穿硅插塞。该方法还包括一操作，从第一基板移除多余的硅，以暴露埋藏于第一基板中的穿硅插塞的第一端。该方法还包括一操作，其中形成一第二铜层在穿硅插塞的第一端。在形成第二铜层之前，沉积一第二铜阻挡层在穿硅插塞的第一端上。另外，该方法包括一操作，其中放置该半导体芯片于这些第一端上的第二铜层的表面上。
虽然本发明已以多个较佳实施例公开如上，然其并非用以限定本发明，任何所属技术领域中的技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (10)

1.一种半导体装置封装体，包括：
一基板，其具有从该基板的一第一表面延伸至与该第一表面相反的一第二表面的多个穿硅插塞，其中一隔离层及一第一铜阻挡层内衬于该一个或多个穿硅插塞的侧壁，且一第一铜层填入所述多个穿硅插塞，其中所述多个穿硅插塞具有第一端及第二端，且其中第二端具有该第一铜层延伸于该基板的第一表面之上，而第一端具有该第一铜层填充至该基板的第二表面；
一第二铜层，形成于所述多个穿硅插塞的第一端上，其中该第二铜层定义出一区域以接收一半导体芯片，其中具有一第二铜阻挡层分离所述多个穿硅插塞第一端上的该第一铜层与该第二铜层；及
该半导体芯片置于该第二铜层所定义出的区域之上。
2.如权利要求1所述的半导体装置封装体，其中具有一共晶接合层及一铜扩散阻挡层于该第二铜层及该半导体芯片之间，其中该铜扩散阻挡层与该第二铜层直接接触，且该共晶接合层与该半导体芯片直接接触。
3.如权利要求1所述的封装体，其中该半导体芯片为一发光装置。
4.如权利要求1所述的封装体，其中所述多个穿硅插塞的其中一为沟槽状，环绕该半导体芯片及放置于该半导体芯片之下的穿硅插塞，其中该沟槽中的该第一阻挡层避免来自被该沟槽环绕的所述多个穿硅插塞的铜扩散。
5.如权利要求1所述的封装体，其中所述多个穿硅插塞的其中一为一圆形沟槽或一具有多个圆边角的长方形沟槽。
6.如权利要求1所述的封装体，其中具有该一个或多个穿硅插塞于该半导体装置之下，其中该一个或多个穿硅插塞具有择自下列的剖面形状：单个圆、多个圆、单个长方形、多个长方形、具有至少四个边角的单个图案，及多个图案，其中一具有至少四个边角。
7.一种半导体装置封装体，包括：
至少三个发光装置，其中所述多个发光装置发射多于一种波长的光；
一基板，具有一个或多个穿硅插塞从该基板的一第一表面延伸至该第一表面对面的一第二表面，其中一隔离层及一第一铜阻挡层内衬于该一个或多个穿硅插塞的侧壁，一第一铜层填入该一个或多个穿硅插塞，其中该一个或多个穿硅插塞具有第一端及第二端，其中所述多个第二端具有该第一铜层延伸于该基板的第一表面之上，而所述多个第一端具有该第一铜层填充至该基板的第二表面；
一第二铜层，形成于所述多个穿硅插塞的所述多个第一端之上，其中一第二铜层定义出一区域以接收所述这些至少三个发光装置，其中具有一第二铜阻挡层，将该一个或多个穿硅插塞的第一端上的该第一铜层与该第二铜层分离，其中所述这些至少三个发光装置被放置于由该第二铜层所定义出的区域上；其中所述多个穿硅插塞的其中一为一沟槽状，环绕所述这些至少三个发光装置及所述多个置于所述这些至少三个发光装置之下的穿硅插塞，其中该沟槽中的该第一阻挡层避免来自被该沟槽环绕的所述多个穿硅插塞的铜扩散。
8.一种半导体装置封装体的制造方法，包括：
提供一第一基板；
形成多个穿硅插塞于该第一基板内，所述多个穿硅插塞从该第一基板的一第一表面延伸，其中一隔离层及一第一铜阻挡层内衬于所述多个穿硅插塞，其中一第一铜层填入所述多个穿硅插塞；
移除该第一基板上多余的硅，以暴露埋藏于该第一基板中的所述多个穿硅插塞的所述多个第一端；
形成一第二铜层于所述多个穿硅插塞的所述多个第一端上，其中在形成该第二铜层之前，沉积一第二铜阻挡层于所述多个穿硅插塞的所述多个第一端；及
放置该半导体芯片于所述多个第一端上的第二铜层的表面上。
9.如权利要求14所述的半导体装置封装体的制造方法，还包括：
沉积一扩散阻挡层于该第二铜层上，在该第二铜层形成之后；
沉积一共晶接合层于扩散阻挡层之上；及
直接放置该半导体芯片于该共晶接合层之上。
10.如权利要求14所述的半导体装置封装体的制造方法，其中利用干膜光致抗蚀剂图案化该第一基板，并实施该图案化工艺于打开所述多个穿硅插塞之后与填入所述多个穿硅插塞之前，以避免湿式光致抗蚀剂污染所述多个穿硅插塞的所述多个开口的表面。
CN201110070897.1A 2010-04-05 2011-03-21 半导体装置封装体及其制造方法 Active CN102214621B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US32081910P 2010-04-05 2010-04-05
US61/320,819 2010-04-05
US12/897,124 2010-10-04
US12/897,124 US8946742B2 (en) 2010-04-05 2010-10-04 Semiconductor package with through silicon vias

Publications (2)

Publication Number Publication Date
CN102214621A true CN102214621A (zh) 2011-10-12
CN102214621B CN102214621B (zh) 2014-12-03

Family

ID=44708609

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201110038181.3A Active CN102214617B (zh) 2010-04-05 2011-02-11 半导体封装基板
CN201110070897.1A Active CN102214621B (zh) 2010-04-05 2011-03-21 半导体装置封装体及其制造方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201110038181.3A Active CN102214617B (zh) 2010-04-05 2011-02-11 半导体封装基板

Country Status (5)

Country Link
US (6) US8507940B2 (zh)
JP (1) JP5389092B2 (zh)
KR (1) KR101271374B1 (zh)
CN (2) CN102214617B (zh)
TW (2) TWI445140B (zh)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103311141A (zh) * 2013-07-05 2013-09-18 北京理工大学 一种同轴垂直互连导电体的制作方法
CN103999009A (zh) * 2011-12-22 2014-08-20 英特尔公司 封装体上输入/输出架构
CN104576521A (zh) * 2015-01-27 2015-04-29 华进半导体封装先导技术研发中心有限公司 一种tsv孔制造工艺
CN105070682A (zh) * 2015-07-17 2015-11-18 上海交通大学 一种高效制备硅转接板的方法
CN105206642A (zh) * 2015-10-13 2015-12-30 南京大学 一种超高密度led显示器件及其制造方法
CN109994586A (zh) * 2012-03-30 2019-07-09 亮锐控股有限公司 密封的半导体发光器件
CN111868589A (zh) * 2018-04-09 2020-10-30 华为技术有限公司 激光器、激光器阵列的封装结构及封装组件
CN113130730A (zh) * 2020-01-16 2021-07-16 深圳市聚飞光电股份有限公司 发光器件封装方法及发光器件
CN113345857A (zh) * 2020-02-18 2021-09-03 南亚科技股份有限公司 半导体元件及其制备方法
CN113632214A (zh) * 2019-03-19 2021-11-09 株式会社电装 半导体模组及用于该半导体模组的半导体装置

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008198916A (ja) * 2007-02-15 2008-08-28 Spansion Llc 半導体装置及びその製造方法
US8399273B2 (en) 2008-08-18 2013-03-19 Tsmc Solid State Lighting Ltd. Light-emitting diode with current-spreading region
US8399268B1 (en) * 2011-12-28 2013-03-19 Ledengin, Inc. Deposition of phosphor on die top using dry film photoresist
KR20110134198A (ko) * 2010-06-08 2011-12-14 삼성전자주식회사 관통 전극을 갖는 반도체 장치
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
KR101215644B1 (ko) * 2010-12-01 2012-12-26 에스케이하이닉스 주식회사 반도체 칩, 반도체 패키지 및 반도체 칩 제조방법
US8236584B1 (en) * 2011-02-11 2012-08-07 Tsmc Solid State Lighting Ltd. Method of forming a light emitting diode emitter substrate with highly reflective metal bonding
US8742564B2 (en) * 2011-01-17 2014-06-03 Bai-Yao Lou Chip package and method for forming the same
TWI445100B (zh) * 2011-05-20 2014-07-11 Subtron Technology Co Ltd 封裝結構及其製作方法
CN103999014B (zh) * 2011-11-15 2019-03-12 汉高知识产权控股有限责任公司 利用热绝缘层组装的电子设备
CN102376642A (zh) * 2011-11-24 2012-03-14 上海华力微电子有限公司 一种硅通孔工艺
ITMI20112296A1 (it) * 2011-12-16 2013-06-17 St Microelectronics Srl Dispositivo elettronico flessibile incapsulato e relativo metodo di fabbricazione
US9082764B2 (en) 2012-03-05 2015-07-14 Corning Incorporated Three-dimensional integrated circuit which incorporates a glass interposer and method for fabricating the same
US9312432B2 (en) 2012-03-13 2016-04-12 Tsmc Solid State Lighting Ltd. Growing an improved P-GaN layer of an LED through pressure ramping
CN103367297B (zh) * 2012-03-31 2016-12-14 南亚科技股份有限公司 具有带状打线的封装结构
US9406587B2 (en) * 2012-06-26 2016-08-02 Intel Corporation Substrate conductor structure and method
US9224640B2 (en) 2012-08-17 2015-12-29 Globalfoundries Inc. Method to improve fine Cu line reliability in an integrated circuit device
DE102012108704A1 (de) * 2012-09-17 2014-03-20 Osram Opto Semiconductors Gmbh Verfahren zur Fixierung einer matrixfreien elektrophoretisch abgeschiedenen Schicht auf einem Halbleiterchip und strahlungsemittierendes Halbleiterbauelement
CN205657081U (zh) 2013-01-16 2016-10-19 3M创新有限公司 支撑制品
US9455188B2 (en) * 2013-01-18 2016-09-27 Globalfoundries Inc. Through silicon via device having low stress, thin film gaps and methods for forming the same
US9123789B2 (en) * 2013-01-23 2015-09-01 United Microelectronics Corp. Chip with through silicon via electrode and method of forming the same
DE102013100818B4 (de) 2013-01-28 2023-07-27 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips
KR101958418B1 (ko) 2013-02-22 2019-03-14 삼성전자 주식회사 발광 소자 패키지
KR101504331B1 (ko) 2013-03-04 2015-03-19 삼성전자주식회사 발광소자 패키지
FR3003403B1 (fr) * 2013-03-14 2016-11-04 Commissariat Energie Atomique Procede de formation de diodes electroluminescentes
CN103236417A (zh) * 2013-04-28 2013-08-07 江苏物联网研究发展中心 一种高深宽比tsv的填充方法
US9296607B2 (en) * 2013-07-22 2016-03-29 Invensense, Inc. Apparatus and method for reduced strain on MEMS devices
TWI511257B (zh) * 2013-07-30 2015-12-01 Univ Nat Chiao Tung 半導體元件之內連接結構
US9514986B2 (en) * 2013-08-28 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Device with capped through-substrate via structure
DE102013111977A1 (de) * 2013-10-30 2015-04-30 Osram Opto Semiconductors Gmbh Optoelektronischer Halbleiterchip und Anordnung mit mindestens einem solchen optoelektronischen Halbleiterchip
TWI509767B (zh) * 2013-12-13 2015-11-21 Universal Scient Ind Shanghai 電子封裝模組及其製造方法
TWI657132B (zh) 2013-12-19 2019-04-21 德商漢高智慧財產控股公司 具有基質及經密封相變材料分散於其中之組合物及以其組裝之電子裝置
CN103826422B (zh) * 2014-02-13 2016-06-29 中国科学院工程热物理研究所 微通道冷却装置
KR102116986B1 (ko) 2014-02-17 2020-05-29 삼성전자 주식회사 발광 다이오드 패키지
KR102258743B1 (ko) 2014-04-30 2021-06-02 삼성전자주식회사 반도체 패키지의 제조 방법, 이에 의해 형성된 반도체 패키지 및 이를 포함하는 반도체 장치
KR20150139660A (ko) * 2014-06-03 2015-12-14 삼성전자주식회사 전자소자 패키지
DE102015101070A1 (de) * 2015-01-26 2016-07-28 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauteil, optoelektronische Anordnung und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils
WO2016167750A1 (en) * 2015-04-14 2016-10-20 Hewlett Packard Enterprise Development Lp Penetration detection boundary having a heat sink
US10950689B2 (en) * 2015-09-23 2021-03-16 Nanyang Technological University Semiconductor device with a through-substrate via hole having therein a capacitor and a through-substrate via conductor
JP6450296B2 (ja) * 2015-10-05 2019-01-09 浜松ホトニクス株式会社 配線構造体、及び配線構造体の製造方法
US9741581B2 (en) * 2016-01-11 2017-08-22 Globalfoundries Inc. Using tensile mask to minimize buckling in substrate
US10170337B2 (en) * 2016-01-13 2019-01-01 International Business Machines Corporation Implant after through-silicon via (TSV) etch to getter mobile ions
US10490483B2 (en) * 2016-03-07 2019-11-26 Micron Technology, Inc. Low capacitance through substrate via structures
JP6973727B2 (ja) * 2017-03-15 2021-12-01 ローム株式会社 電子装置
US10068865B1 (en) 2017-05-10 2018-09-04 Nanya Technology Corporation Combing bump structure and manufacturing method thereof
KR102502176B1 (ko) * 2017-10-13 2023-02-21 삼성전자주식회사 디스플레이 장치 및 그 제조방법
US10163693B1 (en) 2017-12-21 2018-12-25 Micron Technology, Inc. Methods for processing semiconductor dice and fabricating assemblies incorporating same
WO2019132957A1 (en) * 2017-12-29 2019-07-04 Intel Corporation Microelectronic assemblies
FR3080709B1 (fr) 2018-04-26 2023-01-20 St Microelectronics Grenoble 2 Vias conducteurs
JP6897640B2 (ja) 2018-08-02 2021-07-07 日亜化学工業株式会社 発光装置の製造方法
TWI686940B (zh) * 2018-10-31 2020-03-01 世界先進積體電路股份有限公司 光學感測結構及其形成方法
US10651218B1 (en) * 2019-01-03 2020-05-12 Vanguard International Semiconductor Corporation Optical sensor structure and method for forming the same
CN109686707A (zh) * 2019-01-28 2019-04-26 南通大学 高散热硅基封装基板、制作方法及高散热封装结构
US20210125910A1 (en) * 2019-10-25 2021-04-29 Nanya Technology Corporation Semiconductor structure
CN115023791A (zh) * 2020-01-28 2022-09-06 力特保险丝公司 半导体芯片封装件和组装方法
CN111341768B (zh) * 2020-03-06 2022-01-11 弘凯光电(深圳)有限公司 一种传感模组
US20220406696A1 (en) * 2021-06-16 2022-12-22 Intel Corporation Package substrate with glass core having vertical power planes for improved power delivery
US11955416B2 (en) * 2021-09-15 2024-04-09 Macronix International Co., Ltd. Semiconductor structure and method for manufacturing the same
CN116264184A (zh) * 2021-12-15 2023-06-16 长鑫存储技术有限公司 一种半导体结构及其制造方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531328B1 (en) * 2001-10-11 2003-03-11 Solidlite Corporation Packaging of light-emitting diode
US20050133930A1 (en) * 2003-12-17 2005-06-23 Sergey Savastisuk Packaging substrates for integrated circuits and soldering methods
US20050142874A1 (en) * 2003-12-31 2005-06-30 Keum Dong Y. Methods for fabricating a copper interconnect
CN1639383A (zh) * 2002-03-19 2005-07-13 株式会社液晶先端技术开发中心 布线金属层的形成方法、选择性形成金属的方法、选择性形成金属的装置及基板装置
US20060170072A1 (en) * 2005-02-03 2006-08-03 Nec Electronics Corporation Circuit board and semiconductor device
US20060261364A1 (en) * 2003-03-10 2006-11-23 Yoshinobu Suehiro Solid element device and method for manufacturing thereof
JP2008034748A (ja) * 2006-07-31 2008-02-14 Matsushita Electric Works Ltd 発光装置
CN101577304A (zh) * 2008-05-05 2009-11-11 台湾积体电路制造股份有限公司 发光二极管封装结构

Family Cites Families (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074342A (en) 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
JPH05211239A (ja) 1991-09-12 1993-08-20 Texas Instr Inc <Ti> 集積回路相互接続構造とそれを形成する方法
DE4314907C1 (de) 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
US5391917A (en) 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
JP3323324B2 (ja) 1993-06-18 2002-09-09 株式会社リコー 発光ダイオードおよび発光ダイオードアレイ
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
EP2270845A3 (en) 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
US6037822A (en) 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP3516434B2 (ja) 1997-12-25 2004-04-05 昭和電工株式会社 化合物半導体発光素子
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6198225B1 (en) * 1999-06-07 2001-03-06 Symetrix Corporation Ferroelectric flat panel displays
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
EP1472730A4 (en) 2002-01-16 2010-04-14 Mann Alfred E Found Scient Res HOUSING FOR ELECTRONIC CIRCUITS WITH REDUCED SIZE
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US7030481B2 (en) 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US7111149B2 (en) 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
TWI251313B (en) 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
JP2005159299A (ja) 2003-10-30 2005-06-16 Sharp Corp 半導体発光素子
US7335972B2 (en) 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
US7049170B2 (en) 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
JP4467318B2 (ja) 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
US20080043444A1 (en) 2004-04-27 2008-02-21 Kyocera Corporation Wiring Board for Light-Emitting Element
US7508001B2 (en) 2004-06-21 2009-03-24 Panasonic Corporation Semiconductor laser device and manufacturing method thereof
US7262495B2 (en) 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
US7891836B2 (en) 2004-10-22 2011-02-22 Koninklijke Philips Electronics N.V. Semiconductor light-emitting device with improved heatsinking
US7148554B2 (en) 2004-12-16 2006-12-12 Delphi Technologies, Inc. Discrete electronic component arrangement including anchoring, thermally conductive pad
KR100593937B1 (ko) 2005-03-30 2006-06-30 삼성전기주식회사 Ｓｉ기판을 이용한 ＬＥＤ 패키지 및 그 제조방법
US7297574B2 (en) 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
JP5209177B2 (ja) * 2005-11-14 2013-06-12 新光電気工業株式会社 半導体装置および半導体装置の製造方法
GB2432455A (en) 2005-11-17 2007-05-23 Sharp Kk Growth of a semiconductor layer structure
KR100721147B1 (ko) 2005-11-23 2007-05-22 삼성전기주식회사 수직구조 질화갈륨계 발광다이오드 소자
US7928462B2 (en) * 2006-02-16 2011-04-19 Lg Electronics Inc. Light emitting device having vertical structure, package thereof and method for manufacturing the same
KR100867529B1 (ko) 2006-11-14 2008-11-10 삼성전기주식회사 수직형 발광 소자
CN100433391C (zh) 2006-11-30 2008-11-12 何永祥 一种采用多孔金属材料作为散热装置的大功率发光二极管
US7800304B2 (en) * 2007-01-12 2010-09-21 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Multi-chip packaged LED light source
US20080284037A1 (en) * 2007-05-15 2008-11-20 Andry Paul S Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers
US7855397B2 (en) 2007-09-14 2010-12-21 Nextreme Thermal Solutions, Inc. Electronic assemblies providing active side heat pumping
TW200915505A (en) 2007-09-29 2009-04-01 Kinik Co Packaging carrier with high heat-dissipation and method for manufacturing the same
US20090256217A1 (en) * 2008-04-14 2009-10-15 Lsi Logic Corporation Carbon nanotube memory cells having flat bottom electrode contact surface
JP5185683B2 (ja) * 2008-04-24 2013-04-17 パナソニック株式会社 Ｌｅｄモジュールの製造方法および照明器具の製造方法
JP2010027974A (ja) * 2008-07-23 2010-02-04 Sharp Corp 発光装置の製造方法
US8399273B2 (en) 2008-08-18 2013-03-19 Tsmc Solid State Lighting Ltd. Light-emitting diode with current-spreading region
US20100108893A1 (en) * 2008-11-04 2010-05-06 Array Optronix, Inc. Devices and Methods for Ultra Thin Photodiode Arrays on Bonded Supports
US20100127299A1 (en) 2008-11-25 2010-05-27 Cooper Technologies Company Actively Cooled LED Lighting System and Method for Making the Same
US20100140790A1 (en) 2008-12-05 2010-06-10 Seagate Technology Llc Chip having thermal vias and spreaders of cvd diamond
TWI358515B (en) 2009-01-20 2012-02-21 Wun Song Hu Heat dissipation structure for light-emitting comp
US8174044B2 (en) * 2010-01-14 2012-05-08 Shang-Yi Wu Light emitting diode package and method for forming the same
US8183579B2 (en) 2010-03-02 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. LED flip-chip package structure with dummy bumps
US8441020B2 (en) * 2010-03-10 2013-05-14 Micron Technology, Inc. Light emitting diode wafer-level package with self-aligning features
US20130221320A1 (en) 2012-02-27 2013-08-29 Tsmc Solid State Lighting Ltd. Led with embedded doped current blocking layer

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531328B1 (en) * 2001-10-11 2003-03-11 Solidlite Corporation Packaging of light-emitting diode
CN1639383A (zh) * 2002-03-19 2005-07-13 株式会社液晶先端技术开发中心 布线金属层的形成方法、选择性形成金属的方法、选择性形成金属的装置及基板装置
US20060261364A1 (en) * 2003-03-10 2006-11-23 Yoshinobu Suehiro Solid element device and method for manufacturing thereof
US20050133930A1 (en) * 2003-12-17 2005-06-23 Sergey Savastisuk Packaging substrates for integrated circuits and soldering methods
US20050142874A1 (en) * 2003-12-31 2005-06-30 Keum Dong Y. Methods for fabricating a copper interconnect
US20060170072A1 (en) * 2005-02-03 2006-08-03 Nec Electronics Corporation Circuit board and semiconductor device
JP2008034748A (ja) * 2006-07-31 2008-02-14 Matsushita Electric Works Ltd 発光装置
CN101577304A (zh) * 2008-05-05 2009-11-11 台湾积体电路制造股份有限公司 发光二极管封装结构

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103999009A (zh) * 2011-12-22 2014-08-20 英特尔公司 封装体上输入/输出架构
US9519609B2 (en) 2011-12-22 2016-12-13 Intel Corporation On-package input/output architecture
CN109994586B (zh) * 2012-03-30 2022-06-03 亮锐控股有限公司 密封的半导体发光器件
CN109994586A (zh) * 2012-03-30 2019-07-09 亮锐控股有限公司 密封的半导体发光器件
CN103311141A (zh) * 2013-07-05 2013-09-18 北京理工大学 一种同轴垂直互连导电体的制作方法
CN103311141B (zh) * 2013-07-05 2016-01-20 北京理工大学 一种同轴垂直互连导电体的制作方法
CN104576521A (zh) * 2015-01-27 2015-04-29 华进半导体封装先导技术研发中心有限公司 一种tsv孔制造工艺
CN105070682A (zh) * 2015-07-17 2015-11-18 上海交通大学 一种高效制备硅转接板的方法
CN105070682B (zh) * 2015-07-17 2018-05-29 上海交通大学 一种高效制备硅转接板的方法
CN105206642A (zh) * 2015-10-13 2015-12-30 南京大学 一种超高密度led显示器件及其制造方法
CN111868589A (zh) * 2018-04-09 2020-10-30 华为技术有限公司 激光器、激光器阵列的封装结构及封装组件
CN111868589B (zh) * 2018-04-09 2022-10-04 华为技术有限公司 激光器、激光器阵列的封装结构及封装组件
CN113632214A (zh) * 2019-03-19 2021-11-09 株式会社电装 半导体模组及用于该半导体模组的半导体装置
CN113632214B (zh) * 2019-03-19 2023-12-08 株式会社电装 半导体模组及用于该半导体模组的半导体装置
CN113130730A (zh) * 2020-01-16 2021-07-16 深圳市聚飞光电股份有限公司 发光器件封装方法及发光器件
CN113345857A (zh) * 2020-02-18 2021-09-03 南亚科技股份有限公司 半导体元件及其制备方法

Also Published As

Publication number Publication date
TW201135896A (en) 2011-10-16
US8946742B2 (en) 2015-02-03
JP5389092B2 (ja) 2014-01-15
TW201135884A (en) 2011-10-16
TWI445140B (zh) 2014-07-11
US20110241061A1 (en) 2011-10-06
US20160197014A1 (en) 2016-07-07
CN102214621B (zh) 2014-12-03
US20180350678A1 (en) 2018-12-06
KR101271374B1 (ko) 2013-06-07
US8507940B2 (en) 2013-08-13
US20130302979A1 (en) 2013-11-14
CN102214617B (zh) 2014-05-14
TWI560836B (en) 2016-12-01
JP2011222993A (ja) 2011-11-04
US10497619B2 (en) 2019-12-03
US10049931B2 (en) 2018-08-14
US20110241040A1 (en) 2011-10-06
CN102214617A (zh) 2011-10-12
US20150147834A1 (en) 2015-05-28
KR20110112197A (ko) 2011-10-12
US9287440B2 (en) 2016-03-15

Similar Documents

Publication Publication Date Title
CN102214621B (zh) 半导体装置封装体及其制造方法
US11527465B2 (en) Packages with Si-substrate-free interposer and method forming same
US11469166B2 (en) Packages with Si-substrate-free interposer and method forming same
CN102867777B (zh) 在半导体衬底中形成接地硅通孔
CN103579169B (zh) 半导体封装及半导体封装基座的制造方法
US20150380341A1 (en) Three-Dimensional Semiconductor Device
US20090273002A1 (en) LED Package Structure and Fabrication Method
CN107039380A (zh) 接合结构及其形成方法
CN101213661A (zh) 组件、子组件和制造它们的方法
US20150235935A1 (en) Semiconducor device and method of manufacturing the same
CN102956588B (zh) 具有穿衬底通孔的半导体器件
CN103681618A (zh) 具有通孔的功能性玻璃处理晶片
CN104037305B (zh) 一种低热阻的晶圆级led封装方法及其封装结构
US10943883B1 (en) Planar wafer level fan-out of multi-chip modules having different size chips
KR20220015299A (ko) 액체 냉각 리드를 포함하는 패키징된 반도체 장치 및 이를 형성하는 방법
US20240030187A1 (en) Semiconductor package and method of manufacturing semiconductor package

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20160509

Address after: Hsinchu City, Taiwan, China

Patentee after: Jingyuan Optoelectronics Co., Ltd.

Address before: Hsinchu City, Taiwan, China

Patentee before: Taiwan Semiconductor Manufacturing Co., Ltd.