CN109994586B - 密封的半导体发光器件 - Google Patents

密封的半导体发光器件 Download PDF

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CN109994586B
CN109994586B CN201810908784.6A CN201810908784A CN109994586B CN 109994586 B CN109994586 B CN 109994586B CN 201810908784 A CN201810908784 A CN 201810908784A CN 109994586 B CN109994586 B CN 109994586B
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conductive
layer
wafer
layers
type region
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CN109994586A (zh
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雷继谱
S.施亚夫菲诺
A.H.尼克
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Koninklijke Philips NV
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Koninklijke Philips NV
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Abstract

根据本发明的实施例的方法包括提供半导体器件晶片。半导体器件晶片包括半导体结构，其包括夹在n型区和p型区之间的发光层。半导体器件晶片还包括用于每一个半导体器件的第一和第二金属接触。每一个第一金属接触与n型区直接接触并且每一个第二金属接触与p型区直接接触。该方法还包括形成密封每一个半导体器件的半导体结构的结构。半导体器件晶片附接到支撑衬底晶片。

Description

密封的半导体发光器件
技术领域
本发明涉及包括密封半导体结构的结构的半导体发光器件。
背景技术
包括发光二极管（LED）、谐振腔发光二极管（RCLED）、垂直腔激光二极管（VCSEL）和边缘发射激光器的半导体发光器件是当前可用的最高效的光源之一。当前在能够跨可见光谱进行操作的高亮度发光器件的制造中感兴趣的材料体系包括III-V族半导体，特别是镓、铝、铟和氮的二元、三元和四元合金，其也被称为III族氮化物材料。典型地，通过借由金属-有机化学气相沉积（MOCVD）、分子束外延（MBE）或其它外延技术在蓝宝石、碳化硅、III族氮化物或其它合适的衬底上外延生长不同组成和掺杂浓度的半导体层的堆叠来制作III族氮化物发光器件。堆叠通常包括形成在衬底之上的掺杂有例如Si的一个或多个n型层、形成在一个或多个n型层之上的有源区中的一个或多个发光层以及形成在有源区之上的掺杂有例如Mg的一个或多个p型层。电接触形成在n型区和p型区上。
图1图示了在US 6,876,008中更详细地描述的附接到基座114的发光二极管管芯110。在基座的顶表面和底表面上的可焊接表面之间的电气连接形成在基座内。在其上布置焊料球122-1和122-2的基座顶部上的可焊接区域通过基座内的导电通路电气连接到附接于焊料接头138的基座底部上的可焊接区域。焊料接头138将基座底部上的可焊接区域电气连接到板134。基座114可以是例如具有若干不同区的硅/玻璃复合基座。硅区114-2被形成基座的顶表面和底表面之间的导电通路的金属化物118-1和118-2围绕。诸如ECD保护电路之类的电路可以形成在由金属化物118-1和118-2围绕的硅区114-2中，或者在其它硅区114-3中。其它硅区114-3还可以电气接触管芯110或板134。玻璃区114-1电气隔离不同硅区。焊料接头138可以通过可以是例如介电层或空气的绝缘区135电气隔离。
在图1中所图示的器件中，包括金属化物118-1和118-2的基座114在管芯110附接到基座114之前从管芯110分离地形成。例如，US 6,876,008解释了包括用于许多基座的场所（site）的硅晶片被生长成包括诸如以上提到的ESD保护电路之类的任何期望的电路。在晶片中通过常规掩蔽和蚀刻步骤形成孔。诸如金属之类的导电层形成在晶片之上和孔中。导电层然后可以被图案化。玻璃层然后形成在晶片之上和孔中。玻璃层和晶片的部分被移除以暴露导电层。晶片下侧上的导电层然后可以被图案化并且附加的导电层可以被添加和图案化。一旦晶片下侧被图案化，各个LED管芯110就可以通过互连122物理地和电气地连接到基座上的导电区。换言之，LED 110在被切分成各个二极管之后附接到基座114。
发明内容
本发明的目的是提供一种晶片级方法，其用于将半导体器件晶片附接到支撑衬底晶片以使得每一个器件通过到支撑衬底晶片的附接而被密闭地密封，以降低或消除诸如切分和施加波长转换材料和/或透镜之类的稍后处理步骤期间的污染。
根据本发明的实施例的方法包括提供半导体器件晶片。半导体器件晶片包括半导体结构，其包括夹在n型区和p型区之间的发光层。半导体器件晶片还包括用于每一个半导体器件的第一和第二金属接触。每一个第一金属接触与n型区直接接触并且每一个第二金属接触与p型区直接接触。该方法包括形成密封每一个半导体器件的半导体结构的结构。半导体器件晶片附接到支撑衬底晶片。
附图说明
图1图示了包括安装在基座上的LED的现有技术器件。
图2图示了适合用在本发明的实施例中的半导体LED。
图3图示了形成在半导体LED的金属接触上的厚金属层。
图4图示了在平面化电气绝缘层之后的图3的结构。
图5是图4中的以截面视图图示的结构的平面视图。
图6图示了在形成通孔和形成介电层之后的支撑衬底晶片。
图7图示了在形成导电层并蚀刻以显露通孔顶部处的导电材料之后的图6的结构。
图8图示了在减薄的支撑衬底晶片的顶部上形成介电层之后的图7的结构。
图9图示了在沉积种子层和附加的导电层之后的图8的结构。
图10图示了在移除剩余的种子层之后的图9的结构。
图11图示了在形成介电层之后的支撑衬底晶片。
图12图示了在形成一个或多个导电层之后的图11的结构。
图13图示了在形成通孔和介电层之后的图12的结构。
图14图示了在支撑衬底晶片的底部上形成导电层之后的图13的结构。
图15图示了被键合到支撑衬底晶片的一部分的器件晶片的一部分。
具体实施方式
在本发明的实施例中，半导体发光器件在晶片级工艺中被键合到底座。尽管在以下示例中，半导体发光器件为发射蓝光或UV光的Ⅲ族氮化物LED，但是可以使用诸如激光二极管之类的除LED之外的半导体发光器件，以及由诸如其它Ⅲ-Ⅴ族材料、Ⅲ族磷化物、Ⅲ族砷化物、Ⅱ-Ⅵ族材料、ZnO或基于Si的材料之类的其它材料体系制成的半导体发光器件。
图2图示了适合用在本发明的实施例中的半导体发光器件。图2中所图示的器件仅是可以与本发明的实施例一起使用的器件的一个示例。任何合适的器件可以与本发明的实施例一起使用——本发明的实施例并不受限于图2中所图示的细节。例如，尽管图2图示了倒装芯片器件，但是本发明的实施例可以与其它器件几何结构一起使用并且不限于倒装芯片器件。
图2中所图示的器件可以通过首先在生长衬底10上生长半导体结构来形成，如本领域所已知的那样。生长衬底10可以是任何合适的衬底，诸如例如蓝宝石、SiC、Si、GaN或复合衬底。n型区14可以首先生长并且可以包括不同组成和掺杂浓度的多个层，包括例如诸如缓冲层或成核层之类的准备层，和/或可以为n型或非故意掺杂的被设计成促进生长衬底的移除的层，以及设计用于对发光区高效发射光而言合期望的特定光学、材料或电属性的n型或者甚至p型器件层。发光或者有源区16生长在n型区之上。合适的发光区的示例包括单个厚或者薄发光层，或者包括通过阻挡层分离的多个薄或者厚发光层的多量子阱发光区。p型区18然后可以生长在发光区之上。像n型区那样，p型区可以包括不同组成、厚度和掺杂浓度的多个层，包括非故意掺杂的层，或者n型层。器件中的所有半导体材料的总厚度在一些实施例中小于10
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，并且在一些实施例中小于6
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。
在p型区上形成p接触金属20。p接触金属20可以是反射性的并且可以是多层堆叠。例如，p接触金属可以包括用于做出到p型半导体材料的欧姆接触的层、反射性金属层以及防止或降低反射性金属的迁移的防护金属层。半导体结构然后通过标准光刻操作被图案化并且被蚀刻以移除p接触金属的整个厚度的一部分、p型区的整个厚度的一部分以及发光区的整个厚度的一部分，以形成使在其上形成金属n接触22的n型区14的表面显露的至少一个台面。
图2中所图示的器件的平面视图将看起来类似于图5中所图示的平面视图。n接触22可以具有与以下描述的厚金属层26相同的形状。p接触20可以具有与以下描述的厚金属层28相同的形状。n接触和p接触通过间隙24电气隔离，所述间隙24可以填充有固体、电介质、电气绝缘材料、空气、环境气体或任何其它合适的材料。p和n接触可以是任何合适的形状并且可以以任何合适的方式设置。图案化半导体结构和形成n及p接触对本领域技术人员而言是众所周知的。因此，n和p接触的形状和设置不限于图2和5中所图示的实施例。
尽管图2中图示了单个发光器件，但是要理解图2中所图示的器件形成在包括许多这样的器件的晶片上。在器件晶片上的各个器件之间的区13中，半导体结构可以被向下蚀刻到绝缘层，其可以是作为半导体结构的一部分的绝缘半导体层或者是生长衬底，如图2中所示。
图3和4图示了制备用于键合到支撑衬底晶片（以下描述）的LED器件晶片。包括包含n型区、p型区和发光区的半导体结构以及n和p接触的图2中所图示的LED结构以简化形式通过图3和4中的结构12来表示。
在本发明的实施例中，厚金属层形成在LED的n和p接触上。厚金属层可以在器件晶片被切分成各个器件或较小的器件组之前在晶片级上形成。厚金属层可以在器件晶片被切分之后支撑图2的器件结构，并且在一些实施例中可以在生长衬底的移除期间支撑图2的器件结构。
图3图示了形成在LED 12的n和p接触上的厚金属层。在一些实施例中，首先形成未在图3中示出的基底层。基底层是在其上沉积厚金属层的一个或多个金属层。例如，基底层可以包括其材料被选择用于良好地附着到n和p接触的附着层，以及其材料被选择用于良好地附着到厚金属层的种子层。用于附着层的合适材料的示例包括但不限于Ti、W和诸如TiW之类的合金。用于种子层的合适材料的示例包括但不限于Cu。一个或多个基底层可以通过包括例如溅射或蒸发的任何合适技术来形成。
一个或多个基底层可以通过标准光刻技术图案化以使得基底层仅在要形成厚金属层的地方存在。替代性地，光致抗蚀剂层可以形成在基底层之上并且通过标准光刻技术图案化以在要形成厚金属层的地方形成开口。
厚金属层26和28同时形成在LED 12的n和p接触之上。厚金属层26和28可以是任何合适的金属，诸如例如铜、镍、金、钯、镍-铜合金或其它合金。厚金属层26和28可以通过包括例如镀层的任何合适技术来形成。厚金属层28和30可以在一些实施例中在20
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和500
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之间，在一些实施例中在30
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和200
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之间，并且在一些实施例中在50
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和100
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之间。厚金属层26和28在特别是生长衬底的移除的稍后处理步骤期间支撑半导体结构，并且提供热路径以传导热远离半导体结构，这可以改善器件的效率。
在形成厚金属层26和28之后，电气绝缘材料32形成在晶片之上。电气绝缘材料32填充厚金属层26和28之间的间隙30并且还填充LED 12之间的间隙34。电气绝缘材料32可以可选地布置在厚金属层26和28的顶部之上。电气绝缘材料32被选择成电气隔离金属层26和28并且具有与厚金属层26和28中的（多个）金属的热膨胀系数匹配或相对接近的热膨胀系数。例如，电气绝缘材料32可以在一些实施例中为介电层、聚合物、苯并环丁烯、硅的一个或多个氧化物、硅的一个或多个氮化物、硅树脂或环氧树脂。电气绝缘材料32可以通过任何合适的技术形成，包括例如包覆成型、注模、旋涂和喷涂。包覆成型如下执行：提供尺寸和形状适当设计的模具。模具被填充有液体材料，诸如硅树脂或环氧树脂，其在被固化时形成硬化的电气绝缘材料。模具和LED晶片被结合在一起。模具然后被加热以固化（硬化）电气绝缘材料。模具和LED晶片然后分离，将电气绝缘材料32留在LED之上、LED之间并且填充每一个LED上的任何间隙。在一些实施例中，一个或多个填充物被添加到模制化合物以形成具有最佳的物理和材料属性的复合材料。
图4图示了可选的处理步骤，其中例如通过移除铺盖厚金属层26和28的任何电气绝缘材料来平面化器件。电气绝缘材料32可以通过任何合适技术来移除，包括例如微珠喷砂、飞刀切割、利用刀片切割、研磨、抛光或化学机械抛光。厚金属层26和28之间的电气绝缘材料30不被移除，并且邻近的LED之间的电气绝缘材料34不被移除。
图5是图4中的以截面视图示出的结构的平面视图。图4中所示的截面是在图5中所示的轴线27处获取的。形成在图2中所图示的n接触上的厚金属层26是圆形的，尽管它可以具有任何形状。厚金属层26被形成在图2中所图示的p接触上的厚金属层28所围绕。厚金属层26和28通过围绕厚金属层26的电气绝缘材料30电气隔离。电气绝缘材料34围绕器件。
从图2、3和4中所图示的器件晶片的制备分离地制备支撑衬底晶片。图6、7、8、9和10图示了根据一些实施例的支撑衬底晶片的制备。图11、12、13和14图示了根据替代性实施例的支撑衬底的制备。
支撑衬底晶片包括主体40，如图6中所示。主体40可以是例如Si、Ge、GaAs或任何其它合适材料。在主体40中形成通孔。一些通孔42被放置成与电气连接到n型区的器件晶片上的金属层对准。一些通孔44被放置成与电气连接到p型区的器件晶片上的金属层对准。在形成通孔之后，介电层46形成在主体40的底表面上，包括在通孔的内侧中。介电层46可以是任何合适材料，诸如例如通过热生长或等离子体增强化学气相沉积（PECVD）形成的硅的氧化物，或者通过PECVD形成的硅的氮化物。
在图7中，导电层形成在主体40的底表面上的介电层46之上及通孔42和44中。导电层被图案化以形成通孔42中的导电层48和通孔44中的导电层50。导电层48和50通过暴露介电层46的间隙从彼此电气隔离。导电层可以是例如诸如铜或金之类的金属。导电层可以通过首先在主体的整个底表面之上形成种子层（例如通过溅射），然后图案化以移除导电层48和50之间的区中的种子层来形成。较厚金属层然后例如通过镀层形成在种子层的剩余部分上。
在形成导电层48和50之后，主体40从顶表面蚀刻以暴露通孔42和44的顶部处的导电层48a和50a。主体40可以通过任何合适技术进行减薄，包括湿法或干法蚀刻或者诸如研磨之类的机械技术。尽管图7图示了具有平坦顶表面的结构，但是在一些实施例中主体40可以被蚀刻到导电层48a和50a的顶部以下。
在图8中，介电层52形成在主体40的顶部之上、通过参照图7描述的减薄而暴露的表面之上。介电层52可以是任何合适材料，诸如例如通过热生长或PECVD形成的硅的氧化物，或者通过PECVD形成的硅的氮化物。图8图示了热生长的介电层52，其可以与导电层48a和50a自对准以使得形成平坦的顶表面，假设表面在图7中所图示的减薄之后是平坦的。如果介电材料例如通过PECVD沉积，介电材料可以沉积在通孔42和44的顶部处的导电层48a和50a之上。沉积在导电层48a和50a之上的介电材料可以通过常规光刻和蚀刻步骤来移除。顶表面可以如图8中所图示的是平坦的，尽管它不需要如此。
在图9中，一个或多个导电层形成在主体40的顶表面上。一个或多个导电层可以是通过任何合适工艺形成的任何合适材料。在图9中，导电层包括铜层、镍层和金/锡层。导电层与通孔42和44的顶部处的导电层48a和50a直接接触。导电层可以被成形以与图5中以平面视图示出的形成在器件晶片上的厚金属层26和28对准。为了形成图9中所图示的导电层，铜种子层54形成在主体40的顶部之上。种子层可以被图案化以使得光致抗蚀剂57形成在其中不会形成导电层的区域之上，诸如在提供电气连接到通孔42中的金属48的导电层与电气连接到通孔44中的金属50的导电层之间的电气隔离的间隙55中。厚铜层然后例如通过镀层形成，随后是通过镀层形成的镍层，随后是通过以4:1的厚度比顺序地镀金和锡形成的金/锡层。
光致抗蚀剂57然后被移除，如图10中所示，留下将导电层56、60和64从导电层58、62和66电气隔离的间隙55。铜层56、镍层60和金/锡层64形成在通孔42中的导电层48之上。铜层58、镍层62和金/锡层66形成在通孔44中的导电层50之上。
在光致抗蚀剂从间隙55移除之后，在图9中形成的种子层54保留在形成于通孔42之上的铜、镍和金/锡层与形成于通孔44之上的那些层之间的间隙55中。间隙55中的种子层可以通过蚀刻被移除，如图10中所图示的，使得介电层52暴露在间隙55的底部中。结构可以在提升的温度下被退火，以使镀的金和锡层形成金/锡共熔合金。金/锡共熔合金稍后被用作键合层以将支撑衬底晶片附接到器件晶片。
图11、12、13和14图示了用于制备支撑衬底晶片的替代性方法。相似结构可以是相同材料的并且通过以上参照图6、7、8、9和10描述的相同技术形成。在图11中，电介质52形成在主体40的顶表面之上。介电层52可以是任何合适材料，诸如例如通过热生长或PECVD形成的硅的氧化物，或者通过PECVD形成的硅的氮化物。
在图12中，导电层形成在主体40的顶表面上，并且被图案化。如以上参照图9所描述的，一个或多个导电层可以是通过任何合适工艺形成的任何合适材料。在如图9的图12中，导电层包括铜层、镍层和金/锡层。为了形成图9中所图示的导电层，铜种子层54形成在主体40的顶部之上。种子层可以被图案化以使得光致抗蚀剂形成在其中不会形成导电层的区域之上，诸如在稍后形成的通孔42和44之间的提供电气隔离的间隙55中。厚铜层然后例如通过镀层形成，随后是通过镀层形成的镍层，随后是通过以4:1的厚度比顺序地镀金和锡或者通过镀适当组成的金/锡合金形成的金/锡层。然后移除光致抗蚀剂，结果得到图12中所图示的结构。铜层56、镍层60和金/锡层64形成在稍后形成的通孔42的区中之上。铜层58、镍层62和金/锡层66形成在稍后形成的通孔44的区中。种子层54保留在导电金属层之间的区域中。
在图13中，通孔42和44通过常规图案化和蚀刻步骤形成。通孔42和44形成在主体40的底表面上并且朝向主体40的顶表面延伸。通孔42和44延伸通过介电层52分别到导电层56和58的底部。通常为诸如铜之类的金属的导电层56和58充当用于形成通孔42和44的蚀刻步骤的蚀刻停止层。
介电层46形成在主体40的底表面上及通孔42和44中。介电层46可以是任何合适的材料，诸如例如通过热生长或PECVD形成的硅的氧化物，或者通过PECVD形成的硅的氮化物。在介电层46形成之后，导电层形成在主体40的底表面上及通孔42和44中。导电层48与通孔42顶部处的铜种子层54直接接触。导电层50与通孔44顶部处的铜种子层54直接接触。导电层48和50通过暴露介电层46的间隙49从彼此电气隔离。导电层可以是例如诸如铜或金之类的金属。导电层可以通过首先在主体的整个底表面之上形成种子层（例如通过溅射），然后图案化以形成导电层48和50之间的区中的光致抗蚀剂层来形成。较厚金属层然后例如通过镀层形成在未被光致抗蚀剂覆盖的种子层的部分上。移除光致抗蚀剂，然后移除较厚金属层48和50之间的间隙49中的种子层，例如通过蚀刻。同样地，种子层54通过蚀刻从间隙55移除以将金属堆叠56、60、64从金属堆叠52、58、62隔离。结构可以例如在至少200℃的温度下被退火。
图15图示了诸如图4中所图示的器件之类的器件的晶片70的一部分，其附接到诸如图10和14中所图示的支撑衬底之类的支撑衬底的晶片72。晶片70和72通过将支撑衬底晶片72顶部上的金属区64、66与器件晶片70底部上的金属区26、28对准，然后加热结构以使金属层64和66回流而键合到一起。金属层64和66可以具有与金属区26和28相同的形状，如图5中所示。区75连接到图15中所图示的平面以外的导电层50。在一些实施例中，金属层64和66是金/锡共熔合金，尽管可以使用足够导电并适于键合的任何材料。在一些实施例中，绝缘材料30、34是在金属层64和66回流时金属层64和66将不会润湿的材料。因为金属层64和66将不会润湿器件晶片70底部上的绝缘材料30、34，所以填充有环境气体的间隙74形成在金属层64和66之间。而且，因为晶片72上的金属层64和66将仅润湿晶片70上的金属区26和28而非绝缘材料30和34，所以金属层64和66以及金属区26和28不必具有精确相同的形状并且无需精确对准，如图15中所示。
在图15中图示了两个器件，尽管要理解图15中所图示的结构跨两个晶片重复。在键合之后，晶片可以被切分，这在位置76处将两个器件分离。在图2中更详细地图示为半导体层14、16和18并且在图15中以简化形式图示的器件晶片70上的每一个半导体结构71在半导体结构71的顶部上被生长衬底10并且在底部上被金属区26和28及绝缘材料30和34完全围封和密封。图2中所图示的n和p接触22和20也通过密封得以保护。如以上所描述的，密封通过在半导体结构71被连接到生长衬底10时发生的晶片水平处理步骤来形成。在键合到图15中所图示的支撑衬底晶片72期间，没有材料能够接触半导体结构71。特别地，在键合到支撑衬底72期间，由金属区26、28和绝缘材料30、34形成的密封防止金属键合层64、66或者任何其它材料接触半导体结构71。
在一些实施例中，在键合到支撑衬底72之后，生长衬底10从图15中所图示的结构移除。生长衬底可以通过任何合适技术移除，包括例如激光剥离、蚀刻、诸如研磨之类的机械技术或者技术的组合。在一些实施例中，生长衬底是蓝宝石并且通过晶片级激光剥离来移除。由于蓝宝石衬底不需要在移除之前减薄并且未被切分，因此它可以再用作生长衬底。在一些实施例中，生长衬底10仅被减薄，使得生长衬底的一部分保留在最终器件上。在一些实施例中，整个生长衬底10保留在最终器件上。
在一些实施例中，通过移除生长衬底而暴露的半导体结构表面（典型地n型区14的表面（图2中所示））可以可选地例如通过光电化学蚀刻而被减薄和粗糙化。
器件晶片然后被切分成各个LED或者LED组。各个LED或者LED组可以通过锯切、划片、断裂、切割或者以其它方式在位置76处分离相邻的LED而分离，如图15中所示。在一些实施例中，生长衬底10在切分之后而不是之前被减薄或移除。
诸如滤波器、透镜、二向色材料或波长转换材料之类的一个或多个可选结构可以在切分之前或之后形成在LED之上。可以形成波长转换材料以使得由发光器件发射的且入射在波长转换材料上的光的全部或仅一部分可以被波长转换材料所转换。由发光器件发射的未经转换的光可以是最终光谱的一部分，尽管它不需要如此。常见组合的示例包括组合有黄光发射波长转换材料的蓝光发射LED、组合有绿和红光发射波长转换材料的蓝光发射LED、组合有蓝和黄光发射波长转换材料的UV发射LED以及组合有蓝、绿光和红光发射波长转换材料的UV发射LED。可以添加发射其它颜色光的波长转换材料以定制从器件发射的光谱。波长转换材料可以是常规磷光体颗粒、量子点、有机半导体、Ⅱ-Ⅳ或Ⅲ-Ⅴ族半导体、Ⅱ-Ⅳ或Ⅲ-Ⅴ族半导体量子点或纳米晶体、染料、聚合物，或者诸如GaN之类的发光材料。可以使用任何合适的磷光体或其它波长转换材料。
厚金属层26和28以及填充厚金属层之间和相邻LED之间的间隙的电气绝缘材料在键合、衬底移除、切分和其它处理期间为半导体结构提供机械支撑。由厚金属层26和28以及绝缘材料30和34形成的半导体结构周围的密封在键合和其它处理步骤期间保护半导体结构免受污染。
已经详细描述了本发明，本领域技术人员将了解，考虑到本公开，可以在不脱离于本文所描述的发明概念的精神的情况下对本发明做出修改。因此，不旨在将本发明的范围限制于所图示和描述的特定实施例。

Claims (11)

1.一种器件，包括：
半导体结构，所述半导体结构包括布置在n型区和p型区之间的Ⅲ族氮化物发光层；
金属层，所述金属层具有形成在其中并且填充有绝缘材料的开口，所述开口将金属层分离成从第二部分电气隔离的第一部分，第一部分耦合到n型区并且第二部分耦合到p型区；
多个导电堆叠，每一个导电堆叠的第一表面接触金属层的与半导体结构相对的表面，在每一个导电堆叠之间定位相应间隙；以及
与每一个导电堆叠的与第一表面相对的第二表面直接接触的主体，
其中导电堆叠之间的间隙填充有环境气体，每个间隙的底部包括不可被导电堆叠润湿的表面。
2.权利要求1的器件，其中绝缘材料完全覆盖半导体结构的所有暴露表面。
3.权利要求1的器件，其中将金属层键合到所述多个导电堆叠。
4.权利要求1的器件，其中主体包括形成在其中的多个通孔，所述多个通孔中的每一个与所述多个导电堆叠中的一个对准。
5.权利要求4的器件，其中每一个通孔装衬有导电材料，所述导电材料还装衬主体的不邻近所述多个导电堆叠的外表面。
6.权利要求5的器件，其中装衬每一个通孔的导电材料耦合到所述多个导电堆叠中的相应一个。
7.权利要求1的器件，其中每一个导电堆叠包括多种不同导电材料的堆叠。
8.权利要求1的器件，其中每一个导电堆叠包括依次堆叠的铜层、镍层和金/锡共融合金层。
9.权利要求1的器件，其中导电堆叠以及金属层的第一和第二部分全部具有相同形状。
10.权利要求1的器件，其中导电堆叠以及金属层的第一和第二部分具有不同形状。
11.权利要求1的器件，其中相对的导电堆叠以及金属层的第一或第二部分未精确对准。
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