TWI397109B - 形成由半導體基板支撐之結構的方法 - Google Patents

形成由半導體基板支撐之結構的方法 Download PDF

Info

Publication number
TWI397109B
TWI397109B TW098115035A TW98115035A TWI397109B TW I397109 B TWI397109 B TW I397109B TW 098115035 A TW098115035 A TW 098115035A TW 98115035 A TW98115035 A TW 98115035A TW I397109 B TWI397109 B TW I397109B
Authority
TW
Taiwan
Prior art keywords
features
altered
regions
photoresist
acid
Prior art date
Application number
TW098115035A
Other languages
English (en)
Other versions
TW201005801A (en
Inventor
Anton Devilliers
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of TW201005801A publication Critical patent/TW201005801A/zh
Application granted granted Critical
Publication of TWI397109B publication Critical patent/TWI397109B/zh

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

形成由半導體基板支撐之結構的方法
本發明係關於形成由半導體基板支撐之結構的方法。
積體電路製造可涉及在半導體基板上方形成經光微影圖案化遮罩，繼之以藉由一或多個蝕刻而將圖案自遮罩轉印至一或多種材料中。
經光微影圖案化遮罩可包含任何合適輻射可成像材料，諸如，聚醯亞胺或光阻。圖案係藉由以下操作而形成於輻射可成像材料中：使材料經受經圖案化光化輻射(例如，紫外光)，使得輻射可成像材料之一些部分暴露至輻射，而其他部分未暴露至輻射。經暴露部分或未經暴露部分中之任一者可藉由適當顯影溶液相對於經暴露部分及未經暴露部分中之另一者而經選擇性地移除，藉此在輻射可成像材料中產生圖案。
積體電路製造之持續目標係產生較小結構。可在試圖藉由傳統光微影處理來產生較小結構時遇到許多困難，其在於：可藉由光微影製程而達成之最小尺寸係由該製程中所利用之光化輻射之波長強加。現代製程正逼近由光化輻射之物理性質所強加之可按比例調整能力極限。
將需要開發形成用於積體電路製造之圖案的新方法，其可延伸可按比例調整能力極限。
參看圖1至圖10來描述實例實施例。
參看圖1，此圖說明半導體構造10之一部分。該構造包括基底或基板12，其可(例如)包含藉由本底p型摻雜劑而輕度摻雜之單晶矽、基本上由藉由本底p型摻雜劑而輕度摻雜之單晶矽組成或由藉由本底p型摻雜劑而輕度摻雜之單晶矽組成。術語「半導電基板」及「半導體基板」意謂包含半導電材料之任何構造，包括(但不限於)諸如半導電晶圓之塊體半導電材料(其上單獨地或組合地包含其他材料)及半導電材料層(單獨地或組合地包含其他層)。術語「基板」指代包括(但於限於)上文所描述之半導電基板的任何支撐結構。
複數種材料14、16及18係在基底12上方。該等材料可包含可在形成積體電路時利用之任何組合物。因此，材料中之一或多者可包含電絕緣組合物(例如，二氧化矽、氮化矽、硼磷矽玻璃，等等)；材料中之一或多者可包含導電組合物(例如，金屬、金屬氮化物、金屬矽化物、經導電摻雜矽，等等)；及/或材料中之一或多者可包含半導體組合物(例如，矽、鍺，等等)。材料14、16及18可包含任何合適厚度。
經光微影圖案化輻射可成像材料20係在材料18上方。材料20可(例如)包含光阻、基本上由光阻組成或由光阻組成。材料20經圖案化為複數個分離特徵22、24、26、28及30；且此等特徵係藉由間隙21、23、25及27而彼此間隔開。雖然顯示五個分離特徵，但可利用任何合適數目之特徵。通常，將存在至少兩個分離特徵，且因此，通常將存在至少一間隙。
在所顯示之橫截面視圖中，特徵中之每一者具有一對相對側壁17(僅針對特徵22而進行標記)及一頂部19(僅針對特徵22而進行標記)。
參看圖2，在特徵22、24、26、28及30上且在特徵之間的間隙21、23、25及27內(或換言之，跨越特徵之間的間隙21、23、25及27)形成材料40。材料40可被稱為第二材料以使其與輻射可成像材料20區分。
材料40可類似於作為所謂的「AZ R」材料而購自Clariant International,Ltd.之材料種類，諸如，稱為AZ R200TM 、AZ R500TM 及AZ R600TM 之材料。
「AZ R」材料含有在暴露至自化學放大型抗蝕劑所釋放之酸後即交聯的有機組合物。具體而言，可跨越光阻而塗佈「AZ R」材料，且隨後可在自約100℃至約120℃之溫度下烘烤抗蝕劑以使酸自抗蝕劑擴散且進入材料中以在材料之鄰近於抗蝕劑之區域內形成化學交聯。材料之相鄰於抗蝕劑之部分因此相對於材料之未充分鄰近於抗蝕劑之其他部分而經選擇性地硬化。材料可接著暴露至可相對於經硬化部分而選擇性地移除未經硬化部分之條件。此移除可利用(例如)含於離子化水中之10%異丙醇或Clariant International,Ltd.之以「SOLUTION CTM 」銷售的溶液來實現。利用「AZ R」材料之製程有時被認為係RELACS(由化學微縮輔助之解析度增強微影(Resolution Enhancement Lithography Assisted by Chemical Shrink))製程之實例。
「AZ R」材料之問題可為：其組成與光阻夠相近，使得難以相對於經硬化「AZ R」材料而選擇性地移除光阻。
材料40可與「AZ R」材料類似之處在於：材料40可包含類似或等同於有機組合物，該有機組合物在暴露至在輻射可成像材料經烘烤時自該材料所釋放之一或多種物質(例如，酸)後即經變更(例如，形成交聯)。然而，不同於「AZ R」材料，材料40亦可含有分散於有機組合物中之一或多種組份，該一或多種組份經提供以相對於輻射可成像材料(例如，光阻)而化學地改變材料40，使得輻射可成像材料可相對於材料40而經選擇性地移除。分散於材料40之有機組合物中之組份可包括鈦、碳、氟、溴、矽及鍺中之一或多者。分散於有機組合物中之碳可為碳化物化合物之一部分，使得其化學地不同於有機組合物之塊體碳。氟及溴可(例如)由氫氟酸及氫溴酸包含。在一些實施例中，分散於材料40之有機組合物中之組份包括一或多種無機組份，諸如，矽、鍺、金屬(例如，鈦、鎢、鉑，等等)，及/或含金屬化合物(例如，金屬氮化物、金屬矽化物，等等)。
材料40之類似於「AZ R」材料之組份可被稱為「AZ R」型組合物。因此，在一些實施例中，可認為材料40具有分散於有機「AZ R」型組合物中之一或多種無機組份。
材料40可藉由包括(例如)旋轉塗佈之任何合適方法而形成於特徵22、24、26、28及30上且形成於其之間。
參看圖3，使構造10接受導致至少一物質自特徵22、24、26、28及30之材料20擴散至材料40之鄰近於此等特徵之區域中的條件。該等物質變更材料40以鄰近於特徵22、24、26、28及30而形成經變更區域42，且留下未經變更區域44作為材料40之較不鄰近於特徵之片段。經變更區域在圖3中係藉由交叉影線表示以強調不同區域42及44。經變更區域可一起視為界定材料40之經變更部分，且未經變更區域可一起視為界定材料40之未經變更部分。
在一些實施例中，材料20包含化學放大型光阻，且自此光阻所擴散之物質為酸。藉由在至少約100℃之溫度下烘烤構造10而引起光阻釋放酸。酸在材料40之「AZ R」型組合物內形成交聯。交聯量及交聯自光阻特徵伸展之距離可藉由修改烘烤時間及烘烤溫度中之一者或兩者來調整。
材料40之未經變更區域44相對於經變更區域42係可選擇性地移除，且圖4顯示在已移除未經變更區域之後的構造10。此移除可利用異丙醇及/或SOLUTION CTM 來實現。如上文所論述，材料40可包含分散於「AZ R」型組合物中之各種額外組份(例如，金屬、二氧化矽，等等)。在一些實施例中，額外組份可隨著移除材料40之未經變更區域而簡單地清洗掉。在其他實施例中，此等額外組份可藉由對於額外組份為特定之溶劑來移除。舉例而言，若將二氧化矽用作材料40之組份，則可在材料40之未經變更區域之移除期間利用氫氟酸以確保除了未經變更區域之「AZ R」型組合物以外亦移除未經變更區域之二氧化矽。
材料40之經變更區域42形成在特徵22、24、26、28及30之頂部19及側壁17上方延伸的頂蓋。在一些實施例中，具有與之相關聯之頂蓋之特徵可用於圖案化下伏材料14、16及18中之一或多者。在其他實施例中，可能需要選擇性地移除輻射可成像材料20以留下僅包含材料40之經變更區域42的結構。參看圖5及圖6來描述用於選擇性地移除輻射可成像材料之方法。
參看圖5，自特徵22、24、26、28及30之頂部19上方移除材料40，同時沿著此等特徵之側壁17而留下材料40。材料40自特徵之頂部上方之移除可利用包括(例如)定向物理蝕刻及/或化學機械拋光(CMP)之任何合適處理來實現。
參看圖6，移除輻射可成像材料20(圖5)以在材料18上方留下材料40之經變更區域42的結構50、52、54、56、58、60、62、64、66及68。此等結構相對於輻射可成像材料20之特徵22、24、26、28及30(圖1)之原始間距為雙重間距。
材料20(圖5)可歸因於包含除了「AZ R」型組合物以外之一或多種組份的此等經變更區域而相對於材料40之經變更區域42經選擇性地移除。舉例而言，若額外組份為耐氧化的，則可利用灰化或另一氧化製程來移除光阻。此製程可歸因於「AZ R」型組合物中之一些的移除而弱化材料40之區域42。然而，額外組份可形成在自材料40之區域42移除「AZ R」型組合物中之至少一些之後保持的基質。
材料40之區域42的結構可用作遮罩。舉例而言，結構可在材料18之摻雜期間用以保護材料之一區域，而另一區域經摻雜；及/或結構可在蝕刻至下伏材料14、16及18中之一或多者中的一或多個期間用以界定待在此等下伏材料中形成之圖案。
圖7顯示在結構50、52、54、56、58、60、62、64、66及68在穿過下伏材料14、16及18之蝕刻期間已用作遮罩之後的構造10。
圖2至圖5之處理利用材料40之薄保形塗佈(其中材料40為可為「AZ R」型組合物之材料)。在其他實施例中，材料40之厚層可經形成以填充間隙21、23、25及27且覆蓋特徵22、24、26、28及30。此等其他實施例之實例顯示於圖11中，其中顯示在圖1之處理階段之後的處理階段時的構造10。圖11之結構係在類似於圖3之處理階段的處理階段時，且因此，材料40係在經變更區域42與未經變更區域44之中進行再分。在後續處理中，未經變更區域44及經變更區域42之上部部分可經移除以形成圖12之構造。圖12之構造等同於圖5之構造。未經變更區域44及經變更區域42之上部部分的移除可包含類似於圖4及圖5之步驟的兩個分離步驟，或可在單一步驟中進行。
圖6及圖7之結構50、52、54、56、58、60、62、64、66及68在所顯示之橫截面視圖中係呈基座之形式。此等基座可為相對於所顯示之橫截面視圖而延伸至頁面中且延伸出頁面之壁(或線)的一部分。無論如何，基座為非管狀的。在其他實施例中，類似於圖1至圖6之方法的方法可用以形成管狀結構。圖8至圖10說明可用於形成管狀結構之實施例的實例。類似編號將如同以上用以描述圖1至圖6一般用以描述圖8至圖10。
參看圖8，此圖顯示在類似於圖1之處理階段之處理階段時之構造10的三維視圖。然而，不同於圖1，輻射可成像材料20經顯示成圖案化為圓柱。
緊接著參看圖9，顯示在圖8之處理階段之後且類似於圖5之處理階段之處理階段時的構造10。材料40已圍繞輻射可成像材料20而形成且經受形成經變更區域42之處理。隨後，材料40已自輻射可成像材料20上方經移除以留下經變更區域42作為圍繞圓柱狀輻射可成像材料20而延伸之管路。
緊接著參看圖10，移除材料20以留下材料40之經變更區域42的結構70，其中結構70為在材料18上方之管路(換言之，中空圓柱)。在後續處理(未圖示)中，管路可用以界定用於至下伏材料中之摻雜及/或蝕刻的遮罩圖案。所顯示之管路可表示同時形成於半導體基底上方之複數個管路。
圖1至圖10之處理可用於許多積體電路製造應用中之任一者中。舉例而言，該處理可用以形成快閃記憶體或動態隨機存取記憶體(DRAM)。該處理可用於在小於35奈米(nm)之範圍內成像；諸如，自約10nm至小於35nm之範圍內成像。
10．．．半導體構造
12．．．基底/基板
14．．．材料
16．．．材料
17．．．側壁
18．．．材料
19．．．頂部
20．．．輻射可成像材料
21．．．間隙
22．．．特徵
23．．．間隙
24．．．特徵
25．．．間隙
26．．．特徵
27．．．間隙
28．．．特徵
30．．．特徵
40．．．材料
42．．．經變更區域
44．．．未經變更區域
50．．．結構
52．．．結構
54．．．結構
56．．．結構
58．．．結構
60．．．結構
62．．．結構
64．．．結構
66．．．結構
68．．．結構
70．．．結構
圖1至圖7為在一實施例之各種製程階段時所顯示之半導體晶圓構造之一部分的圖解橫截面視圖。
圖8至圖10為在一實施例之各種製程階段時所顯示之半導體晶圓構造之一部分的三維視圖。
圖11及圖12為圖1至圖7中在一實施例之各種製程階段時所顯示之部分的視圖。圖11之處理階段跟隨圖1之處理階段，且圖12之處理階段跟隨圖11之處理階段。
10．．．半導體構造
12．．．基底/基板
14．．．材料
16．．．材料
18．．．材料
40．．．材料
42．．．經變更區域
50．．．結構
52．．．結構
54．．．結構
56．．．結構
58．．．結構
60．．．結構
62．．．結構
64．．．結構
66．．．結構
68．．．結構

Claims (13)

  1. 一種形成結構之方法，其包含：在一半導體基板上形成一輻射可成像材料；將該輻射可成像材料光微影圖案化為至少兩個分離特徵；該等分離特徵之間具有一或多個間隙；在該至少兩個分離特徵上且跨越該至少兩個分離特徵之間的該一或多個間隙形成一第二材料；烘烤在其上具有該第二材料之該等特徵以釋放變更該第二材料之至少一物質；該未經變更第二材料相對於該經變更第二材料係可選擇性地移除，且該等特徵相對於該經變更材料係可選擇性地移除；該烘烤將該至少一物質自該等特徵轉移至該第二材料之鄰近於該等特徵之區域中以變更該等區域，同時留下該第二材料之其他區域未經變更；相對於該第二材料之該等經變更區域而選擇性地移除該第二材料之該等未經變更區域；及相對於該第二材料之該等經變更區域而選擇性地移除該等特徵以留下該第二材料之該等經變更區域的至少一結構，其中該第二材料包含分散於一有機組合物中之一或多種無機組份，該有機組合物在暴露至酸後即為可交聯的，其中自該等特徵所釋放之該至少一物質包括酸，且其中該等區域之該變更包含在暴露至自該等特徵所釋放之該酸後即在該有機組合物內形成交聯。
  2. 如請求項1之方法，其中該一或多種無機組份包括矽。
  3. 如請求項1之方法，其中該一或多種無機組份至少包括金屬。
  4. 如請求項1之方法，其中：該第二材料包含一混合物，該混合物包括分散於一有機組合物中之一或多種組份，該有機組合物在暴露至酸後即為可交聯；自該等特徵所釋放之該至少一物質包括酸；該等區域之該變更包含在暴露至自該等特徵所釋放之該酸後即在該有機組合物內形成交聯；且該一或多種組份包括鈦、碳、氟、溴、矽及鍺中之一或多者。
  5. 如請求項1之方法，其中該半導體基板包含一基底半導體材料及在該基底半導體材料上之一或多種材料；且進一步包含在蝕刻至該一或多種材料中之至少一者期間利用該第二材料之該等經變更區域的該至少一結構作為一遮罩。
  6. 一種形成由一半導體基板支撐之結構的方法，其包含：在一半導體基板上形成至少兩個分離光阻特徵；在該至少兩個光阻特徵上且跨越該至少兩個光阻特徵之間的一或多個間隙形成一材料；該等光阻特徵經組態以釋放變更該材料之至少一物質；該未經變更材料相對於該經變更材料係可選擇性地移除，且該等光阻特徵相對於該經變更材料係可選擇性地移除； 自該等光阻特徵釋放該至少一物質且進入該材料之鄰近於該等光阻特徵之區域中以變更該等區域；該等區域藉此變為該材料之經變更之一部分，而該材料之另一部分保持未經變更；相對於該材料之該經變更部分而選擇性地移除該材料之該未經變更部分；及相對於該材料之該經變更部分而選擇性地移除該等光阻特徵以在該半導體基板上方留下該材料之該經變更部分的至少一結構，其中該材料包含分散於一有機組合物中之一或多種無機組份，該有機組合物在暴露至酸後即為可交聯，其中自該等光阻特徵所釋放之該至少一物質包括酸，且其中該等區域之該變更包含在暴露至自該等光阻特徵所釋放之該酸後即在該有機組合物內形成交聯。
  7. 如請求項6之方法，其中該一或多種無機組份包括矽。
  8. 如請求項6之方法，其中該一或多種無機組份至少包括金屬。
  9. 如請求項6之方法，其中：該材料包含一混合物，該混合物包括分散於一有機組合物中之一或多種組份，該有機組合物在暴露至酸後即為可交聯；自該等光阻特徵所釋放之該至少一物質包括酸；該等區域之該變更包含在暴露至自該等光阻特徵所釋放之該酸後即在該有機組合物內形成交聯；且 該一或多種組份包括鈦、碳、氟、溴、矽及鍺中之一或多者。
  10. 如請求項6之方法，其中該半導體基板包含一基底半導體材料及在該基底半導體材料上之一或多種材料；且進一步包含在蝕刻至該一或多種材料中之至少一者期間利用該材料之該經變更部分的該至少一結構作為一遮罩。
  11. 如請求項6之方法，其中該材料之該經變更部分的該至少一結構包含一管路。
  12. 如請求項6之方法，其中該材料之該經變更部分的該至少一結構包含複數個非管狀基座。
  13. 如請求項6之方法，其中該材料之該經變更部分延伸至該等光阻特徵上；且進一步包含：在該相對於該材料之該經變更部分而選擇性地移除該光阻特徵之前，自該等光阻特徵上方移除該材料之該經變更部分，同時沿著該等光阻特徵之側壁而留下該材料之該經變更部分。
TW098115035A 2008-05-22 2009-05-06 形成由半導體基板支撐之結構的方法 TWI397109B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/125,725 US10151981B2 (en) 2008-05-22 2008-05-22 Methods of forming structures supported by semiconductor substrates

Publications (2)

Publication Number Publication Date
TW201005801A TW201005801A (en) 2010-02-01
TWI397109B true TWI397109B (zh) 2013-05-21

Family

ID=41340762

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098115035A TWI397109B (zh) 2008-05-22 2009-05-06 形成由半導體基板支撐之結構的方法

Country Status (6)

Country Link
US (1) US10151981B2 (zh)
EP (1) EP2279517B1 (zh)
KR (1) KR20110008247A (zh)
CN (1) CN102037543B (zh)
TW (1) TWI397109B (zh)
WO (1) WO2009142869A2 (zh)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8852851B2 (en) 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US7989307B2 (en) 2008-05-05 2011-08-02 Micron Technology, Inc. Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same
US10151981B2 (en) 2008-05-22 2018-12-11 Micron Technology, Inc. Methods of forming structures supported by semiconductor substrates
US8247302B2 (en) 2008-12-04 2012-08-21 Micron Technology, Inc. Methods of fabricating substrates
US8796155B2 (en) 2008-12-04 2014-08-05 Micron Technology, Inc. Methods of fabricating substrates
US8273634B2 (en) 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
US9640396B2 (en) * 2009-01-07 2017-05-02 Brewer Science Inc. Spin-on spacer materials for double- and triple-patterning lithography
US8268543B2 (en) 2009-03-23 2012-09-18 Micron Technology, Inc. Methods of forming patterns on substrates
US9330934B2 (en) 2009-05-18 2016-05-03 Micron Technology, Inc. Methods of forming patterns on substrates
US8518788B2 (en) 2010-08-11 2013-08-27 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8455341B2 (en) 2010-09-02 2013-06-04 Micron Technology, Inc. Methods of forming features of integrated circuitry
US8575032B2 (en) 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
US9177794B2 (en) 2012-01-13 2015-11-03 Micron Technology, Inc. Methods of patterning substrates
CN103390544B (zh) * 2012-05-11 2016-03-30 中芯国际集成电路制造(上海)有限公司 用于形成硬掩膜层的方法
US9005877B2 (en) * 2012-05-15 2015-04-14 Tokyo Electron Limited Method of forming patterns using block copolymers and articles thereof
US8629048B1 (en) 2012-07-06 2014-01-14 Micron Technology, Inc. Methods of forming a pattern on a substrate
CN103400750A (zh) * 2013-08-19 2013-11-20 中国科学院高能物理研究所 一种在硅衬底表面涂覆光刻胶的方法
KR102394994B1 (ko) 2013-09-04 2022-05-04 도쿄엘렉트론가부시키가이샤 유도 자기 조립용 화학 템플릿을 생성하기 위한 경화 포토레지스트의 자외선을 이용한 박리
US10256098B2 (en) 2015-10-29 2019-04-09 Micron Technology, Inc. Integrated assemblies containing germanium
US9947597B2 (en) 2016-03-31 2018-04-17 Tokyo Electron Limited Defectivity metrology during DSA patterning
US10566194B2 (en) 2018-05-07 2020-02-18 Lam Research Corporation Selective deposition of etch-stop layer for enhanced patterning
US10818508B2 (en) * 2018-10-17 2020-10-27 Nanya Technology Corporation Semiconductor structure and method for preparing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6383952B1 (en) * 2001-02-28 2002-05-07 Advanced Micro Devices, Inc. RELACS process to double the frequency or pitch of small feature formation
US20050130068A1 (en) * 2003-11-21 2005-06-16 Takehiro Kondoh Pattern forming method and method for manufacturing a semiconductor device
US20080044770A1 (en) * 2006-08-17 2008-02-21 Fujitsu Limited Process for forming resist pattern, semiconductor device and manufacturing method for the same

Family Cites Families (250)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5646531A (en) 1979-09-25 1981-04-27 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS58157135A (ja) 1982-03-15 1983-09-19 Matsushita Electric Ind Co Ltd パタ−ン形成方法
JPS59211231A (ja) 1983-05-16 1984-11-30 Matsushita Electric Ind Co Ltd パタ−ン形成方法
BE900156A (fr) 1984-07-13 1985-01-14 Itt Ind Belgium Procede pour superposer deux couches de vernis photosensibles positifs.
JPS6435916A (en) 1987-07-31 1989-02-07 Hitachi Ltd Formation of fine pattern
US4910168A (en) 1988-05-06 1990-03-20 Mos Electronics Corporation Method to reduce silicon area for via formation
JPH01292829A (ja) 1988-05-19 1989-11-27 Mitsubishi Electric Corp 半導体装置の製造方法
US5008207A (en) 1989-09-11 1991-04-16 International Business Machines Corporation Method of fabricating a narrow base transistor
JPH03270227A (ja) 1990-03-20 1991-12-02 Mitsubishi Electric Corp 微細パターンの形成方法
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
US5013680A (en) 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5047117A (en) 1990-09-26 1991-09-10 Micron Technology, Inc. Method of forming a narrow self-aligned, annular opening in a masking layer
US5420067A (en) 1990-09-28 1995-05-30 The United States Of America As Represented By The Secretary Of The Navy Method of fabricatring sub-half-micron trenches and holes
US5382315A (en) 1991-02-11 1995-01-17 Microelectronics And Computer Technology Corporation Method of forming etch mask using particle beam deposition
US5372916A (en) 1991-09-12 1994-12-13 Hitachi, Ltd. X-ray exposure method with an X-ray mask comprising phase shifter sidewalls
US6249335B1 (en) 1992-01-17 2001-06-19 Nikon Corporation Photo-mask and method of exposing and projection-exposing apparatus
US5254218A (en) 1992-04-22 1993-10-19 Micron Technology, Inc. Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer
US5573837A (en) 1992-04-22 1996-11-12 Micron Technology, Inc. Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer
JPH0677180A (ja) 1992-08-24 1994-03-18 Fujitsu Ltd 細線状エッチングマスクの製造方法
US5386132A (en) 1992-11-02 1995-01-31 Wong; Chun C. D. Multimedia storage system with highly compact memory device
JPH06275577A (ja) 1993-03-23 1994-09-30 Sumitomo Metal Ind Ltd 半導体装置のコンタクトホール形成方法
JP3270227B2 (ja) 1993-05-26 2002-04-02 富士写真フイルム株式会社 電動巻き上げ装置
US5429988A (en) 1994-06-13 1995-07-04 United Microelectronics Corporation Process for producing high density conductive lines
KR970007173B1 (ko) 1994-07-14 1997-05-03 현대전자산업 주식회사 미세패턴 형성방법
DE19526011C1 (de) 1995-07-17 1996-11-28 Siemens Ag Verfahren zur Herstellung von sublithographischen Ätzmasken
US5905279A (en) 1996-04-09 1999-05-18 Kabushiki Kaisha Toshiba Low resistant trench fill for a semiconductor device
US7064376B2 (en) 1996-05-24 2006-06-20 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US5998256A (en) 1996-11-01 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
TW454339B (en) 1997-06-20 2001-09-11 Hitachi Ltd Semiconductor integrated circuit apparatus and its fabricating method
JP2006245625A (ja) 1997-06-20 2006-09-14 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6207523B1 (en) 1997-07-03 2001-03-27 Micron Technology, Inc. Methods of forming capacitors DRAM arrays, and monolithic integrated circuits
US6063688A (en) 1997-09-29 2000-05-16 Intel Corporation Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
KR100247862B1 (ko) 1997-12-11 2000-03-15 윤종용 반도체 장치 및 그 제조방법
US6087263A (en) 1998-01-29 2000-07-11 Micron Technology, Inc. Methods of forming integrated circuitry and integrated circuitry structures
US6605541B1 (en) 1998-05-07 2003-08-12 Advanced Micro Devices, Inc. Pitch reduction using a set of offset masks
US6140217A (en) 1998-07-16 2000-10-31 International Business Machines Corporation Technique for extending the limits of photolithography
US6303272B1 (en) 1998-11-13 2001-10-16 International Business Machines Corporation Process for self-alignment of sub-critical contacts to wiring
EP1039533A3 (en) 1999-03-22 2001-04-04 Infineon Technologies North America Corp. High performance dram and method of manufacture
US6667502B1 (en) 1999-08-31 2003-12-23 Micron Technology, Inc. Structurally-stabilized capacitors and method of making of same
US6174818B1 (en) 1999-11-19 2001-01-16 Taiwan Semiconductor Manufacturing Company Method of patterning narrow gate electrode
US6967140B2 (en) 2000-03-01 2005-11-22 Intel Corporation Quantum wire gate device and method of making same
KR100620651B1 (ko) 2000-06-22 2006-09-13 주식회사 하이닉스반도체 반도체 소자의 미세패턴 제조방법
US6339241B1 (en) 2000-06-23 2002-01-15 International Business Machines Corporation Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch
KR100340879B1 (ko) 2000-06-29 2002-06-20 박종섭 반도체 소자의 미세 패턴 형성방법 및 이를 이용한 게이트 전극 형성방법
US6429123B1 (en) 2000-10-04 2002-08-06 Vanguard International Semiconductor Corporation Method of manufacturing buried metal lines having ultra fine features
JP3406302B2 (ja) 2001-01-16 2003-05-12 株式会社半導体先端テクノロジーズ 微細パターンの形成方法、半導体装置の製造方法および半導体装置
US6580136B2 (en) 2001-01-30 2003-06-17 International Business Machines Corporation Method for delineation of eDRAM support device notched gate
CA2340985A1 (en) 2001-03-14 2002-09-14 Atmos Corporation Interleaved wordline architecture
US6545904B2 (en) 2001-03-16 2003-04-08 Micron Technology, Inc. 6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array
US6455433B1 (en) 2001-03-30 2002-09-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming square-shouldered sidewall spacers and devices fabricated
US6627524B2 (en) 2001-06-06 2003-09-30 Micron Technology, Inc. Methods of forming transistor gates; and methods of forming programmable read-only memory constructions
JP2002374092A (ja) 2001-06-15 2002-12-26 Polymatech Co Ltd 放熱性電波吸収体
US20030008968A1 (en) 2001-07-05 2003-01-09 Yoshiki Sugeta Method for reducing pattern dimension in photoresist layer
US6590817B2 (en) 2001-07-23 2003-07-08 Micron Technology, Inc. 6F2 DRAM array with apparatus for stress testing an isolation gate and method
DE10142590A1 (de) 2001-08-31 2003-04-03 Infineon Technologies Ag Verfahren zur Seitenwandverstärkung von Resiststrukturen und zur Herstellung von Strukturen mit reduzierter Strukturgröße
US6951822B2 (en) 2001-09-28 2005-10-04 Infineon Technologies North America Corp. Method for forming inside nitride spacer for deep trench device DRAM cell
KR100569536B1 (ko) 2001-12-14 2006-04-10 주식회사 하이닉스반도체 Ｒｅｌａｃｓ 물질을 이용하여 패턴 붕괴를 방지하는 방법
KR100843888B1 (ko) 2001-12-14 2008-07-03 주식회사 하이닉스반도체 Ｒｅｌａｃｓ 물질을 이용하여 식각 내성이 향상된포토레지스트 패턴을 형성하는 방법
KR20030056601A (ko) 2001-12-28 2003-07-04 주식회사 하이닉스반도체 플래시 메모리 소자의 소스 라인 형성 방법
US6638441B2 (en) 2002-01-07 2003-10-28 Macronix International Co., Ltd. Method for pitch reduction
US6548401B1 (en) 2002-01-23 2003-04-15 Micron Technology, Inc. Semiconductor processing methods, and semiconductor constructions
JP2003234279A (ja) 2002-02-08 2003-08-22 Sony Corp レジストパターンの形成方法、半導体装置の製造方法およびレジストパターンの形成装置
JP3976598B2 (ja) 2002-03-27 2007-09-19 Ｎｅｃ液晶テクノロジー株式会社 レジスト・パターン形成方法
KR20030089063A (ko) 2002-05-16 2003-11-21 주식회사 하이닉스반도체 포토레지스트 패턴 형성방법
US6734107B2 (en) 2002-06-12 2004-05-11 Macronix International Co., Ltd. Pitch reduction in semiconductor fabrication
US6774051B2 (en) 2002-06-12 2004-08-10 Macronix International Co., Ltd. Method for reducing pitch
US6548385B1 (en) 2002-06-12 2003-04-15 Jiun-Ren Lai Method for reducing pitch between conductive features, and structure formed using the method
JP3707780B2 (ja) * 2002-06-24 2005-10-19 東京応化工業株式会社 パターン微細化用被覆形成剤およびそれを用いた微細パターンの形成方法
KR20040016678A (ko) 2002-08-19 2004-02-25 삼성전자주식회사 반도체 장치 및 그의 제조방법
US6566280B1 (en) 2002-08-26 2003-05-20 Intel Corporation Forming polymer features on a substrate
US6756619B2 (en) 2002-08-26 2004-06-29 Micron Technology, Inc. Semiconductor constructions
US7205598B2 (en) 2002-08-29 2007-04-17 Micron Technology, Inc. Random access memory device utilizing a vertically oriented select transistor
KR20040025289A (ko) 2002-09-19 2004-03-24 삼성전자주식회사 고밀도 스토리지 패턴 형성방법
JP2004177952A (ja) 2002-11-20 2004-06-24 Rohm & Haas Electronic Materials Llc 多層フォトレジスト系
KR20040057582A (ko) 2002-12-26 2004-07-02 주식회사 하이닉스반도체 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법
JP2004214379A (ja) 2002-12-27 2004-07-29 Toshiba Corp 半導体装置、ダイナミック型半導体記憶装置及び半導体装置の製造方法
US6916594B2 (en) 2002-12-30 2005-07-12 Hynix Semiconductor Inc. Overcoating composition for photoresist and method for forming photoresist pattern using the same
JP2004247399A (ja) 2003-02-12 2004-09-02 Renesas Technology Corp 半導体装置の製造方法
KR100540475B1 (ko) 2003-04-04 2006-01-10 주식회사 하이닉스반도체 미세 패턴 형성이 가능한 반도체 장치 제조 방법
US6919154B2 (en) 2003-05-05 2005-07-19 Xerox Corporation Photoconductive members
WO2004100235A1 (ja) 2003-05-09 2004-11-18 Fujitsu Limited レジストの加工方法、半導体装置及びその製造方法
US6905975B2 (en) 2003-07-03 2005-06-14 Micron Technology, Inc. Methods of forming patterned compositions
US7230292B2 (en) 2003-08-05 2007-06-12 Micron Technology, Inc. Stud electrode and process for making same
US7125781B2 (en) 2003-09-04 2006-10-24 Micron Technology, Inc. Methods of forming capacitor devices
US7067385B2 (en) 2003-09-04 2006-06-27 Micron Technology, Inc. Support for vertically oriented capacitors during the formation of a semiconductor device
US7030008B2 (en) 2003-09-12 2006-04-18 International Business Machines Corporation Techniques for patterning features in semiconductor devices
JP3908213B2 (ja) * 2003-09-30 2007-04-25 富士通株式会社 レジストパターンの形成方法及び半導体装置の製造方法
US7033735B2 (en) 2003-11-17 2006-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. Water soluble negative tone photoresist
US7049652B2 (en) 2003-12-10 2006-05-23 Sandisk Corporation Pillar cell flash memory technology
US7023069B2 (en) 2003-12-19 2006-04-04 Third Dimension (3D) Semiconductor, Inc. Method for forming thick dielectric regions using etched trenches
KR100554514B1 (ko) 2003-12-26 2006-03-03 삼성전자주식회사 반도체 장치에서 패턴 형성 방법 및 이를 이용한 게이트형성방법.
US7037840B2 (en) 2004-01-26 2006-05-02 Micron Technology, Inc. Methods of forming planarized surfaces over semiconductor substrates
US7354847B2 (en) 2004-01-26 2008-04-08 Taiwan Semiconductor Manufacturing Company Method of trimming technology
US6864184B1 (en) 2004-02-05 2005-03-08 Advanced Micro Devices, Inc. Method for reducing critical dimension attainable via the use of an organic conforming layer
KR100781538B1 (ko) 2004-02-07 2007-12-03 삼성전자주식회사 성능이 향상된 멀티 게이트 트랜지스터용 액티브 구조의제조 방법, 이에 의해 제조된 액티브 구조 및 멀티 게이트트랜지스터
JP2005243681A (ja) 2004-02-24 2005-09-08 Tokyo Electron Ltd 膜改質方法、膜改質装置及びスリミング量の制御方法
US7390750B1 (en) 2004-03-23 2008-06-24 Cypress Semiconductor Corp. Method of patterning elements within a semiconductor topography
US7098105B2 (en) 2004-05-26 2006-08-29 Micron Technology, Inc. Methods for forming semiconductor structures
US20050272220A1 (en) 2004-06-07 2005-12-08 Carlo Waldfried Ultraviolet curing process for spin-on dielectric materials used in pre-metal and/or shallow trench isolation applications
US7132333B2 (en) 2004-09-10 2006-11-07 Infineon Technologies Ag Transistor, memory cell array and method of manufacturing a transistor
US7521378B2 (en) 2004-07-01 2009-04-21 Micron Technology, Inc. Low temperature process for polysilazane oxidation/densification
DE102004034572B4 (de) 2004-07-17 2008-02-28 Infineon Technologies Ag Verfahren zum Herstellen einer Struktur auf der Oberfläche eines Substrats
US7387939B2 (en) 2004-07-19 2008-06-17 Micron Technology, Inc. Methods of forming semiconductor structures and capacitor devices
US7439152B2 (en) 2004-08-27 2008-10-21 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7202127B2 (en) 2004-08-27 2007-04-10 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7151040B2 (en) 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7910288B2 (en) 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7442976B2 (en) 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
US7655387B2 (en) 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7115525B2 (en) 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
KR100640587B1 (ko) 2004-09-23 2006-11-01 삼성전자주식회사 반도체 소자 제조용 마스크 패턴 및 그 형성 방법과 미세패턴을 가지는 반도체 소자의 제조 방법
CN100438040C (zh) 2004-10-14 2008-11-26 茂德科技股份有限公司 动态随机存取存储器的结构
US7595141B2 (en) 2004-10-26 2009-09-29 Az Electronic Materials Usa Corp. Composition for coating over a photoresist pattern
US7298004B2 (en) 2004-11-30 2007-11-20 Infineon Technologies Ag Charge-trapping memory cell and method for production
US7320911B2 (en) 2004-12-06 2008-01-22 Micron Technology, Inc. Methods of forming pluralities of capacitors
US7390616B2 (en) 2005-01-12 2008-06-24 International Business Machines Corporation Method for post lithographic critical dimension shrinking using post overcoat planarization
US7253118B2 (en) 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7390746B2 (en) 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7557015B2 (en) 2005-03-18 2009-07-07 Micron Technology, Inc. Methods of forming pluralities of capacitors
US7981595B2 (en) 2005-03-23 2011-07-19 Asml Netherlands B.V. Reduced pitch multiple exposure process
US7384849B2 (en) 2005-03-25 2008-06-10 Micron Technology, Inc. Methods of forming recessed access devices associated with semiconductor constructions
US7166533B2 (en) 2005-04-08 2007-01-23 Infineon Technologies, Ag Phase change memory cell defined by a pattern shrink material process
KR100674970B1 (ko) 2005-04-21 2007-01-26 삼성전자주식회사 이중 스페이서들을 이용한 미세 피치의 패턴 형성 방법
US7544563B2 (en) 2005-05-18 2009-06-09 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7517753B2 (en) 2005-05-18 2009-04-14 Micron Technology, Inc. Methods of forming pluralities of capacitors
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
KR100732289B1 (ko) 2005-05-30 2007-06-25 주식회사 하이닉스반도체 반도체 소자의 미세 콘택 형성방법
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7396781B2 (en) 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7541632B2 (en) 2005-06-14 2009-06-02 Micron Technology, Inc. Relaxed-pitch method of aligning active area to digit line
JP4197691B2 (ja) 2005-06-21 2008-12-17 株式会社東芝 半導体装置の製造方法
US7459362B2 (en) 2005-06-27 2008-12-02 Micron Technology, Inc. Methods of forming DRAM arrays
US7271108B2 (en) 2005-06-28 2007-09-18 Lam Research Corporation Multiple mask process with etch mask stack
JP2007013457A (ja) 2005-06-29 2007-01-18 Kyocera Corp デジタル放送受信装置
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
KR100640657B1 (ko) 2005-07-25 2006-11-01 삼성전자주식회사 반도체 소자의 미세 패턴 형성 방법
US7776715B2 (en) 2005-07-26 2010-08-17 Micron Technology, Inc. Reverse construction memory cell
US7291560B2 (en) 2005-08-01 2007-11-06 Infineon Technologies Ag Method of production pitch fractionizations in semiconductor technology
US7199005B2 (en) 2005-08-02 2007-04-03 Micron Technology, Inc. Methods of forming pluralities of capacitors
TWI264058B (en) 2005-08-09 2006-10-11 Powerchip Semiconductor Corp Method of correcting mask pattern and method of forming the same
US8153350B2 (en) 2005-08-24 2012-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method and material for forming high etch resistant double exposure patterns
US7829262B2 (en) 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7416943B2 (en) 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US7776744B2 (en) 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7557032B2 (en) 2005-09-01 2009-07-07 Micron Technology, Inc. Silicided recessed silicon
US7262135B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Methods of forming layers
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7572572B2 (en) 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7687342B2 (en) 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7759197B2 (en) 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7265059B2 (en) 2005-09-30 2007-09-04 Freescale Semiconductor, Inc. Multiple fin formation
KR101200938B1 (ko) 2005-09-30 2012-11-13 삼성전자주식회사 반도체 장치의 패턴 형성 방법
US20070085152A1 (en) 2005-10-14 2007-04-19 Promos Technologies Pte.Ltd. Singapore Reduced area dynamic random access memory (DRAM) cell and method for fabricating the same
US7696101B2 (en) 2005-11-01 2010-04-13 Micron Technology, Inc. Process for increasing feature density during the manufacture of a semiconductor device
US7768055B2 (en) 2005-11-30 2010-08-03 International Business Machines Corporation Passive components in the back end of integrated circuits
US7390749B2 (en) 2005-11-30 2008-06-24 Lam Research Corporation Self-aligned pitch reduction
KR100784062B1 (ko) 2006-01-20 2007-12-10 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성방법
KR100672123B1 (ko) 2006-02-02 2007-01-19 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성방법
KR100703985B1 (ko) 2006-02-17 2007-04-09 삼성전자주식회사 반도체 소자의 제조 방법
KR100694412B1 (ko) 2006-02-24 2007-03-12 주식회사 하이닉스반도체 반도체소자의 미세패턴 형성방법
US7745339B2 (en) 2006-02-24 2010-06-29 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device
US7476933B2 (en) 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7842558B2 (en) 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
US7759253B2 (en) 2006-08-07 2010-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method and material for forming a double exposure lithography pattern
JP4801477B2 (ja) 2006-03-24 2011-10-26 富士通株式会社 レジスト組成物、レジストパターンの形成方法、半導体装置及びその製造方法
JP2007281136A (ja) * 2006-04-05 2007-10-25 Toshiba Corp 半導体基板および基板検査方法
US7902074B2 (en) 2006-04-07 2011-03-08 Micron Technology, Inc. Simplified pitch doubling process flow
US7557013B2 (en) 2006-04-10 2009-07-07 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8158333B2 (en) 2006-04-11 2012-04-17 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
JP2007294511A (ja) 2006-04-21 2007-11-08 Tdk Corp レジストパターンの形成方法、薄膜パターンの形成方法及びマイクロデバイスの製造方法
US8003310B2 (en) 2006-04-24 2011-08-23 Micron Technology, Inc. Masking techniques and templates for dense semiconductor fabrication
US7488685B2 (en) 2006-04-25 2009-02-10 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
US7314810B2 (en) 2006-05-09 2008-01-01 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device
US7429533B2 (en) 2006-05-10 2008-09-30 Lam Research Corporation Pitch reduction
US7537866B2 (en) 2006-05-24 2009-05-26 Synopsys, Inc. Patterning a single integrated circuit layer using multiple masks and multiple masking layers
US7795149B2 (en) 2006-06-01 2010-09-14 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US7709341B2 (en) 2006-06-02 2010-05-04 Micron Technology, Inc. Methods of shaping vertical single crystal silicon walls and resulting structures
US7625776B2 (en) 2006-06-02 2009-12-01 Micron Technology, Inc. Methods of fabricating intermediate semiconductor structures by selectively etching pockets of implanted silicon
US7628932B2 (en) 2006-06-02 2009-12-08 Micron Technology, Inc. Wet etch suitable for creating square cuts in si
KR20070122049A (ko) 2006-06-23 2007-12-28 주식회사 하이닉스반도체 이중 노광 공정을 이용한 미세 패턴 형성방법
KR100801078B1 (ko) 2006-06-29 2008-02-11 삼성전자주식회사 수직 채널을 갖는 비휘발성 메모리 집적 회로 장치 및 그제조 방법
US8852851B2 (en) 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
KR100843870B1 (ko) 2006-07-14 2008-07-03 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성 방법
US7521371B2 (en) 2006-08-21 2009-04-21 Micron Technology, Inc. Methods of forming semiconductor constructions having lines
JP4319671B2 (ja) 2006-08-22 2009-08-26 富士通株式会社 レジストパターン及びその製造方法、並びに、半導体装置及びその製造方法
US7611980B2 (en) 2006-08-30 2009-11-03 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
KR100761857B1 (ko) 2006-09-08 2007-09-28 삼성전자주식회사 반도체 소자의 미세패턴 형성방법 및 이를 이용한 반도체소자의 제조방법
US7959818B2 (en) 2006-09-12 2011-06-14 Hynix Semiconductor Inc. Method for forming a fine pattern of a semiconductor device
KR100855845B1 (ko) 2006-09-12 2008-09-01 주식회사 하이닉스반도체 반도체 소자의 미세패턴 형성방법
US7790357B2 (en) 2006-09-12 2010-09-07 Hynix Semiconductor Inc. Method of forming fine pattern of semiconductor device
US7666578B2 (en) 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
US8129289B2 (en) 2006-10-05 2012-03-06 Micron Technology, Inc. Method to deposit conformal low temperature SiO2
US7902081B2 (en) 2006-10-11 2011-03-08 Micron Technology, Inc. Methods of etching polysilicon and methods of forming pluralities of capacitors
US7553760B2 (en) 2006-10-19 2009-06-30 International Business Machines Corporation Sub-lithographic nano interconnect structures, and method for forming same
KR20080038963A (ko) 2006-10-31 2008-05-07 주식회사 하이닉스반도체 콘택을 갖는 반도체소자의 제조방법
KR100913005B1 (ko) 2006-10-31 2009-08-20 주식회사 하이닉스반도체 마스크 패턴 형성 방법
KR100771891B1 (ko) 2006-11-10 2007-11-01 삼성전자주식회사 더블 패터닝 공정을 이용하는 반도체 소자의 미세 패턴형성 방법
CN101542390A (zh) 2006-11-14 2009-09-23 Nxp股份有限公司 用以增大特征空间密度的两次形成图案的光刻技术
US20080113483A1 (en) 2006-11-15 2008-05-15 Micron Technology, Inc. Methods of etching a pattern layer to form staggered heights therein and intermediate semiconductor device structures
US7807575B2 (en) 2006-11-29 2010-10-05 Micron Technology, Inc. Methods to reduce the critical dimension of semiconductor devices
US20080120900A1 (en) 2006-11-29 2008-05-29 Femo Operations, Lp Systems and Methods for Repelling and/or Killing Pests Using Mulch
KR20090095604A (ko) 2006-12-06 2009-09-09 후지필름 일렉트로닉 머티리얼스 유.에스.에이., 아이엔씨. 이중 패터닝 공정을 이용한 장치 제조 방법
US7786016B2 (en) 2007-01-11 2010-08-31 Micron Technology, Inc. Methods of uniformly removing silicon oxide and a method of removing a sacrificial oxide
US8236592B2 (en) 2007-01-12 2012-08-07 Globalfoundries Inc. Method of forming semiconductor device
US7842616B2 (en) 2007-01-22 2010-11-30 Advanced Technology Development Facility, Inc. Methods for fabricating semiconductor structures
US7964107B2 (en) 2007-02-08 2011-06-21 Micron Technology, Inc. Methods using block copolymer self-assembly for sub-lithographic patterning
US7741015B2 (en) 2007-02-16 2010-06-22 Shin-Etsu Chemical Co., Ltd. Patterning process and resist composition
US7785962B2 (en) 2007-02-26 2010-08-31 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7790360B2 (en) 2007-03-05 2010-09-07 Micron Technology, Inc. Methods of forming multiple lines
US8083953B2 (en) 2007-03-06 2011-12-27 Micron Technology, Inc. Registered structure formation via the application of directed thermal energy to diblock copolymer films
KR100880323B1 (ko) 2007-05-11 2009-01-28 주식회사 하이닉스반도체 플래시 메모리 소자의 제조 방법
US20080292991A1 (en) 2007-05-24 2008-11-27 Advanced Micro Devices, Inc. High fidelity multiple resist patterning
US7709390B2 (en) 2007-05-31 2010-05-04 Micron Technology, Inc. Methods of isolating array features during pitch doubling processes and semiconductor device structures having isolated array features
KR100886219B1 (ko) 2007-06-07 2009-02-27 삼성전자주식회사 자기정렬된 이중 패터닝을 채택하는 미세 패턴 형성 방법
KR101073858B1 (ko) 2007-06-08 2011-10-14 도쿄엘렉트론가부시키가이샤 패터닝 방법
US7682924B2 (en) 2007-08-13 2010-03-23 Micron Technology, Inc. Methods of forming a plurality of capacitors
JP2009049338A (ja) 2007-08-23 2009-03-05 Toshiba Corp 半導体装置及びその製造方法
US20090074958A1 (en) 2007-09-13 2009-03-19 Dequan Xiao Polymeric nanocompositions comprising self-assembled organic quantum dots
DE102007052050B4 (de) 2007-10-31 2010-04-08 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement und Verfahren zum Erhöhen der Ätzselektivität während der Strukturierung einer Kontaktstruktur des Halbleiterbauelements
KR100874433B1 (ko) 2007-11-02 2008-12-17 주식회사 하이닉스반도체 반도체 소자의 패턴 형성 방법
KR20090050699A (ko) 2007-11-16 2009-05-20 주식회사 동부하이텍 미세 패턴 제조 방법 및 반도체 소자의 제조 방법
US8530147B2 (en) 2007-11-21 2013-09-10 Macronix International Co., Ltd. Patterning process
US7851135B2 (en) 2007-11-30 2010-12-14 Hynix Semiconductor Inc. Method of forming an etching mask pattern from developed negative and positive photoresist layers
US8083958B2 (en) 2007-12-05 2011-12-27 International Business Machines Corporation Patterning method using a combination of photolithography and copolymer self-assemblying lithography techniques
JP2009194196A (ja) 2008-02-15 2009-08-27 Nec Electronics Corp 半導体装置の製造方法および半導体装置
US7906031B2 (en) * 2008-02-22 2011-03-15 International Business Machines Corporation Aligning polymer films
JP2009252830A (ja) 2008-04-02 2009-10-29 Toshiba Corp 半導体装置の製造方法
US7713818B2 (en) 2008-04-11 2010-05-11 Sandisk 3D, Llc Double patterning method
US8440576B2 (en) 2008-04-25 2013-05-14 Macronix International Co., Ltd. Method for pitch reduction in integrated circuit fabrication
US7989307B2 (en) 2008-05-05 2011-08-02 Micron Technology, Inc. Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same
US10151981B2 (en) 2008-05-22 2018-12-11 Micron Technology, Inc. Methods of forming structures supported by semiconductor substrates
JP2009289974A (ja) 2008-05-29 2009-12-10 Toshiba Corp 半導体装置の製造方法
US7759193B2 (en) 2008-07-09 2010-07-20 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20100021573A1 (en) 2008-07-22 2010-01-28 Michael J Gonzalez Compositions and methods for the prevention of cardiovascular disease
US8158335B2 (en) 2008-09-15 2012-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. High etch resistant material for double patterning
US8012675B2 (en) 2008-09-18 2011-09-06 Macronix International Co., Ltd. Method of patterning target layer on substrate
JP2010087301A (ja) 2008-09-30 2010-04-15 Toshiba Corp 半導体装置の製造方法
US8039399B2 (en) 2008-10-09 2011-10-18 Micron Technology, Inc. Methods of forming patterns utilizing lithography and spacers
US8173034B2 (en) 2008-11-17 2012-05-08 Micron Technology, Inc. Methods of utilizing block copolymer to form patterns
US8492282B2 (en) 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
US8080460B2 (en) 2008-11-26 2011-12-20 Micron Technology, Inc. Methods of forming diodes
US8247302B2 (en) 2008-12-04 2012-08-21 Micron Technology, Inc. Methods of fabricating substrates
US8796155B2 (en) 2008-12-04 2014-08-05 Micron Technology, Inc. Methods of fabricating substrates
US8273634B2 (en) 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
JP5606019B2 (ja) 2009-07-21 2014-10-15 株式会社東芝 電力用半導体素子およびその製造方法
US8623458B2 (en) 2009-12-18 2014-01-07 International Business Machines Corporation Methods of directed self-assembly, and layered structures formed therefrom
JP2013534542A (ja) 2010-06-04 2013-09-05 エーエスエムエル ネザーランズ ビー．ブイ． 自己組織化可能な重合体及びリソグラフィにおける使用方法
US8575032B2 (en) 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8629048B1 (en) 2012-07-06 2014-01-14 Micron Technology, Inc. Methods of forming a pattern on a substrate
JP6275577B2 (ja) 2014-07-25 2018-02-07 善之 中山 釣り用ワーム及びジグヘッドリグ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6383952B1 (en) * 2001-02-28 2002-05-07 Advanced Micro Devices, Inc. RELACS process to double the frequency or pitch of small feature formation
US20050130068A1 (en) * 2003-11-21 2005-06-16 Takehiro Kondoh Pattern forming method and method for manufacturing a semiconductor device
US20080044770A1 (en) * 2006-08-17 2008-02-21 Fujitsu Limited Process for forming resist pattern, semiconductor device and manufacturing method for the same

Also Published As

Publication number Publication date
US20090291397A1 (en) 2009-11-26
EP2279517A4 (en) 2012-06-06
KR20110008247A (ko) 2011-01-26
US10151981B2 (en) 2018-12-11
CN102037543B (zh) 2014-06-18
WO2009142869A2 (en) 2009-11-26
EP2279517B1 (en) 2014-07-09
CN102037543A (zh) 2011-04-27
WO2009142869A3 (en) 2010-02-18
TW201005801A (en) 2010-02-01
EP2279517A2 (en) 2011-02-02

Similar Documents

Publication Publication Date Title
TWI397109B (zh) 形成由半導體基板支撐之結構的方法
KR101208847B1 (ko) 리소그래피와 스페이서들을 이용한 패턴 형성 방법
US9396996B2 (en) Methods of forming openings in semiconductor structures
TWI406360B (zh) 製造基板之方法
US8846517B2 (en) Methods of forming a pattern on a substrate
US20100176479A1 (en) Method of fabricating a semiconductor device
US7862986B2 (en) Patterning process
WO2017205136A1 (en) Method for patterning a substrate using a layer with multiple materials
TWI411013B (zh) 形成圖案之方法
US20140162459A1 (en) Methods of Forming A Pattern On A Substrate
US10083842B2 (en) Methods of sub-resolution substrate patterning
US10720336B2 (en) Method for manufacturing a mask
TWI515768B (zh) 微影圖案化方法及雙重圖案化方法
TW201830471A (zh) 半導體裝置的製作方法
US20050255411A1 (en) Multiple exposure and shrink to achieve reduced dimensions
JP2008066467A (ja) パターン形成方法
US11515159B2 (en) Forming contact holes using litho-etch-litho-etch approach
KR20030049116A (ko) 불화아르곤 노광원을 이용한 반도체 소자 제조 방법
US8163466B2 (en) Method for selectively adjusting local resist pattern dimension with chemical treatment
JP2009109768A (ja) レジストパターン形成方法
JPS63258020A (ja) 素子分離パタ−ンの形成方法
JP2024519492A (ja) ウェット－ドライ二層レジスト
KR19980068052A (ko) 반도체 장치의 제조방법