TWI283919B - A semiconductor device - Google Patents
A semiconductor device Download PDFInfo
- Publication number
- TWI283919B TWI283919B TW092119251A TW92119251A TWI283919B TW I283919 B TWI283919 B TW I283919B TW 092119251 A TW092119251 A TW 092119251A TW 92119251 A TW92119251 A TW 92119251A TW I283919 B TWI283919 B TW I283919B
- Authority
- TW
- Taiwan
- Prior art keywords
- bonding
- memory chip
- package substrate
- semiconductor device
- memory
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
1283919 玫、發明說明: 【發明所屬之技術領域】 本發明係關於半導體裝置,例如係關於可有效利用於在 封裝基板將多數半導體晶片搭載成疊層構造所構成之半 體裝置之技術。 【先前技術】 在封裝基板將半導體晶片組裝成疊層構造之疊層lsi (大 型積體電路),一般多半會組合既有半導體晶片,並以封裝 體之配線施行共用之訊號及、電源/接地端之連接。依據完鲁 成本發明後所作之公知例之調查,作為與本發明有關連之 資料,據報告有日本特開平2000_4353 1號公報存在。但, 孩公報所記載之技術傾向於設法減少有關疊層封裝lsi之 機種設計開發之時間與勞力,如後所述,欠缺朝向封裝基 板之外型尺寸之小型化、薄型化上之考慮。 【發明所欲解決之問題】 、&構成疊層封裝LSI<2個晶片中共用之訊號及、電源/接地 端由於未必一定將墊配置於容易在晶片間連接之處,在封_ 裝基板上連接配線時,也常會遇到必須交又配線,或配線 極端地密集之情形,封裝基板之配線層數增多,或外型尺 寸變大時’會造成小型薄型化之障礙。為個別地設置所搭 載之晶片之連接端子而需要較寬之端子排列區域也就成了 封裝體外型尺寸增大之重要因.素。 圖19至圖21係表示在本發明之前所探討之疊層封裝lsi 之例。微電LSI|| $憶體LSI係分別由既有之半導體晶片 所構成。圖19中分別表示構成叠層封裝⑶之微電腦⑶、 85980 1283919 記憶體LSI及封裝基板。微電腦LSI與記憶體LSI係分別由既 有之半導體晶片所構成。圖20中表示在基板上搭載微電腦 LSI與記憶體LSI後,再施行接合後之外觀,圖21中表示剖 面圖。 如前述圖19至圖21所示,疊層封裝LSI之構造係在將記憶 體LSI晶片接合於玻璃環氧構成之封裝基板上後,將微電腦 LSI重疊並施以晶片接合,將各晶片與基板間連線焊接後, 以樹脂塑模成型,在背面端子部附設焊料球。 φ 在圖19中,微電腦LSI係將與記憶體等連接用之位址端 子、資料端子分別集中配置於鄰接之邊。此構成在平面地 安裝微電腦LSI與記憶體LSI等時,可在安裝基板上,朝向 記憶體等以最短距離且集中地配置位址匯流排及資料匯流 排。另一方面,記憶體LSI由於端子數本身較少及為了對應 於標準的封裝體之外部端子排列,在一邊主要配置著位址 端子,在與此相對向之另一邊配置著資料端子。 將排列著如上所述之接合墊之微電腦LSI與記憶體LSI予0 以疊層時,例如,使微電腦LSI與記憶體LSI之位址端子之 方向一致時,資料端子之方向會不一致,為了在封裝基板 連接配線,有必要採用繞道連接。而且,在上述應該一致 之位址端子方面,也會因接合墊之間距在微電腦LSI與記憶 體LSI中之不一致,而有在大部分之情形必須獨立地設置端 子之情事。 因此,在封裝基板中,接合端子數(接合導線)會增加,無 法以1行排完接合導線,故如圖20之例所示,有配置成2行 85980 1283919 記憶體LSI為具有約8 Μ位元之記憶容量之靜態型RAM, 唯並未特別限定於此,其半導體晶片之形狀為長方形,使 位址端子與資料端子在短邊側分開而設有接合墊。與此種 記憶體LSI相比,微電腦LSI之晶片形狀呈現大致正方形, 且外型尺寸小於上述記憶體LSI。故如前所述,呈現在將記 憶體LSI晶片接合於封裝基板上後,將微電腦LSI重疊並施 以晶片接合,將各晶片與基板間連線焊接之構成。 上述封裝基板為了縮小外型尺寸,以大致正方形方式對| 外周確保最大之面積。如此,記憶體LSI之短邊側即不會有 面積的餘裕,故沿著其外周配置以長方形表示之接合導 線,使連到通孔之配線之拉出方向朝向封裝基板之内侧。 對於對應於上述位址端子及資料端子之接合導線,將其所 對應之通孔排列在基板之内側。相對地,由於記憶體L SI 之長邊側有面積的餘裕,故以夾著接合導線方式將通孔交 互分散配置於兩側。 如上所述,微電腦LSI係將位址端子與資料端子集中配置< 於相對向之邊。又,對與記憶體LSI之連接無助益之端子類 則主要配置於其他邊。因此,即使與記憶體LSI疊層,也不 會有相連接之端子彼此之方向不一致之事發生。為了防止 更進一步疊層而接合時,金屬線複雜地交叉,微電腦LSI 與記憶體LSI之端子一併地調整間距。也就是說,金屬線複 雜地交叉時,例如在如圖21所示,縱方向重疊3條金屬線之 情形、與如圖3所示,無交叉而重疊2條金屬線之情形,可 減薄模塑體(封裝樹脂體)之厚度。 85980 -12- 1283919 接合墊則密集配置在靠近基板之中央,其結果,金屬線呈 現放射狀集中於靠近基板之中央位置。此結果,可能發生 金屬線通過鄰接之其他導線之上空而被接合,以致於使得 鄰接導線與金屬線發生短路之可能性較高之問題。 圖7係表示本發明所使用之封裝基板之另一實施例之上 面圖。本實施例傾向於說明避免產生如前述圖5之實施例所 示金屬線通過鄰接之其他導線之上空而被接合之部分之可 能性問題之方法。在本實施例中,考慮施行接合導線與% 電腦LSI及記憶體LSI之對應之接合墊之連接之金屬線方向 而將接合導線傾斜配置。圖8係表示在此種封裝基板疊層搭 載記憶體LSI與微電腦LSI並予以接合之外觀。 在圖8中,在記憶體LSI與微電腦LSI共同施行接合之接合 導線中,雖然有至少2條金屬線呈現放射狀而朝向微電腦 LSI及記憶體LSI之對應之接合墊,但利用使此此方向與接 合導線之長度方向大致相同之方式,以消除金屬線通過鄰 接之其他導線之上空而被接合之部分。且,與此同時,消 除金屬線複雜交叉之現象,頂多也只有2條對應於微電腦 LSI與記憶體LSI之金屬線重疊,故可薄化模塑體之厚度。 圖9係表示本發明所使用之封裝基板之另一實施例之上 面圖。本實施例傾向於說明避免產生如前述圖5之實施例所 示金屬線通過鄰接之其他導線之上空而被接合之部分之問 題之方法。在本實施例中,在鄰接導線之金屬線通過上空 之部分設置缺口,以便一面降低鄰接導線與金屬線發生短 路之可能性,一面將導線之間距縮小至必要之最低限。圖 85980 -15- 1283919 1 0係表示在此種封裝基板疊層搭載記憶體LSI與微電腦LSI 並予以接合之外觀。 在圖10中,如前所述,在記憶體LSI與微電腦LSI共同施 行接合之接合導線中,至少2條金屬線呈現放射狀而朝向微 電腦LSI及記憶體LSI之對應之接合墊,微電腦LSI之金屬線 有必要連接於導線之較裏面(外側)。此結果,可能產生金屬 線通過鄰接之其他導線之上空而被接合之部分,而有導致 鄭接導線與金屬線發生短路之可能性升高,但由於在上 鄰接金屬線通過上空之部分之導線設置缺口,故可避免鄰· 接導線與金屬線發生短路之問題。 圖11係表示本發明之半導體裝置之另一實施例之局部外 觀圖。本實施例係例示地表示封裝基板搭載1個半導體晶片 LSI之情形之外觀之一部分。在本實施例中,搭載於封裝基 板之半導體晶片係搭載1個半導體晶片LSI。當然,也可同 樣週用於在此半導體晶片LSI上疊層其他半導體晶片之構 造之情形。 本貫施例係適用於設在半導體晶片LSI之接合墊數較_ 多’而無法在基板上將接合導線排成1行之情形。此時,將 接合導線排成2行,使内側與外側之行交互地形成所謂交錯 •置此理由係為了消除連接接合導線與接合塾之鄰接金 屬線彼此之重疊及確保由外側之接合導線延伸至設於内側 之通孔之配線之形成區域。 “圖12係表示本發明之半導體裝置之另一實施例之局部外 觀圖。本實施例係有關前述圖12之實施例之改良,例示地 85980 -16 - 1283919 表示封裝基板搭載1個半導體晶片LSI之情形之外觀之一部 分。在如述圖11之貫施例中,會產生由外側之接合導線延 伸之金屬線通過内側之其他導線之上空而被接合之部分, 而具有内側之導線與金屬線發生短路之可能性升高之可能 性。 在本實施例中,為了避免此問題,考慮施行接合導線與 半導體晶片LSI之對應之接合墊之連接之金屬線方向而將 接合導線傾斜配置。利用使接合導線與其所連接之金屬線I 大致朝向相同方向而成放射狀,以消除金屬線通過内側之 其他導線之上空而被接合之部分。且,與此同時,消除金 屬線彼此交叉之現象’故可防止金屬線彼此之短路,並薄 化模塑體之厚度。 圖13係表示本發明之半導體裝置之另一實施例之局部外 觀圖。本實施例係有關前述圖12之實施例之改良,例示地 表示封裝基板搭載1個半導體晶片LSI之情形之外觀之一部
分。在前述圖12之實施例中,將導線排列成多行使導線之 傾斜與金屬線方向一致時,愈往外側,導線間隔愈寬。反 之,内侧之導線之角部之間隔會變窄,可能發生由外側之 導線延伸之配線無法通過之情形。為了避免此問題,在本 實施例中,因此,將放射狀擴散之導線之内周角部形成缺 口,以確保配線通過所需之空間寬度,因此,無需將接合 區域擴大至必要程度以上,即可施行配線之繞道連接。 圖1 5係表示本發明所使用之微電腦LSI之一實施例之區 塊圖。同圖之各電路區塊係利用公知之CMOS (互補型MOS) 85980 -17- 1283919 半導體積體電路之製造技術形成餘如單晶矽等之1個基板 上。 上述4政電腦 LSI係利用 RISC (Reduced instruction set computer :精簡指令集運算)型之中央處理裝置CPU,實現高性能之 運算處理’將必要之周邊機器聚集形成於系統構成上,以 便適合於可攜式機器之應用,唯並非特別限制於此。中央 處理裝置CPU具有RISC型指令集,基本指令執行管線處理, 以1 ^曰令1狀怨(1系統時鐘週期)執行動作。以此中央處理裝I 置CPU與資料訊號處理器DSP為中心,例如向行動電話機搭 載以下之周邊電路。 内部匯流排係由I匯流排、γ匯流排、X匯流排、L匯流排 及周邊匯流排所構成,為了可利用最少零件數構成用戶系 統,作為内建周邊模組,設有適合於圖像處理之記憶體 XYMEM、記憶體控制器XYCNT。此記憶體XYMEM及記憶
體控制器XYCNT係連接於I匯流排、X、γ匯流排及l匯流排 ’執行圖像處理用之資料輸出入及顯示動作用之資料輸出 動作。 上述I匯流排中設有快取記憶體CACHE及快取記憶體控 制器CCN、記憶體管理控制器MMU、翻譯後援緩衝器TLB、 中斷控制器INTC、時鐘振盪器/看門狗定時器CPG/WDT、 視訊I/O模組VIO及外部匯流排介面,經由此外部匯流排介 面連接於前述記憶體LSI。 L匯流排中連接上述快取記憶體CACHE及快取記憶體控 制器CCN、記憶體管理控制器MMU、翻譯後援緩衝器TLB、 85980 -18- 1283919 設有電源接聊。 記憶體LSI具有約8 Μ位元之記憶容量,以16位元之單位 施行記憶體存取,故作為位址端子,有Α0〜Α1 8之19位元之 接腳。微電腦LSI如上所述,作為位址端子,有Α0〜Α25之 26個,但在微電腦LSI與記憶體LSI共同連接者為19個,與 資料用接腳加起來,為19+16=35支接腳。 此外,作為共同被連接之控制訊號用之接腳,有WE (允
許寫入)、0E (允許輸出)、US (選擇上位)、LS (選擇下位 用之4支接腳,唯並非特別限制如此。訊號US係指示寫入16 位元之資料中之上位8位元,訊號LS係指示寫入16位元之資 料中之下位8位元。因此,在微電腦LSI與記憶體LSI共同連 接者,就整體而言,為39支之少數接腳。因此,為了配合 記憶體LSI之上述共同連接之接腳之配置,在微電腦LSI 中,如同圖之黑圓所示,將資料用之接合墊及位址用之接 合墊隔三跳四地分散配置。
圖16係表示在本發明之半導體裝置之一實施例之基板上 搭載記憶體LSI與微電腦LSI後施行接合後之外觀圖。本實 施例係表示搭載前述圖14、圖15所示之微電腦LSI與約8M 位元之SRAM構成之記憶體LSI之疊層封裝LSI。同圖中,以 圓表示設於封裝基板之背面之焊料球。
在本實施例中,設於基板之接合導線中,塗上黑色者係 表示金屬線由該處向記憶體LSI與微電腦LSI延伸而共同地 被連接。圖17係表示其局部放大圖,接合導線沿著金屬線 之延長方向傾斜,使由接合導線向記憶體LSI與微電腦LSI 85980 -20- 1283919 延伸之金屬線不致於互相交叉。又,此構成也可防止由鄰 接導線延伸之金屬現在接合導線之上空交叉。 圖18係表示使用於圖16之半導體裝置之封裝基板之一實 施例之上面圖。在基板之上邊與下邊,設有包含前述記憶 體LSI與微電腦LSI之資料端子與位址端子之接合導線。此 等設於上下邊之接合導線係沿著最外周而被配置。相對地, 僅連接於微電腦LSI之接合導線則以其為中心,左右分散地 設有通孔。也就是說,在左右之邊,於最外周設有通孔。| 以上述接合導線為中心而左右分散之通孔數並非如前述圖 1之實施例所示般地一律交互均等地分散,而係考慮基板上 之空間後,適宜地決定其數量。 在上述實施例中,由於將封裝基板上之配線繞道連接抑 制在最小限,故可將外型尺寸抑制在較小尺寸。由於無交 叉配線,封裝配線可利用表背2層予以連接,故可使用薄型 而廉價之基板。更由於金屬線之交叉也可加以抑制,故可 薄化模塑體部。附帶而言,採用前述本案發明之前所探討φ 之圖19所示之構成時,利用1_4 mm只能製成LFBGA之半導 體裝置,若改用前述圖16所示之構成時,1.2 mm卻能實現 製成如TFBGA般小1級之半導體裝置。 以上,已就本發明人所創見之發明,依據前述實施例予 以具體說明,但本案發明並不僅限定於前述實施例,在不 脫離其要旨之範圍内,當然可作種種適當之變更。例如, 記憶體LSI除了前述之SRAM以外,也可使用動態型RAM、 快閃記憶體(EEPROM)。微電腦LSI只要屬於包含微處理器 85980 -21 - 1283919 圖5係表示本發明所使用之封裝基板之一實施例之上面 圖。 圖6係表示在圖5之基板上搭載記憶體lsi與微電腦LSI後 施行接合之外觀圖。 圖7係表示本發明所使用之封裝基板之另一實施例之上 面圖。 圖8係表示在圖7之基板上搭載記憶體LSI與微電腦LSI後 施行接合之外觀圖。 圖9係表示本發明所使用之封裝基板之另一實施例之上 面圖。 /圖1〇係表示在圖9之基板上搭載記憶體LSI與微電腦LSI 後施行接合之外觀圖。 圖11係表示本發明之半導體裝置之另一實施例之局部外 觀圖。 圖12係表示本發明之半導體裝置之另一實施例之局部外 觀圖。 圖13係表示本發明之半導體裝置之另一實施例之局部外籲 觀圖。 圖14係表示本發明所使用之微電腦乙“之一實施例之區 塊圖。 圖係表示圖丨4之微電腦LSI之一實施例之概略接腳配 置圖。 圖16係表示在本發明之半導體裝置之一實施例之基板上 搭載記憶體LSI與微電腦LSI後施行接合後之外觀圖。 85980 -23 -
Claims (1)
- .................... 光¥7 形日修(更)正替換頁 工283抛?11·號專利申請案 中文申請專利範圍替換本(95年7月) 拾、申请專利範固: 1. 其特徵在於·· 一種半導體裝置 备己憶體晶片,龙伯 ^ ,、係包含··沿著第1邊而對應於位址端子 之弟1接合塾、及、、儿戈 /σ f與上述第1邊相對向之第2邊而對應 於資料端子之第2接合墊者; 封裝基板’其係包含··對應於上述記憶體晶片的第1邊 而汉置之第1接合導線、及對應於上述記憶體晶片的第2 邊而設置之第2接合導線者;及 半導體晶片,其係包含··沿著第1邊而配置之位址輸出 私路用的第3接合整、及第4接合墊者,該第4接合墊包含 訊號處理電路,該訊號處理電路包含使用於沿著與上述 第1邊相對向之第2邊而配置的記憶體存取之資料輸出入 電路及資料處理功能者; 上述第1及第3接合墊係連接於上述封裝基板之共通的 上述第1接合導線,且上述第2及第4接合墊係連接於上述 封裝基板之共通的上述第2接合導線; 於上述封裝基板上搭載有上述記憶體晶片及半導體晶 片而構成疊層構造。 2.如請求項1之半導體裝置,其中,上述半導體晶片與記 憶體晶片相對應之端子彼此係藉由金屬線而連接對於上 述封裝基板之所共通化的接合導線者。 3·如請求項1之半導體裝置,其中,配合上述記憶體晶片 之位址及資料之各接合墊之間距,配置有上述半導體晶 片之相對應之位址及資料之各接合墊,且在上述半導體 85980-9507l3.doc 1283919 晶片之上述位址及資料之各接合墊之間,適宜地配置以 適3於上述記憶體晶片側之間距方式獨自設置於上述半 導體晶片之接合墊者。 •如凊求㉟1之半導體裝置,其中,上述封裝基板係在搭 =有半導體晶片之表面、及設有作為外部端子之球部的 背面分別設置有配線層,並以通孔連接相對應之配線層 者。 5.如請求項4之半導體裝置’其中,上述半導體晶片係構 成單一晶片之微電腦者,上述4邊之中剩下2邊也排列 排列有連接於微電腦所需之外部端子之接合塾者。 6· t凊求㉟5之半導體裝置,其中,上述記憶體晶片係包 含大於上述半導體晶片之面積,且形成上述第丨邊與第2 邊足長度比其他2邊之長度短之長方形,對於對應於上 述記憶體晶片的第1邊與第2邊之接合導線列,並使連 到通孔之配線之拉出方向朝向封裝基板之内側者。 7·如請求項6之半導體裝置,其中,於上述封裝基板之表 面搭載有上述記憶體晶片,於上述記憶體晶片之表面搭 載有上述半導體晶片而成為疊層構造者。 8·如請求項5之半導體裝置,其中,對於對應於上述記憶 體晶片之第1邊與第2邊以外之2邊而設置之接合導線 列,並使連到通孔之配線之拉出方向分別朝向封裝基板 之内側與外側者。 如π求貞8之半導體裝置,其中,與對應於上述記憶體 晶片之第1邊與第2邊而設置之接合導線之長度相比, 85980-950713.doc 1283919 對應於上述記憶體晶片之第丨邊與第2邊以外之2邊而 設置之接合導線之長度較短者。 10.如請求項6之半導體裝置,其中,對應於上述記憶體晶 片 < 上述第1邊與第2邊之封裝基板之接合導線係形成 長方形者,使其長度方向朝向進行連接其所對應之記憶 體晶片及半導體晶片之接合墊之金屬線之沿長方向者。 η.如請求们之半導體裝置’其中,上述第"矣合墊與上 述第3接合墊,分別係配置在與上述封裝基板之共通之 上述第1接合導線同侧,且上述第2接合墊與上述第4 接口墊,分別係配置在與上述封裝基板之共通之上述第2 接合導線同側。 12· —種半導體裝置,其特徵在於包含: 配線基板,其係包含多數接合導線者; 記憶體晶片,其係搭載於上述配線基板之主面上,且 包含多數第1接合墊者; 夕从:知晶片’其係搭載於上述記憶體晶片上,且包含: =數弟2接合塾、也使用於記憶體存取之位址輸出電路及 :料輸出入電路、及具有資料處理功能之訊號處理電路 /、即刀别廷性連接上述記憶體晶> ::第1接合墊與上述配線基板之多數接合導線d 上:金屬線’其係分別電性連接上述微電腦晶片 上述夕數第2接合孰愈μ 上逑配線基板之多數接合導線读 树脂體,其倍_如μ ^ 、上4 Μ電腦晶片、上述記憶體晶片 85980-950713.doc 1283919 上述多數第1金雇 且上述記严A 、7及上述多數第2金屬線者; 、<憶靉晶 電腦晶片露出者0 ^ 述多數第1接合墊係從上述微 13 ·如請求項12夕生f & A第丨、# "a裝置,其中,上述記憶體晶片係包 …邊與較上述第1邊還長之第2邊; 上述記憶體晶片之上述多數第1接合整係沿著上述 邊而配置; 上述彳政電腦晶片係包含多數第3邊; 上述$己憶體晶片之上述第2邊之長度係較上述微電腦 晶片的上述多數第3邊之長度還長者。 85980-950713.doc
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2003
- 2003-06-27 US US10/606,891 patent/US7061785B2/en not_active Expired - Fee Related
- 2003-07-15 TW TW092119251A patent/TWI283919B/zh not_active IP Right Cessation
- 2003-07-24 KR KR1020030050878A patent/KR20040023493A/ko not_active Application Discontinuation
- 2003-08-05 CN CNB031525962A patent/CN100433324C/zh not_active Expired - Fee Related
- 2003-08-05 CN CNA2007101122434A patent/CN101079404A/zh active Pending
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2006
- 2006-04-11 US US11/401,284 patent/US7286386B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN101079404A (zh) | 2007-11-28 |
TW200409333A (en) | 2004-06-01 |
US7286386B2 (en) | 2007-10-23 |
US20060180943A1 (en) | 2006-08-17 |
CN1481021A (zh) | 2004-03-10 |
CN100433324C (zh) | 2008-11-12 |
JP2004071838A (ja) | 2004-03-04 |
KR20040023493A (ko) | 2004-03-18 |
US7061785B2 (en) | 2006-06-13 |
US20040027869A1 (en) | 2004-02-12 |
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