TW521304B - Method and apparatus for treating low k dielectric layers to reduce diffusion - Google Patents
Method and apparatus for treating low k dielectric layers to reduce diffusion Download PDFInfo
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- TW521304B TW521304B TW090117266A TW90117266A TW521304B TW 521304 B TW521304 B TW 521304B TW 090117266 A TW090117266 A TW 090117266A TW 90117266 A TW90117266 A TW 90117266A TW 521304 B TW521304 B TW 521304B
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Classifications
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
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- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
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- H—ELECTRICITY
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
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Description
521304 A7 B7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明( 發明領域: 本發明所揭露者係關於一種在底材上積體電路的製 程及降低氧氣擴散進入介電層之方法。 發明背景: 過去十年間’眾所皆知的是積體電路的設計與製造 獲得持續且得預測的進展。能夠成功地獲得改善的其中 一個關键便是積體電路元件中能提供傳導途徑的多層内 連線技術。導體或半導體底材的微小尺寸特性,如水平 線及垂直接觸孔、介電孔(vias)或内連線(interc〇nnects), 在大型積體電路及超大型積體電路技術中,已增加了改 善半導體元件電流密度的重要性。 為了再進一步改善積體電路中半導體元件的電流密 度,必須利用具低電阻率及低介電常數的材料(此處之定 義為在介電層中其介電常數約低於3 〇,在蝕刻中止層及 阻障層中約低於5.0)作為絕緣層來降低相鄰内連線^之 電容稱合。習知的介電材料在内連線間具相當的電容搞 合性,如此會導致串音(cross talk)現象且/或電阻_電容遲 延’亦即需要花費時間以消除降低半導體 積能量。 的系 然而’習知的低介電常數介電材料是能被 需要-阻障層來避免材料間之内層擴散至該低介 介電材料。習知阻障層材料的介電常數高於7兒吊數 如氮化矽。而當習知阻障層材料盥 ·以上, '、低介電常數材料相接 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐 ____________--------訂---------< (請先閱讀背面之注意事項再填寫本頁) 521304 A7 經濟部智慧財產局員工消費合作社印制衣 五、發明說明( 合時,該絕緣體堆疊會降低該低介兩〜 果,並通常會產生一介電常數無法、/ '數材料之改善效 在利用傳統的低介電常數介^低於,6』的堆疊。 另一個困難便是積體電路中鋼使用見枓當作絕緣層時, 阻率(1·7μΩ<ιη)及高傳導性使它2的增加。銅的低電 、 為内連線材料的選擇 冬一。不過,銅很容易地便會擴散 、 會改變鄰接層的電子元件特徵 十 且 ΑΑ你、# 例如形成一越過介電層 的傳導途徑,因而降低整個電路 一从^ ^ ^ 叩Τ信賴度並甚至造成 70件的故障°銅的這種㈣特性’特別是對於該新的且 低介電常數、易滲透及擴散的薄膜,增加了具抗擴散性 低介電常數阻障層的需要。 碳化碎層已被認為是作 > 彳#人 疋忭為低介電常數阻障材料的潛 在材料。尤其是如美國專利專利申請冑〇9/165,248,標 題為「作為阻障層及中止層之碳化石夕之況積」之申請案, 1 998年1〇 $ 1日中清,為本發明申請案之受讓人所擁 有並在此併入以兹參考,且本發明並無不一致之内容, 碳化石夕在該案中便被使用為一具低介電常數之阻障層。 然而,低介私$數之碳化矽層通常是可滲透且能讓 氧擴散入該介電層,特別是能擴散入謗介電層之表面。 氧能在該碳化矽介層中與矽材料反應形成氧化物,一般 相信該氧化物會增加導體材料(例如:鋼)擴散入碳化矽 的特性及降低該阻障層的整體效果。氧擴散入碳化矽層 的h況可發生於在沉積過程中碳化矽與氧的接觸或是當 該碳化矽層在處理室與核團工具(cluster t〇〇ls)的轉換之 第5頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 1 ^1 ϋ -ϋ ϋ Βϋ i_i 1— ·ϋ * ϋ ^1 ^1 ϋ I ^1 —.1 I —·1 ϋ· 1§ ϋ 11 ϋ ϋ I #▲ (請先閱讀背面之注意事項再填寫本頁) A7
521304 五、發明說明() 間接觸到氧化的環境。 此外,碳化矽層吸附氧之後將影響該碳化矽層與鄰 接材料之键結或附著性,特別是銅等傳導材料,炎jL會 ^成材料的層韌離。另外,在碳化矽層中所形成之氧化 物通常具有較相鄰的碳化矽材料為低的密度。形成於破 化矽層 < 表面及上層部分的低密度氧化物會導致該層變 (J如凸起或隆丘),在同形(conformally)填充高深寬 比物件時’特別不希望該變形行為發生,且這種形變會 在Ik後的材料沉積時形成空孔及其他沉積缺陷。 因此’便需要一能夠減少低介電常數介電層中氧擴 政之製%。在理想的情況中,該製程能夠減少阻障層中 氧的3里’例如在銅的金屬化製程中碳化矽層的使用。 發明概述: 本發明之各態樣係關於一種產生低介電常數介電層 (例如·蛟化矽)的方法,該介電層具有對氧的抗擴散性 及低氧含I,在銅的金屬化過程中可被利用作保護層及/ / 章層本發明其中之一怨樣為一種在處理室中處理 底材之方法,包括先於處理室中在一底材上沉積一低介 電常數介電層,輸入一處理氣體至該處理室中,產生該 處理氣體之電漿,並且將該低介電常數介電層曝露於該 處理氣體之中。 本發明之另一態樣為一種處理底材之方法,包括在 處理室中於該底材上沉積一碳化矽層,輸入一選自惰性 第6頁 本紙張反度適用中國國家標準(CNS)A4規格(210 x 297公釐) -----------^裝--------訂_| c請先閲讀背面之江意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 521304 經濟部智慧財產局員工消費合作社印製 氣體、氮化氣體及其 處理室中,並將碳化 良該碳化矽層之表面 該惰性氣體可能包含 氣體可能包含氨、氮 意組合物。 本發明之另一態 數阻障層之方法,包 層,並在該低介電常 護層由一包含矽與氮 化物。 A7 發明說明( 上述任意組合族群之處理氣體至該 矽層曝露於該處理氣體電槳中來改 以在該碳化梦層上形成—保護層。 氮、氣及其任意組合物,而該氮化 、氮與氫之混合物、氧化氮及其任 樣為—種在底材上形成一低介電常 括在甩材上沉積一低介電常數介電 數介電層上沉積一薄保護層。該保 的材料所構成,如氮化矽或矽氧氮 圖式簡單說明: 本發明之上述及其令3 、、 匕目的、特徵及優點可由下 細說明並配合圖示之說明 ^ J向更侍以彰顯,其中上述 述的本發明之特定描述可、 斤概 丁參考詳細說明中的特余眘 施例,這些特定實施例則以 貫 丨厂订 < 圖式配合說明。 不過在此當聲明的是, 订 < 圖不僅用以說明太筱 明之典型實施例,而並非用 本^ m ^ 艮疋本發明範圍,本菸明 之軌圍貫則包含其餘等效之實施例。 第1圖所示者為本發明所利 L 已商業使用的化學翕 相沉和(C V D )電漿處理室 、 主刹面圖; 第2圖所示者為一受惰性氣 * 私水處理的碳化矽層原子 /辰度尤X-ray光電子 ^ (X-ray Photoelectron 本紙張尺度_中關家標準(CNSM4規格
Hi n 1^1 ϋ fi · ϋ— K n ϋ .^1 ϋ i^i 一。, n I ϋ I ϋ n ϋ I 1— i (請先閱讀背面之注意事項再填寫本頁) 521304 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明()
Spectroscopy, XPS)圖; 第3圖所示者為一受氮化氣體電漿處理的碳化矽層原子 濃度之X-ray光電子光譜圖; 第4圖所示者為一受電漿處理的碳化矽底材之剖面圖; 第5圖所示者為一具保護層之碳化矽層原子濃度之x_ray 光電子光譜圖; 第6圖所示者為受碳化矽層覆蓋的底材之剖面圖。 圖號對照說明: I n i·— emmmmm ammmm ϋ 1 · ϋ ·ϋ ϋ tmt ϋ ϋ ϋ ϋ- 1 ·_1 ϋ ·ϋ I #! (請先閱讀背面之注意事項再填寫本頁) 1 0化學氣相沉積處理室 11氣體分佈板 12晶座 13支撐柱 1 4抬升馬達 15處理室 16底材 17絕緣環 1 9氣體混合系統 24 管道 2 5 RF電源供應器 32真空幫浦系統 3 4系統控制器 3 6控制線 3 8記憶體 100金屬化堆疊 1 3 0咬底材 1 3 2氧化物層 1 3 4第一低介電常數碳化 矽阻障層 1 3 6抗擴散表面 1 3 8 銅層 1 4 0第二低介電常數碳化 矽阻障層 200金屬化堆疊 230矽底材 232氧化物層 第8頁 本紙張尺度綱巾關家標準(CNS)A4規格 521304 A7 ---- B7 — _ 一 五、發明說明() 234 第一低介電常數碳化矽層 236氮化矽層 238銅層 240第二低介電常數碳化矽層 242氧化物層 發明詳細說明: 本發明係關於利用一製程設備’如位於加州聖塔克 拉拉的應用材料公司所生產的Centura®平台,來實行之 電漿處理及化學氣相沉積製程。該設備以包含一具有化 學氣相沉積處理室(CVD chamber)的整合平台為佳,如由 應用材料公司所生產的DxZTM化學氣相處理室或 ProduCerTM化學氣相處理室。以下對該處理室的描述僅 疋為了說明’而不應推斷或解釋為對本發明範圍之限制。 第1圖為可利用前述之製程產生並維持電漿的化學 氣相沉積處理室之剖面圖。處理室1 0包括一氣體分佈板 11,該氣體分佈板位於底材支撐板或晶座12之上並定義 了處理底材16的處理範圍。晶座12能間接受熱並位於 一支撐柱13上,如此晶座12便可以在一較低負荷或無 負荷的位置及一較高或接受處理的位置之間由抬升馬達 14來控制其移動。當該晶座12位於處理位置時,一絕 緣環1 7環繞該晶座i 2及其上之底材i 6的周圍。製種氣 體由氣體分佈板11上之入口輸入至該處理室1〇,並且 均勻地分佈於該處理區域及底材表面。該製程氣體利用 真空幫浦系統32由管道24排出。 第9頁 本紙張尺度適用中關家標準(CNS)A4規格(21G X 297公餐"^ ' -- (請先閱讀背面之注意事項再填寫本頁) 裝 訂· 經濟部智慧財產局員工消費合作社印製 521304 A7
五、發明說明() 經濟部智慧財產局員工消費合作社印製 一熱加強製程或電漿加強製程可完成於處理室丨〇, 孩電漿加強製程以用來作為本發明後沉積層處理為佳。 在電漿處理的過程中,可在鄰近底材處形成一受控制的 電漿藉由RF電源供應器25及接地的晶座12向該氣體分 佈板11供應RF能量。一 RF電源供應器25能提供該氣 體分佈板1 1單一或混合頻率的RF來增強任何輸入至處 理罜1 5的反應物種的分解。一混合頻率之rf功率供應 一般提供約13.56MHz的高RF頻率(RF1)及約35〇kHz的 低RF頻率(RF2)。 典型的處理室内部,包括氣體分佈板丨丨、晶座12 及各種其他的處理室裝置皆是由鋁或電鍍鋁所製成。一 化學氣相沉積處理室典型的例子如美國專利案第 5,000,113號,標題「一熱CVD/PECVD處理室及二氧化 矽的熱CVD之利用及其多階平坦化製程」,由王等人獲 传專利’並轉濃給應用材料公司,在此併入以兹參考, 本發明並無不一致之内容。 邊抬升馬達1 4將晶座1 2在加工位置及一較低的底 材負荷位置間升起及下降。一系統控制器34由控制線36 控制該馬達、該氣體混合系統1 9及該RF電源供應器25。 該處理室包含由系統控制器3 4所控制的類比式配件,如 質流控制器(MFCs)及標準或脈衝式rf產生器,而該系 統控制器所執行的系統控制軟體儲存在記憶體3 8中,其 貫施例一硬式磁碟儲存裝置為佳。馬達及光學感應器皆 利用來移動及決定該可移動機械組件的位置,如真空幫 第10頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ---------II^_W ^--------訂-— (請先閱讀背面之注意事項再填寫本頁) 五、發明說明() 浦32之節流閥與晶座12之定位馬達。 該系統控制器34控制該化學氣相沉積處理室之活動 並包括一硬式磁碟儲存裝置、一軟式磁碟儲存裝置及一 卡式架。該卡式架包含一單板計算機(single board eomputer,SBC)、類比式及數位式輸入/輸出板、介面板 及步進馬達控制器板。該系統控制器符合了定義電路板、 卡式房以及連接器尺寸及種類的Versa Modular Europeans(VME)標準。該標準亦規範了 16位元資料匯流 排與24位元定址匯流排之架構。儲存於該硬式磁碟儲存 裝置3 8中的電腦程式控制了系統控制器34之運轉。該 電腦程式係處理一特定製程之時點、氣體之混合、Rf功 率、晶座位置及其他參數。 該設備1 0之特定實施例在此描述本發明,但並不庶 推斷或解釋為對本發明範圍之限制。 典型製程 經濟部智慧財產局員工消費合作社印製 本發明之各態樣將在此描述以作為上述製程之較佳 參考。本發明各態樣與製造低介電常數介電層(例如· 0 化矽)之方法有關,該介電層能減少氧擴散及維持低氧本 量,在銅的金屬化過程當中並可被使用為保護層且/或阻 障層。該介電層可同步或不同步地與低氧含量形成,藉 著將該低介電常數介電層曝露於惰性氣體電装當中來辦 加該介電層之密度並形成一保護層表面,將低介電常數 介電層曝露於氮化電漿當中來形成一氮化物保護層表面 第11頁
經濟部智慧財產局員工消費合作社印製 於咸;丨電層上,或县获六士、 % ^ JS ΛΑ 一 θ邊低介電常數介電層上沉積一 薄保-層的方法來降低氧擴散入該層内。 本發明中一保護表面 ^ * 今、翁* 廣心地疋義為能減少水分擴 政、虱虱及其他有害狀況 ^ H 、例如·孩表面或該材料層曝露 於周k ^境或製程污染物 仅二祓@ 、 A T )义一材料或一材料層。該 保遠層那能減少導體金屬 I j Μ •銅)之擴散。在同一個 處理至中可同步完成二 ^ ^ ^ , Μ 4夕個製程或在同一製程系統 内不中斷真空狀態或不與 、狂T的5染物環境接觸。 、T施例巾/儿積一低介電常數介電層並利用本 土明I電漿製程於該低介電常數介電層上形成一保護表 面:,電漿製程能利用來處理一低介電常數介電層(例 士瓦化矽)以作為一低介電常數的保護層或阻障層。 由% t矽構成的低介電常數介電層係由供應一流 動率約介於ΐθ至1000標準立方公分(standard centimeters,seem)之含矽碳源材料至一電漿處理室沉積 形成忒έ矽之奴源材料由一或多個有機矽燒前驅物所 構成,例如三甲基矽烷、二甲基矽烷、甲基矽烷及其紐 合物。此外’包含分離矽及包含碳之製程氣體(例如:石夕 燒及甲燒)亦分別地輸入該處理室來幫助碳化矽的沉積。 一惰性氣體(例如:氦、氬及其組合物)亦以約 5 0 seen 至5 000sccm間之流率輸入至該處理室中。維持該處理室 壓力於約100 milliTorr至15 Torr間。在沉積過程中, 維持該底材表面之溫度於約1〇〇°c至450°c間。該氣體分 佈板11放置於距底材約200 mils至600 mils。 第12頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 521304 A7 --------B7 五、發明說明() 供應該處理室10 一單頻13·56ΜΗζ之RF電源以產 生一功率獪度約介於〇 3 watts/cm2及3.2 watt/cm2間或 於200 mm底材上功率介於1〇〇 waUs至i〇〇〇 waUs之電 漿。提供該處理室以產生電漿以約介於〇 9 waUs/cm2至 2.3 Watts/Cm2間之功率密度或200mm底材上約介於 300watts至700watts之功率為佳。 一沉積碳化矽材料之典型製程方法包括以約sccm 至500 seem之流率輸入一含三甲基矽烷之製程氣體至一 處理室,以約1〇〇 “⑽至2000 sccm之流率輸入一氬之 惰性氣體至孩處理室,維持該處理室之氣壓於約3 至10 Torr間,保持一底材表面溫度於約2〇〇它至4⑻。c 間,並提供孩處理室約300watts至7〇〇waUs來產生該製 程氣體之電槳。該氣體分佈板n放置於距底材約3〇〇mUs 至 600 mils 〇 由上述之製程所沉積的低介電常數碳化矽層為氫化 之碳化石夕層,其介電常數約於5·5 ^下,並可作為阻障 層。此外,觀察上述製程參數進行沉積所獲得之低介電 常數碳化矽層,其中該層之組成為:石夕:碳之莫耳分率 約為1 : 1,且該層之氫原子濃度至少約為30%至45%之 馬1。在製造半導體元件時,該低介電常數碳切層可使 用作保護層、阻障層、餘刻中止層及反反應塗佈(anti_ reactive coatings) 〇 沉積低介電常數碳化梦層的製程已更完整地在美國 專利未定案,第09/165,248號,1 998年1〇月i日申請、 第13| 本紙張尺度適用中國國家標準(CNSM4規格(21G X 297公髮y ---------1 I —Awl --------訂---------* (請先閱讀背面之注意事項再填寫本頁) 521304
、發明說明( 美國專利未定案,第09/21 9,945號,1 998年口 'i z 月 2 3 申請,以及美國專利未定案,第〇9/27〇,〇39 日 1 El L 死 ’ 1999 年 Γ4先閱讀背面之注意事項再填寫本頁) 月Μ日申請,在此併入以茲參考,本發明並無不— 又内容。本發明之實施例在此所描述的碳化矽芦^ 致 、,僅為描述本發明,該特定實施例不應限制本發明^〜 圍。本發明亦考慮了其他沉積碳化矽層之製程及材料^軏 惰性氣體電漿製程 本發明之一實施例,係將前述之沉積的低介電常數 碳化矽層曝露在一惰性氣體中,來增加該碳化矽層之密 度以形成一保護表面並降低擴散至該層之氧。將一底材 放入處理室中,並選擇氧、氬及其上述任意組合物族群 之惰性氣體,以約200至2000sccm之流率輸入至該處理 室中。在進行電漿處理製程時,維持處理室之壓力於約 1至12Torr,並維持底材的溫度於約1〇〇t:至45〇t:之間。 在進行電漿處理製程時,維持該底材溫度於約3 5 〇。〇為 較佳。 經濟部智慧財產局員工消費合作社印製 提供該處理室約0.08至6.4watts/cm2間之RF功率 密度,或提供200mm底材約25至2000watts的RF功率 來產生該惰性氣體的電漿。供應該處理室來產生電漿以 約0.3至3.2watts/cm2的功率密度,或2〇〇mm底材約100 至1 000watt的功率為佳。該電漿之處理時間為約3〇至120 秒鐘。以電漿來處理沉積層與沉積該低介電常數碳化矽 層可同步執行。 第u頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公餐) 經濟部智慧財產局員工消費合作社印製 521304 A7 ---—---- —_B7__ 五、發明說明() 一儿積碳化矽層之處理製程係以約400seem之流率 將氛輸入至含有2〇〇mm底材的處理室中。在該處理製程 中’將達到並維持約8τ〇ΓΓ的處理室氣壓及約35〇°c的底 材/皿度。亥處理室接受約1 · 2至1 · 6 watts/cm 2的RF功率 被度或約400至500 watts的RF功率以產生電漿,並處 理該碳化矽層約5 〇秒鐘。 沉積碳化梦層一較佳的處理製程係以約l3〇〇sccm的 流率將氦輸入含有200mm底材的處理室中,維持該處理 室壓力與底材溫度於約8.7Torr及35(TC,供應該處理室 約250watts以產生電漿,並維持該電漿約5〇秒。 该碳化石夕沉積處理室或相同整合系統之一不同處理 室可同步執行該電漿處理,亦即不需中斷製程間之真空 狀態。目别已觀祭到依本發明之惰性氣體電漿處理方法 所產生的碳化矽層,其氧含量約低於6%原子濃度。 第2圖所示者為根據本發明所揭露的惰性氣體電漿 製程所處理的5〇oA厚的碳化矽層之原子濃度(at〇mic concentration,atomic %)與濺擊時間之x_ray光電子光譜 (X-ray Photoelectron Spectropy,XPS)圖。該圖描述除氫 以外的碳化矽層元素,隨著該層深度不同之原子濃度。 該XPS之資料係以約20至25A的速率移除材料後,該 層每經濺擊一分鐘後所得之資料。第2圖的X轴,即藏 鍍時間’係该層不同深度之元素原子濃度讀數。第2圖 的Y軸係依據該層濺擊步驟時間的元素原子濃度,其中 碳表示為C’碎表示為Si,氧表示為〇,氮表示為n。 第15頁 本紙張尺度適財關家群(CNS)A4規格x 297公餐) "一 * 裝--------訂---------齊. (請先閱讀背面之注意事項再填寫本頁) 521304
經濟部智慧財產局員工消費合作社印製 五、發明說明() 曰則巳覜祭到接受該 石夕層中氧的平均濃度為約4%至6%,較習知未經處理的 礙化層之氧之預期濃度約10%至15%為低。 一般相信該惰性電體之電漿物種藉由移除材料(例 如·薄膜上的妓與氫)、移除該材料的微孔與移除或降低 其空孔或其他缺陷來加強該層之表面密度。將一碳化矽 材料(、、勺90A至100A厚)與一碳化矽塊料下層之材料(約 〇A至420A厚)比較,前者表面密度約1·以至 1.59g/cm3,而後者之整體密度為約2 〇8至a」乜“Μ。 -般更認為增強表面之密度提供了一防止氧氣擴散 入Μ層之保護表面,與未經處理過的碳化矽層相比較, 該表面對氧氣擴散及材料氧化更具抵抗的效果,也加強 了孩層與連接層的黏著性。一 a 一 舨也相仏,在半導體製造 密度表面對其他材料⑽ 抵抗性。 辦狀文八 氮化氣體電漿製程 《月 < 另f施例’係將一低介電常數碳化 曝露於氮化氣體電漿中,以 产 在邊石反化矽層上形成一舍 氮的表面。該富含氮的碳切層表面包括氮化♦、: 亂化物、矽氧氮化物、或碳矽 反 甘&尸/ 乳鼠化物’在本發明Φ 1览化表面。該氮化氣體係選自氣、氮、 及其上述任意組合之族群。由於氨於乳化- 即高於25〇。(:後氨易解^ 、易解離性 風“離為電漿形態的特性,因此氨, 第16| --------I--裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 521304
經濟部智慧財產局員工消費合作社印制衣 五、發明說明() 般便用來產生氮化表面。 本發明所描述的氮化表面能藉由以下的製程形成於 %化梦層上。在處理室中放置一底材並以約i 〇〇至 3OOsccm的流率輸入氮化氣體至該處理室中。維持該處 理室的壓力於約100 milliTorr至25 milliTorr間。維持 孩處理室的壓力於i Torr至12 T〇rr間為較佳,5 至 1 〇 Torr為更佳的狀態。在電漿處理的過程中,維持該底 材溫度於約1 〇 〇。〇至5 0 0。(:之間。 才疋供該處理室約〇·〇8至6.4 watts/cm2的RF功率密 度,或200mm底材約25至2000watts的RF功率來產生 私漿°提供約0.3至3.2 watts/cm2的RF功率密度或2〇〇mm 底材約100至l〇〇〇watts的功率為較佳。將該碳化矽層曝 露於該氮化電漿中約10至120秒鐘來產生一約5〇A至 400A厚的氮化表面。该碳化梦沉積之同一處理室或相同 整合系統之一不同處理室可同步執行該電漿處理。 一典型的沉積低介電常數介電層之氮化電漿處理製 程方法包括對含有200mm碳化矽底材的處理室以約2〇〇 至600sCCm的流率提供氨,於氮化過程中維持該處理室 壓力於約8至9Torr並維持該底材的溫度於約3〇〇£>c至4〇〇 °C,提供該處理室約1.2至1.6 watts/cm2之Rf功率密度 或約400至500watts的RF功率以產生電槳,並維持該 電漿約5至60秒鐘來修正該碳化矽表面以產生一氮化表 面。該電漿能在一個或多個處理循環中產生。而另一個 方法則是將碳化矽層曝露在該電漿製程中約2〇至6〇秒 第17頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ------------Φ·裝--------訂i (請先閱讀背面之注意事項再填寫本頁) 521304 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明( 鐘 孩氮化氣體更可由一惰性氣體所組成(例如:氬或 氦)’來f助處理該層之表面,亦可協助穩定該氣流及電 装反應。惰性氣體可以約低於2000seem的速率輸入至該 處理罜中來與氮化製程相接合。該氮化氣體亦可由一反 應氣體(例如:氫)所組成,來協助清除氮化製程中該層 的污染物。 该石反化砂沉積處理室或相同整合系統之一不同處理 i可同步執行該電漿處理,亦即不需中斷製程間之真空 狀態。目前已觀察到本發明揭露的氮化氣體電漿處理方 法可產生氧含量低於6%原子濃度的碳化矽層。 弟3圖所示者為一根據本發明所揭露的惰性氣體電 漿製程所處理的500A厚碳化矽層之原子濃度(at〇mic concentration,atomic %)與濺擊時間之x-ray光電子光譜 (X-ray Ph〇t〇electron Spectropy,xPS)圖。該碳化矽層經 過流率約40〇sccm氨的處理,處理室壓力維持在約, 提供200mm的底材約350wattsRF功率以產生電聚,並 維持該底材溫度於約35(rC。第3圖之Y軸顯示該碳化 層之平均氧濃度為4% ’低於未經處理過的碳化珍層之預 期10%至15%之氧濃度。 當氮氣電漿被使用於一電漿處理方法之實施例當 中,以在碳化矽層上形成一氮化表面時,今 T 邊虱化氣體覆 於該層上並且一不同的反應(例如:熱反應)會在該層及 該氮化氣體間促進該氮化反應。 第18頁 I ϋ I βϋ ϋ· 41— ϋ ·1 *1 ·1 ϋ ime 1§ · mmmtm n I— 1 If «^1 ϋ I (請先閲讀背面之注意事項再填寫本頁) 521304 A7 B7 五、 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 發明說明( 本發明的另一實施例,係將該沉積低介電常數碳化 矽層曝露在該氮化氣體之中,並利用一熱加強製程方法 讓氧從該碳化碎層逸出並在該層上形成一氮化表面。一 熱製程至少包括以約1 00至3 OOOsccm的流率輸入該氮化 氣體至處理室中’維持該處理室壓力於約5至25 Torr間, 在處理過程中維持該底材溫度於約3 5 0 °C至5 0 0。(:間。此 外,亦可在該退火過程中維持該處理室壓力於約8Torr 至lOTorr °在該退火過程中維持該底材溫度於約45〇°C 為佳。 當氮被混入該碳化矽層之中,該氮化表面被認為能 在該碳化矽層上形成一由碳化矽、碳矽氮化物、矽氧氮 化物或碳矽氧氮化物所構成的薄氮化保護層表面。該氮 化表面與未經處理過的碳化矽層相較更具對氧擴散入碳 化矽層的阻抗能力。一般也認為該氮化保護層表面並不 會顯著地增加該碳化矽層的介電常數。更進一步來說, 對該層的表面進行氮化處理將使該非結晶的碳化矽層產 生氮的键結,因此當消除相鄰層間的缺陷時,便能增強 界面間的鍵結及黏著性。更進一步地說,目前已觀^到 孩氮化表面比起含有氧化矽的其他層,對其他材料(例 如:水或銅)的擴散具有更好的阻抗能力,因此在鋼的全 屬化製程當中增強了碳化矽層的阻障特性。 ▲ 弟4 B I員示在一利用本發明所揭冑的惰#氣體或氮 化氣體電漿方法所處理之銅的金屬化堆疊100中,將低 介電常數碳化矽層作為阻障層。該阻障層134係利用上 第19頁 本紙張尺度適財關家標準(CNS)A4規格⑵G x 297公^ --------I--裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 521304 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明( 述的低介電常數碳化矽沉積製葙 領I私所產生。該金屬化堆疊 1 〇 〇首先係在矽底材1 3 0上沉穑 ,,r 9 /儿積一約5〇〇〇A的氧化物層 132。約800A的第一低介電當 •私吊數石反化矽阻障層134隨後 沉積於該氧化物層132上。接戈 … 接著,利用本發明的惰性氣 體或氮化氣體電漿製程處理該第一低介電常數碳切阻 障層⑴以產生一抗擴散表面136。接下來,於該第一 低介電常數碳化梦阻障| 134的抗擴散表面136上沉積 一約测A厚的銅層138。在該铜層138上沉積_約8〇〇入 厚的第二低介電常數碳化矽阻障層14〇,並且在該第二 低介電常數碳化矽阻障I 14〇上沉積一約1〇〇〇入厚的氧 化物層 142。另一種方式盔 丄 禋万式為,亦可在該銅層之前沉積一 金屬氮化物阻障層(例如:氮化鈇(TiN)或氮化麵(TaN))來 進—步限制該銅層138對該碳化珍層134的層間擴散。 以上的金屬化堆疊100僅是為了供舉例說明,不應被分 析或解釋為限制本發明的範園。舉例來說,—雙镶嵌結 構製造過程之一特徵區中,該氮化矽層140可作為一蝕 刻阻障層或一反反應塗佈。 氮化矽保護層 本發明 < 另一實施例係以一由矽及氮構成之薄保護 層覆蓋於一低介電常數碳化矽層上,來降低進入該層之 氧的擴散。琢保護層由氮化矽、碳矽氮化物、矽氧氮化 物或碳矽氧氮化物所構成。 在一碳化碎層上沉積一保護層的方法包括以约至 第20頁 lx 297公釐) — — — — — — I — — if I ·1111111 一« — — — — — — I— ^^^^1 ri I I f.. (請先閱讀背面之注意事項再填寫本頁) 521304 經濟部智慧財產局員工消費合作社印製 A7 ______B7 _ 五、發明說明() 100 0seem的流率輸入一含石夕的氣體以及以約50至 2000seem的流率輸入一含氮的氣體至處理室中。該含梦 的氣體係選自矽烷、甲基矽烷、三甲基矽烷、其替代衍 生物及其上述任意組合之族群。該含氮的氣體係選自氨、 氮、一氧化一氮、及其上述任組合之族群。該氮化氣體 含有氧(例如:一氧化二氮)來沉積一矽氧氮化物之保護 層。 維持該底材溫度於約100至5 50。(:。維持該處理室 壓力於約1至25Torr。一較佳的實施例係在沉積的過程 中,維持該處理室壓力於4至5Torr。提供約0.3至 3.2watts/cm2的RF功率密度或提供200mm底材約1〇〇至 lOOOwatts之RF功率至該處理室以產生該製程氣體之電 漿。 沉積該氮化矽層約25至500A厚。以沉積該保護層 約50至200人厚為較佳。該氮化矽層被預期能沉積任何 厚度,端視該製程對碳化矽層及保護層的應用。 該保護層沉積處理室或相同整合系統之一不同的處 理室可同步在碳化梦層上沉積一保護層’亦即不需中斷 製程間的真空狀態。該保護層之沉積與隨後的低介電碳 化矽層之沉積同步為佳,以避免該碳化矽層曝露在可能 產生污染及氧化作用的空氣之中。該氮化矽層及珍氧氮 化物層的碳含量低於5%原子濃度。當該氮化矽層及梦氧 氣化物層以上述的方法沉積後,其他能沉積由沙及氮組 成的保護層的方法及材料便能被預期得到。 第21頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -------------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 521304 A7 B7 五、發明說明() 第5圖顯示在一矽底材上所沉積並由如前段所述之 包含矽及氮的保護層所覆蓋的約500A厚的碳化矽層,其 原子濃度相對於濺擊時間的(X-ray Photoelectron Spectropy,XPS)圖。該保護層的沉積包括以約li5sccm 的速率輸入三甲基梦燒及以約1500sccm的速率輸入氨至 該處理室中,維持處理室壓力於約4至5Torr,提供約 3 50watts的RF功率至一 200mm底材,當三甲基矽烷與 氨反應時’維持該底材溫度於約3 5 〇。 Μ保護層沉積約400A厚。該保護層能沉積較400A 還薄的厚度以對一 SiN/SiC堆疊之介電常數k的全面衝 擊達到最小。第5圖的γ軸顯示出具有沉積保護層之該 層的平均氧濃度介於約2至4%之間,較未經處理的碳化 石夕層 < 預期的氧濃度約1 0至1 5 %為低。 如第5圖所示,經過濺擊過程約2〇分鐘後,該氮化 梦層皆已被濺擊’該氮化珍層的組成便能夠被測量出來。 依據孩層之成m ’量測料之氧濃度並未超過該平 =值約2至4%’此結果顯示該層現場沉積可減少該二氧 二广染程度。一般認為電漿增強該薄保護層的 ^:在該碳切層上形成—抵抗層’來形成—對氧具 性且不會影響該阻障層介電常數的整合阻 草層。更進一步地說,一般 刃、 化物對導Γ材料M 〜、、、因為虱化矽及矽氧氮 t導材枓(例如:銅)具更佳 氮仆功仅冷既 机彍散性,因此孩 :保濩層可改善該碳化矽阻障層的性質。 弟6圖所示者為一低介 一 吊數石反化矽阻障層,其被 第22頁
本紙張尺度適用^^_ m〇 X 2^iT
五、發明說明( 揭露的氮切保護層所覆蓋。金屬化堆叠20l 23 2 夕底材230上沉積一約5000A厚的氧化 斤1。第一低介電常數碳切阻障層⑼隨後利用本S ::揭露的製程方法沉積在該氧化層232上約800A厚發 :製;氮化:保護層236藉由三…燒及氨之増強電 4。〇广積在該第一低介電常數碳…障層上約 00A。一約 50〇〇a 厚的 陸 ? P現後、,儿積在該碳化矽阻 曰《虱石夕層236上。沒有顯示 化物阻障層(例如:氮化咎力a 金屬虱 鈦或氮化妲)也能較該銅層為先 永’儿知以限制銅擴散人# J门擴政入錢化矽層234。接著,沉積_ 約800A厚的第二低介♦登 弟低η私吊數碳化矽層240於該銅層23丨 ,最後是一約1000人厚的氧化物層242。 二般相信本發明所揭露的電漿處理製程改善了對掮 月阻抗性、強化了該低介電常數介電層(例如··碳化珍 =鄰的材料之間的内層鍵結及黏著…般亦編 私水處理製程亦降低了合凰 - “屬化組合層間的電阻或阻相 1,也藉由增加的沉積碳切層之介電常數該消除m 染物(例如:氧)。作A你 為保&層且/或阻障層,該低氧含^ 低介電常數之材料可降低銅之内層擴散與減少該保護
^或阻障層内連線《電容藕合。當關於處理低介電常I 夕層Ik後的描述,本發明亦考慮應用已知的製程3 其他半導體製造中能渗透層及其他習知的電常^ 電層。 込之說月僅為本發明中的較佳實施例,而非用, 第23頁 ---------·裝 f請先閱讀背面之注意事項再填寫本頁) _ n ϋ· 11 ϋ n «ϋ · i ϋ -I ϋ n 1 I 1 經濟部智慧財產局員工消費合作社印製 521304 A7 B7_ 五、發明說明() 限定本發明之範圍,故利用這些實施例所進行的修改或 更動都不脫離在所附專利範圍所言明之範圍外,本發明 之範圍當以後述的專利申請範圍為基準。 -------------裝--------訂--------- 辞 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 第24頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
Claims (1)
- 521304 A8 B8 C8 D8 六 經濟部智慧財產局員工消費合作社印製 申請專利範圍 1. 一種處理底材之方法,該方法至少包含: 在一處理室中沉積一低介電常數介電層在該底材 請 先 閱 讀 背 之 注 意 事 項 再 填 本 頁 上; 輸入一製程氣體至該處理室中; 在該處理室中產生該製程氣體之電漿;及 曝露該低介電常數介電層於該製程氣體電漿中。 2. 如申請專利範圍第1項所述之方法,其中上述之低介 電常數介電層具有原子濃度約為6%以下之氧含量。 3 ·如申請專利範圍第1項所述之方法,其中上述之低介 電常數介電層更包含碳化矽。 4 ·如申請專利範圍第1項所述之方法,其中上述之製程 氣體係選自氦、氬及其任意組合之族群。 5 ·如申請專利範圍第1項所述之方法,其中上述曝露該 低介電常數介電層於該電漿中之步驟係增加該低介電 常數介電層之表面密度。 6.如申請專利範圍第1項所述之方法,其中上述之製程 氣體係一選自氨、氮、氧化氮及其任意組合族群之氮 化氣體。 第25頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 521304 A8 B8 C8 D8 六 經濟部智慧財產局員工消費合作社印製 申請專利範圍 7.如申請專利範圍第6項所述之方法,其中上述之氮化 氣體於該低介電常數介電層上形成一氮化表面。 請 先 閱 讀 背 之 注 意 事 項 再 填 本 頁 8 ·如申請專利範圍第1項所述之方法,其中上述曝露該 低介電常數介電層於該電漿中之步騾更包含供應該處 理室約0.08至6.4watts/cm2電力的功率密度以產生該 電漿。 9 ·如申請專利範圍第8項所述之方法,其中上述之該低 介電常數介電層係曝露於該電漿當中約1 0至1 2 0秒 鐘。 I 0 ·如申請專利範圍第1項所述之方法,其中上述之處理 室壓力介於約lOOmilliTorr至25Torr。 II ·如申請專利範圍第1項所述之方法,其中上述處理該 底材之步驟更包括以約3000sccm或3000sccm以下的 流率輸入一含惰性氣體、氮化氣體或其任意組合之製 程氣體至該處理室中,並維持該處理室壓力於約1至 12Torr,供應該處理室約0.3至3.3watts/cm2功率密度 的電力以產生該電漿,並且維持該電漿約20至60秒 鐘。 1 2 ·如申請專利範圍第11項所述之方法,其中上述之低 第26頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 521304 A8 B8 C8 D8 六、申請專利範圍 介電常數介電層具有原子濃度約為6%以下之氧含量。 1 3 · —種處理底材的方法,該方法至少包含: 於處理室中沉積一碳化矽層在一底材上; 輸入一選自惰性氣體、氮化氣體及其上述任意組合 之族群之製程氣體至該處理室中; 在該處理室中產生該製程氣體之電漿;及 曝露該碳化矽層於該製程氣體電漿中以改良該碳化 矽層之表面,以產生一保護層表面於該碳化矽層上。 14_如申請專利範圍第13項所述之方法,其中上述之惰 性氣體係選自氦、氬及其任意組合之族群。 1 5 ·如申請專利範圍第1 3項所述之方法,其中上述之製 程氣體係一惰性氣體,且增強該碳化矽層之表面密度。 16. 如申請專利範圍第13項所述之方法,其中上述之氮 化氣體係選自氨、氮、氧化氮及其任意組合之族群。 17. 如申請專利範圍第13項所述之方法,其中上述之製 程氣體更包括一氮化氣體,並且在該低介電常數介電 層上形成一氮化表面。 18·如申請專利範圍第13項所述之方法,其中上述曝露 第27頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ---------‘---裝--- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 521304 A8 B8 C8 D8 六、申請專利範圍 該低介電常數介電層於該電漿中之步驟更包含供應該 處理室約 0.3至 3.2watts/cm2功率密度的電力以產生 該電漿。 19·如申請專利範圍第18項所述之方法,其中上述之該 低介電常數介電層係曝露於該電漿當中約20至60秒 鐘。 20.如申請專利範圍第13項所述之方法,其中上述之處 理室壓力為約1至12Torr。 2 1 ·如申請專利範圍第1 3項所述之方法,其中上述處理 該底材之步驟更包括以約3 0 0 0 s c c m或3 0 0 0 s c c m以下 的流率輸入一含惰性氣體、氮化氣體或其任意組合之 製程氣體至該處理室中,並維持該處理室壓力於約5 至lOTorr,供應該處理室約1.2至1.6watts/cm2電力 的功率密度以產生該電漿,並且維持該電漿約20至60 秒鐘。 22.如申請專利範圍第13項所述之方法,其中上述之碳 化秒層係一阻障層、一领刻停止層、一保護層或一抗 反射塗佈層。 2 3 ·如申請專利範圍第1 3項所述之方法,其中上述之碳 第28頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ---------裝—— (請先閱讀背面之注意事項再填寫本頁) . 經濟部智慧財產局員工消費合作社印?衣 521304 A8 B8 C8 D8 六、申請專利範圍 化矽層具有原子濃度約為6%以下之氧含量。 24.—種在底材上形成一低介電常數阻障層之方法,該方 法至少包含: 在該底材上沉積一碳化矽層;及 在該碳化矽層上沉積一包含矽及氮的保護層。 2 5 ·如申請專利範圍第2 4項所述之方法,其中該保護層 係包含氮化矽或氮氧化矽。 26·如申請專利範圍第24項所述之方法,其中上述之沉 積該保護層包括: 輸入一含矽氣體及一含氮氣體至一内有該底材之處 理室中; 在該處理室中產生一電漿; 在該電漿當中讓該含矽氣體與該含氮氣體反應,以 沉積一含珍及氮之保護層。 27. 如申請專利範圍第26項所述之方法,其中上述之含 矽氣體係選自矽烷、甲基矽烷、三甲基矽烷、其替代 衍生物及其任意組合之族群。 28. 如申請專利範圍第26項所述之方法,其中上述之含 氮氣體係選自氨、氮、氧化氮及其任意組合之族群。 第29頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝 · 521304 A8 B8 C8 D8 六、申請專利範圍 2 9 ·如申請專利範圍第2 6項所述之方法,其中上述之電 漿係由供應該處理室約0 · 3至3 · 2 watts/cm2功率密度 之電力所產生。 3 0 ·如申請專利範圍第2 6項所述之方法,其中上述之處 理室氣壓約為1至25Torr。 3 1.如申請專利範圍第24項所述之方法,其中上述包含 矽及氮之保護層係沉積約25至5 00A之厚度。 請 先 閱 讀 背 之 注 意 事 項 再 填 本 頁 經濟部智慧財產局員工消費合作社印刺衣 第30頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
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-
2001
- 2001-07-10 US US09/902,518 patent/US6794311B2/en not_active Expired - Lifetime
- 2001-07-12 EP EP01305999A patent/EP1172845A3/en not_active Withdrawn
- 2001-07-14 KR KR1020010042623A patent/KR100743775B1/ko not_active IP Right Cessation
- 2001-07-16 JP JP2001215713A patent/JP2002176100A/ja active Pending
- 2001-09-25 TW TW090117266A patent/TW521304B/zh not_active IP Right Cessation
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KR20020007224A (ko) | 2002-01-26 |
KR100743775B1 (ko) | 2007-07-30 |
US20020016085A1 (en) | 2002-02-07 |
EP1172845A3 (en) | 2009-09-30 |
EP1172845A2 (en) | 2002-01-16 |
US6794311B2 (en) | 2004-09-21 |
JP2002176100A (ja) | 2002-06-21 |
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