KR101048002B1 - 반도체 소자의 장벽 금속층 형성방법 - Google Patents
반도체 소자의 장벽 금속층 형성방법 Download PDFInfo
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- KR101048002B1 KR101048002B1 KR1020030097638A KR20030097638A KR101048002B1 KR 101048002 B1 KR101048002 B1 KR 101048002B1 KR 1020030097638 A KR1020030097638 A KR 1020030097638A KR 20030097638 A KR20030097638 A KR 20030097638A KR 101048002 B1 KR101048002 B1 KR 101048002B1
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- forming
- layer
- dual damascene
- damascene pattern
- insulating film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (8)
- 하부 금속 배선이 형성된 반도체 기판 상에 제1 절연막, SiC로 이루어진 식각 정지막, 제2 절연막을 순차적으로 형성하는 단계;상기 제2 절연막에는 트렌치를 형성하고, 상기 제1 절연막에는 비아홀을 형성하여 듀얼 다마신 패턴을 형성하는 단계;상기 듀얼 다마신 패턴 내부의 제1절연막과 제2절연막 측벽 및 트렌치에 의해 노출되는 식각정지막의 상면을 플라즈마처리하여 상기 듀얼 다마신 패턴 내부의 제1절연막과 제2절연막 측벽 및 트렌치에 의해 노출되는 식각정지막의 상면에 플라즈마 처리막을 형성하는 단계;상기 듀얼 다마신 패턴을 포함한 전체 구조 상에 확산 방지막을 형성하는 단계;상기 듀얼 다마신 패턴의 측벽 및 저면에 금속 시드층을 형성하는 단계; 및상기 듀얼 다마신 패턴내에 금속물질로 매립하여 금속 배선을 형성하는 단계로 구성되며,상기 플라즈마처리는 Ar가스와 CH4반응가스에 의해 실행되어, 상기 제1절연막과 제2절연막의 표면에 SiC결합을 형성하여 상기 듀얼 다마신 패턴 내부의 표면특성을 균일하게 하는 것을 특징으로 하는 반도체 소자의 장벽 금속층 형성방법.
- 삭제
- 삭제
- 삭제
- 제 1 항에 있어서,상기 Ar 가스 대 상기 CH4 반응가스의 비율이 0.25 내지 2인 반도체 소자의 장벽 금속층 형성방법.
- 제 1 항에 있어서,상기 하부 금속 배선 상에 형성된 금속 산화물이 상기 표면 플라즈마 처리에 의해 환원되어 금속으로 변하면서 제거되는 반도체 소자의 장벽 금속층 형성방법.
- 제 1 항에 있어서,상기 플라즈마 처리 시 상기 반도체 기판의 온도를 25℃ 내지 350℃로 유지하고, 400W 내지 800W의 고주파 파워와 0W 내지 100W의 저주파 파워를 인가하는 반도체 소자의 장벽 금속층 형성방법.
- 제 1 항에 있어서,상기 확산 방지막은 단원자 증착법으로 형성되는 반도체 소자의 장벽 금속층 형성방법.
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KR1020030097638A KR101048002B1 (ko) | 2003-12-26 | 2003-12-26 | 반도체 소자의 장벽 금속층 형성방법 |
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KR1020030097638A KR101048002B1 (ko) | 2003-12-26 | 2003-12-26 | 반도체 소자의 장벽 금속층 형성방법 |
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KR20050066362A KR20050066362A (ko) | 2005-06-30 |
KR101048002B1 true KR101048002B1 (ko) | 2011-07-13 |
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Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100853098B1 (ko) * | 2006-12-27 | 2008-08-19 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 및 이의 제조 방법 |
KR101932660B1 (ko) | 2012-09-12 | 2018-12-26 | 삼성전자 주식회사 | Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20020007224A (ko) * | 2000-07-14 | 2002-01-26 | 조셉 제이. 스위니 | 확산을 감소시키도록 낮은 유전상수의 유전층을 처리하기위한 방법 및 장치 |
KR100399909B1 (ko) * | 2000-12-29 | 2003-09-29 | 주식회사 하이닉스반도체 | 반도체 소자의 층간 절연막 형성 방법 |
KR20030091700A (ko) * | 2002-05-21 | 2003-12-03 | 에이저 시스템즈 인크 | 반도체 장치 및 반도체 장치 제조 프로세스 |
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Publication number | Priority date | Publication date | Assignee | Title |
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KR20020007224A (ko) * | 2000-07-14 | 2002-01-26 | 조셉 제이. 스위니 | 확산을 감소시키도록 낮은 유전상수의 유전층을 처리하기위한 방법 및 장치 |
KR100399909B1 (ko) * | 2000-12-29 | 2003-09-29 | 주식회사 하이닉스반도체 | 반도체 소자의 층간 절연막 형성 방법 |
KR20030091700A (ko) * | 2002-05-21 | 2003-12-03 | 에이저 시스템즈 인크 | 반도체 장치 및 반도체 장치 제조 프로세스 |
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