TW514994B - Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate spacers, and a memory array made thereby - Google Patents

Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate spacers, and a memory array made thereby Download PDF

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Publication number
TW514994B
TW514994B TW090123061A TW90123061A TW514994B TW 514994 B TW514994 B TW 514994B TW 090123061 A TW090123061 A TW 090123061A TW 90123061 A TW90123061 A TW 90123061A TW 514994 B TW514994 B TW 514994B
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TW
Taiwan
Prior art keywords
layer
trenches
conductive material
polycrystalline silicon
scope
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Application number
TW090123061A
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English (en)
Chinese (zh)
Inventor
Jr-Shing Wang
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Silicon Storage Tech Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
TW090123061A 2000-09-20 2001-09-19 Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate spacers, and a memory array made thereby TW514994B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US23431400P 2000-09-20 2000-09-20
US23398800P 2000-09-20 2000-09-20
US24209600P 2000-10-19 2000-10-19
US09/916,619 US6868015B2 (en) 2000-09-20 2001-07-26 Semiconductor memory array of floating gate memory cells with control gate spacer portions

Publications (1)

Publication Number Publication Date
TW514994B true TW514994B (en) 2002-12-21

Family

ID=27499707

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090123061A TW514994B (en) 2000-09-20 2001-09-19 Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate spacers, and a memory array made thereby

Country Status (6)

Country Link
US (2) US6868015B2 (enExample)
EP (1) EP1191585A2 (enExample)
JP (1) JP5140219B2 (enExample)
KR (1) KR100821495B1 (enExample)
CN (1) CN1186820C (enExample)
TW (1) TW514994B (enExample)

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US7613041B2 (en) * 2003-06-06 2009-11-03 Chih-Hsin Wang Methods for operating semiconductor device and semiconductor memory device
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US20080203464A1 (en) * 2004-07-01 2008-08-28 Chih-Hsin Wang Electrically alterable non-volatile memory and array
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US8072023B1 (en) 2007-11-12 2011-12-06 Marvell International Ltd. Isolation for non-volatile memory cell array
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US9634019B1 (en) * 2015-10-01 2017-04-25 Silicon Storage Technology, Inc. Non-volatile split gate memory cells with integrated high K metal gate, and method of making same
CN107305892B (zh) * 2016-04-20 2020-10-02 硅存储技术公司 使用两个多晶硅沉积步骤来形成三栅极非易失性闪存单元对的方法
CN107359163B (zh) * 2016-05-05 2020-06-02 中芯国际集成电路制造（天津）有限公司 存储单元的制备方法
KR102604564B1 (ko) 2016-07-01 2023-11-22 인텔 코포레이션 자기 정렬 게이트 에지 트라이게이트 및 finfet 디바이스들
TWI805336B (zh) * 2022-04-25 2023-06-11 華邦電子股份有限公司 半導體結構及其形成方法

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Also Published As

Publication number Publication date
EP1191585A2 (en) 2002-03-27
CN1351382A (zh) 2002-05-29
CN1186820C (zh) 2005-01-26
JP2002151608A (ja) 2002-05-24
US7018897B2 (en) 2006-03-28
KR100821495B1 (ko) 2008-04-11
US20020034846A1 (en) 2002-03-21
KR20020022628A (ko) 2002-03-27
US6868015B2 (en) 2005-03-15
US20040214395A1 (en) 2004-10-28
JP5140219B2 (ja) 2013-02-06

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