TW492066B - Susceptors for semiconductor-producing apparatuses - Google Patents

Susceptors for semiconductor-producing apparatuses Download PDF

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TW492066B
TW492066B TW090118156A TW90118156A TW492066B TW 492066 B TW492066 B TW 492066B TW 090118156 A TW090118156 A TW 090118156A TW 90118156 A TW90118156 A TW 90118156A TW 492066 B TW492066 B TW 492066B
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Shinji Yamaguchi
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Ngk Insulators Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67103—Apparatus for thermal treatment mainly by conduction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

492066 五、發明說明（l) 【發明所屬的技術區域】 本發明係有關於在半導體製造裝置中，為了在載置面 上載置被處理物並加熱的陶瓷製基座。 【習知技術】 氮化矽等陶瓷構成之在基座底部埋設阻抗發熱體的陶 瓷加熱器，被使用於在半導體製造裝置内的半導體晶圓之 加熱用途。又，埋設產生高頻率電漿的電極之加熱器被使 用於半導體製造裝置。於如此的裝置中，在基座上設置矽 晶圓或液晶用基盤等被處理物，在處理後，被處理物由舉 起銷舉起，解除被處理物的支持，搬送被處理物。 【發明所欲解決的課題】 本發明者發現，把晶圓以美应±.^ ^ w 熱施以既定的處理，在由電聚環境下加 時，屢屢發生因為晶起晶圓，欲解除支持 載置面上有數_的位置偏差。 私王日日圓在 本發明的課題為對以基座支 理時，當解除晶圓的支持時 止^曰曰因在加熱下施以處 之附著現象而產生的位置偏差。因晶圓往基座的載置面 本發明為，在半導體製造裝 置於載置面上而加熱的陶究製加執吏被處理物載 了設置載置面的表面層以及 :15，其特徵在於：具備 ’其中’表面層的體積電阻率層成-體化的支持層 。 又符層的體積電阻率還低 如此，藉著在陶瓷基座上設 置體積電阻率相對低的表
第4頁 7066-4216-PF； ahddub.ptd
jI« λ成功的防止由被處理物往載置面的吸附現象，當 ?处勿的支持解除時，被處理物的位置偏差。 特別的人3 對於為了在電聚環境下載置、加熱被處理物 十。加熱被支持於基座上的被處理物的方法並沒有特別限 =詈例=i可用紅外線加熱基座。又，可在基座的背面側 ς，另一=加熱器。但是，在支持層内埋設發熱體的情況 時’特別容易發生前述之被處理物的位置偏差，本發明 有效的。 ^又，雖然理由還不清楚，但是，在支持層内埋設產生 南頻率電漿用電極的情況時，特別容易發生前述之被 物的位置偏差，本發明為有效的。 基座的使用溫度並沒有特別限定，但2 5 〇 〇c以上的溫 度特別適用於本發明。又，使用溫度的上限亦沒有特 定，但以6 5 0 °C以下為佳。 义 表面層及支持層的各個體積電阻率，可按照，於使用 的溫度等的吸附能力應答性或漏電流等適當決定。但是， 在基座的目的使用溫度，體積電阻率以1 X 1 〇8 Ω · 以下 為佳，在1 X 1 Ο7 Ω · cm以下更佳。 於支持層的目的使用溫度，舉例來說，體積電阻率為 了提高產生電襞的效率，體積電阻率以1x1 〇8Ω .cm以上' 為佳，在1 X 1 01G Ω · cm以下更佳。 又，於目的使用溫度，支持層的體積電阻率為表面層 的體積電阻率的10倍以上為佳，1〇〇〇倍以上更佳。 曰
492066 五、發明說明（3) 陶兗：Ϊ基=表面層及支持層最好由被一體化的同種的 成，稭由此，可防止表面層和支持層的剝離， 由基座的彎曲所產生的載置面的平面度的低落。 及 即使f 同種陶瓷指的是主成分相同的陶瓷，添加成分 /、動也可。最好是佔有8〇重量％的成分為同一種。 Μ 1主成分以氮化銘、氮切、氧化1呂、鍅、氮化蝴# 為較佳，以氮化鋁為最佳。 见化,4 在各種陶瓷中，由於控制體積電阻 =詳細的記載。但是，例如在氮化 材質為佳。 付〜以以下的 化铭=電阻率比較高的敗化紹，可舉例說明，以氮 鋁為主成V刀’係擁有氮化氮 二結體，燒結體中含有100ppm以上50。夕二質 或鋰的化合物或鎂的化合物。 下的鋰或疋鎂 又，在氮化鋁中，稀土類元夸沾人 旦 換算值）為150PPm以上，0.5重量％以^，二（對氧化物的 以外的金屬不除物量為900ppm以下，在陰‘二二元素 在350nm〜37〇nm的波長區域中有主要高峰"、光瑨中， 體，因為有1 X 1 〇6 Ω · cm以上，丨χ】ni2 w佳。此燒結 電阻率，i金屬不純物的量也少 二"1以下的體積 造裝置。 也夕所以適合作為半導體製 表面層的厚度並沒有特別的限定，但 的效果有效，以1 〇 # m以上為佳，姓 為了使本發明 雖然表面層的厚度沒有特別”的上限別是lmm以上為最佳。 义，但以20mm以下為佳。 492066 五、發明說明（4) 支持層的厚度並沒有限定，但特別以3〜5〇龍為佳。 相射二去ί :層Γ厚度為支持層的厚度的1 /4以下為佳。 mi;層，表面層太厚的話會易受晶圓上部發生的電 水饴度为布的影響，並不為佳。 在較佳的實施型態中，在基座上， 處理物的支持之用的解除用構件的在 ： 二ΐί情況中，被支持於載置面上的基座，形成 差特別容易產: 舉起的形狀，被處理物的位置偏 暫if :古二在基座内的發熱體及產生高頻率用的電極之材 質η:別限定，但以金屬海或钥合金為佳。以翻和鶴 的比率的卜金作為鉬合金為佳。在鉬合金的場合，鉬 :=的上限沒有特別的上限，可以增加到100重量“純 人厶ν冰而鉬的比率的下限為50重量％。又’除鉬金屬或 ° 1丄以鎢、紹、鉑的純金屬或合金為佳。 沖孔ίΐΐϊί用的電極的形態並沒有限定，“網狀或是 ^屬狀的情況時特別容易發生前述的問冑，本發明為 有效的。 祛。：t發明中’以表面層有一定程度厚度的板狀體為 本身面層可為在支持層上形成的膜，而以表面層 本身為陶瓷的表體為佳。 ，如，根據以下的方法，可製造本發明的基座。 署吝41)把支持層用的陶瓷粉末用加壓成形，在其上設 同頻率用的電極及/或發熱體，然後再在其上充填 _ 第7頁 7066-4216-PF ; ahddub.ptd ^U66 五、發明說明（5) 支持層用的陶瓷粉末，以加壓成形。接著，在此成型體上 ’充填表面層用的陶瓷粉末，再加壓成形，而得到成形體 將此成形體燒成一體而得到燒成體，加工燒成體而得到 基座。 (2 )把支持層用的陶瓷粉末用加壓成形，在其上放 上產生高頻率電漿用的電極及/或發熱體，然後再在其上 真支持層用的陶兗粉末’以加壓成形。在此粉末成型體 ^放上支持層用的陶瓷表體，藉著把粉末成形體及表體燒 成一體而得到燒成體，再加工此燒成體。 (3 J)把支持層用的陶瓷粉末用加壓成形，在其上放 j產生高頻率電漿用的電極及/或發熱體，然後再在其上 榼ii持層用的陶瓷粉末，以加壓成形，㉟成-體而得到 。表面層用的陶瓷表體，和此燒成體接合，加工成 以狀座。在此時的接合方法可以是鋅接、ΐ 瑪接合、樹脂接合、固相擴散法等。 圖1概略的表示本發明的實施形態中基座丨。基座丨 =層3及支持層2構成。在表面層3的載置面4上，支持著 :回8。在支持層2的内部，埋設了產 = 和阻抗發熱體10。5為基座的本體。電極的電 接，發熱體10和電源12連接。從恭¥ ^ ，、1連 穿孔7。 钱從載置面4向著背面6形成貫 【實施例】（比較例） 使用藉由還原氮化法所得到的氣化銘粉 中添加丙稀樹脂黏結劑，洚丨 叔末 和利用喷霧造粒裴置造粒，而得到 7066-4216-PF ； ahddub.ptd 492066 五、發明說明（6) 造粒顆粒。將此造粒顆粒成形，製作成直徑為2〇〇111(11，厚 度為3 0mm的圓盤狀預備成形體。此時，在成形體中埋設電 極9及組抗發熱體1〇。此時的成形壓力為2〇〇kg/cm2。使用 錮製的金屬網作為電極9。使用直徑0〇· 2〇π1的鉬線，以i 英吋約50根的密度所編織而成的金屬網作為此金屬網。 燒結此成形體，而得到直徑為23〇mm、厚度為1 5mm的 基座。將基座設置在反應室中，在此基座上設置矽晶圓。 反應室内為1 〇-3以下之真空，將氟系氣體導入反應室中， 供給電極電力，使氟系氣體的電漿產生。與此同時，供給 電力給阻抗發熱體，將矽晶圓加熱到既定溫度。然後，從 貫穿孔7 ( 3處）使舉起銷上升，舉起矽晶圓，解除支持。 用1 0 0片的矽晶圓進行此實驗，從觀察窗口來確定晶圓有 無位置偏差。計算產生位置偏差的晶圓數。其結果如表1 所示。 [表1] 晶圓的想度rc> A1N的體積電阻率（Ω ♦〇〇 產生位置偏差的晶圓軚 100 2 X 1〇15 0 200 lx 1014 5 250 1 X 1013 87 650 3 X 108 23 700 lx 1〇6 0 (本發明例1 ) 製造與比較例1相同的基座。但是，電極9及阻抗發熱
7066-4216-PF ； ahddub.ptd 第 9 頁
體1 0埋設在支持層内，另外，製一 層。表面層的厚度為1.5 mm。 氮化鋁構成的表面 將支持層的接合面和表面層的人々 接著在兩者間以三氧化二釔水溶 5 ^达研磨加工， 和表面層接合。對於如此所得到:媒μ、加熱使支持層 樣的實驗。其結果如表2所示。土座，進行和比較例同 [表2] 表面層的體積電 阻率（Ω ·〇!〇 生位置偏®
晶圓的溫度（°c η (本發明例2) 製造與本發明例1同樣之基座，但是，表面層及支持 層的各體積電阻率變更為如表3所示。 [表3] 晶圓的溫度rc> 表面層的體積電 诅率（Ω D 支持餍的體積電 阻率（Ω ♦«〉 產生位置偏差的晶圓數 200 7 X 108 1 x 10iS 3 250 1 X 10s 4 χ 10H 0 650 1 5 lF ~~ 8 x 109 0 700 8 , 5 x 10s 0
7066-4216-PF ； ahddub.ptd 第10頁 492066 五、發明說明（8) 【發明效果】 如以上所述，只要根據本發明的基座，可防止當支持 在基座上的晶圓在加熱下施以處理，解除晶圓的支持之際 ，晶圓對基座載置面的吸附現象所產生的位置偏差。 【圖式簡單說明】 【圖1】關於本發明的一個實施形態的基座1的概略的 示意圖。 【符號說明】 1〜基座； 2〜支持層； 3〜表面層； 4〜載置面； 5〜基座本體； 6〜基座的背面； 7〜貫穿孔； 8〜被處理物； 9〜產生高頻率電漿用之電極； 1 0〜發熱體。
7066-4216-PF ； ahddub.ptd 第11頁

Claims (1)

  1. 4yzuoo
    、· 種半導體製造裝置用基座，在半導體製造裝置中 將被處理物載置於載置面上而加熱的陶瓷製者， 其特徵在於包括： 表面層，設置了前述載置面；以及 支持層’與表面層成一體化， 表面層的體積電阻率較支持層的體積電阻率還低。 2·如申請專利範圍第1項所述之基座，其中，為了在 電聚環境下載置前述被處理物並加熱之基座。 3·如申請專利範圍第1或2項所述之基座，其中，在前 述支持層内埋設了加熱體。 4·如申請專利範圍第1或2項所述之基座，其中，在前 述支持層内埋設了產生高頻率電漿用的電極。 5·如申請專利範圍第3項所述之基座，其中，在前述 支持層内埋設了產生高頻率電漿用的電極。 6·如申請專利範圍第1或2項所述之基座，其中，前述 基座沒有靜電夾盤功能。 7·如申請專利範圍第5項所述之基座，其中，前述基 座沒有靜電夾盤功能。 8·如申請專利範圍第丨或2項所述之基座，其中，前述 基座的使用溫度為250 °C—650 °C。 9.如申請專利範圍第7項所述之基座，其中，前述基 座的使用溫度為250 °C— 650。(：。 10·如申請專利範圍第1或2頊所述之基座，其中，前 述表面層之於目的使用溫度的體積電阻率為1x10 Ω ·επι
    7066-4216-PF ί ahddub.ptd 第12頁 X 492066 六、 申請專利範圍 以下，前述支持層之於目的使用溫度的體積電阻率為i 1 〇8 Ω · cm 以上。 11·如申請專利範圍第9項所述之基座，其中，前述表 面層之於目的使用溫度的體積電阻率為l><l08Ω·cm以\ 下，前述支持層之於目的使用溫度的體積電阻率為1χ1〇8 Ω · cm以上。 12·如申請專利範圍第1或2項所述之基座，其中，前 述表面層與前述支持層為同種的陶瓷所構成。 13·如申請專利範圍第11項所述之基座，其中，前述 表面層與前述支持層為同種的陶瓷所構成。 14·如申請專利範圍第1或2項所述之基座，其中，形 成為了插入作為解除被處理物的支持之用之解除用構件的 在前述載置面上開口的貫穿孔。 1 5 ·如申請專利範圍第1 3項所述之基座，其中，形成 為了插入作為解除被處理物的支持之用之解除用構件的在 前述載置面上開口的貫穿孔。
    7066-4216-PF ； ahddub.ptd
TW090118156A 2000-10-23 2001-07-25 Susceptors for semiconductor-producing apparatuses TW492066B (en)

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