TW454312B - Printed wiring board for semiconductor plastic package - Google Patents

Printed wiring board for semiconductor plastic package Download PDF

Info

Publication number
TW454312B
TW454312B TW089102305A TW89102305A TW454312B TW 454312 B TW454312 B TW 454312B TW 089102305 A TW089102305 A TW 089102305A TW 89102305 A TW89102305 A TW 89102305A TW 454312 B TW454312 B TW 454312B
Authority
TW
Taiwan
Prior art keywords
copper
wiring board
printed wiring
pad
copper foil
Prior art date
Application number
TW089102305A
Other languages
English (en)
Inventor
Hidenori Kimbara
Nobuyuki Ikeguchi
Katsuji Komatsu
Original Assignee
Mitsubishi Gas Chemical Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP11036365A external-priority patent/JP2000236041A/ja
Priority claimed from JP11089782A external-priority patent/JP2000286362A/ja
Application filed by Mitsubishi Gas Chemical Co filed Critical Mitsubishi Gas Chemical Co
Application granted granted Critical
Publication of TW454312B publication Critical patent/TW454312B/zh

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01012Magnesium [Mg]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0103Zinc [Zn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01045Rhodium [Rh]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01051Antimony [Sb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01056Barium [Ba]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01083Bismuth [Bi]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/011Groups of the periodic table
    • H01L2924/01105Rare earth metals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049Nitrides composed of metals from groups of the periodic table
    • H01L2924/04944th Group
    • H01L2924/04941TiN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/40Details of apparatuses used for either manufacturing connectors or connecting the semiconductor or solid-state body
    • H01L2924/401LASER
    • H01L2924/402Type
    • H01L2924/4025Type being a gas
    • H01L2924/40252CO2 LASER
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • H05K1/0353Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0373Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0206Materials
    • H05K2201/0209Inorganic, non-metallic particles
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09472Recessed pad for surface mounting; Recessed electrode of component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09509Blind vias, i.e. vias having one side closed
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979Redundant conductors or connections, i.e. more than one current path between two points
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0038Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/31504Composite [nonstructural laminate]
    • Y10T428/31678Of metal
    • Y10T428/31681Next to polyester, polyamide or polyimide [e.g., alkyd, glue, or nylon, etc.]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

12 4543 五、發明說明(1) 領域 本' Sx明疋關於_種丰连練 是,關於-種晶片:二襄之印刷插線板。特別 係以半導體晶片固、ίΐ 之印刷插線板’其形成 樣大!固疋在一個、具有和該半導體晶片幾乎- 薄的球狀柵極陳2刷插線板,更特別是’關於-種非常 作為)型塑膠封裝之印刷插線板。 晶片被:二作為终產/之印刷插線板,具有-個半導體 UMq 7器、特殊功能積體電路 :的主機板==他然有烊 Utii術之描沭 你冤子機口或设備中。 ^知的晶片級封裝(CSP) 環氣鉍租取疏;Π; 0 土體材料’主要是從玻璃 來:膜材料和陶究材料、所形成的薄膜 :巨離:0,或更大’然而卻希望能降低封裝的厚度、 r球二1 : 此’近年來’焊球的直徑愈來愈小,而且 斗球的間距、以及電路的線,間隙間的距 J =勢引起了:基板的熱阻,在吸附水氣後、多層板的 電絕緣’以及防徙動性質的問題。 在習知的塑膠球狀柵極陣列(p,A)和晶片級封裝 二板知ΐΐίΐ材料的附著性”遺著焊球墊大小的減少而 其ft:瑕疯。再者’因為基板的厚度很小,由 ,在基=正面與反面上之焊料絕緣塗料的厚度之變異性 (vanabiHty),以及銅箱的殘餘比例的差’所以
89102305.ptd 第7頁 4543 1 2 五、發明說明(2) 插線板不可避免地進行曲扭。 發明之概述 本發明的目的’是提供一種晶片級封裝之印刷插線板, 碁秦能,克服煤.球對基體材.料嚴息I著i,而其低的附著性 是由於減少焊球的大小所引起的。 本發明的另一個目的,是提供一種晶片級封裝之印刷插 、 線板,.義ΐ:旅Ip慰插線板的典扭被降展j,而且以引線接 -合法或是倒裝片接合法、將半導體晶片固定在印刷插線板 上,所形成的半導體塑膠封裝的曲扭,也被降低了。 本發明的更進一步目的’是提供一種晶片級封裝之印刷 Γ 插線板,其係能克服熱阻’和在吸附水氣後的電絕緣 及防徙動孤質的退氣(組狀ion );其退化是由於降 低封.裝的厚度、大小和重量所引起的。 根據本發明1 ’是提供一種半導體塑膠封裝之印刷插線 板’其作為晶片級封裝的基板之印刷插線板,係具有以厚 度0. 2mni或更小的絕緣層所形成的雙面覆銅的層製品,並 具有鋼箔在其兩表面上’一銅箔在一表面而一銅箔在另外 一表面’其中雙面覆鋼的層製品、有上方的銅箔表面以及 下方的銅箔表面,該上方的銅箔表面有一引線接合或是倒 裝片接合的終端、將半導體晶片的終端連接到該基板上, 和有一銅墊、其位置在該銅墊可以電路連接到該引線接合 或是倒裝片接合的終端、並且可以連接到在下方的鋼表面 所形成的隱蔽介層洞,該下方的鋼箔表面有一焊球固定 墊、其位置符合於該銅墊,該焊球固定墊本身至少具有兩
89102305.ptd 第8頁 4543 1 2 五、發明說明(3) 個隱蔽介層洞,並且以道 球固定墊、為了要固定導= = = 墊的反面之焊 料、並充填到隱蔽介^洞用垃解的知球電路連接到導電材 根據本發明1,進〜參担 面覆銅的層製品之絕緣4一述么^ 包含多官能性氰醆酯和續":a薄膜、其中附著了一種 固性樹脂組合物,或是!=的;聚物為主要成份之熱 又疋廷類薄膜的多層板。 根據本發明1,更進—+捭 雙面覆銅的層製品之絕緣步/供/述 德七入夕—处U β 緣層,為一層合板、其形成是以一 匕3夕吕月Μ生氰酸酯和該氰酸酯 熱固性樹脂組合物、來缉,、杳故使, ^ , 7來汉潰一強固基板,並且乾燥此被浸 /賈的強固基板、來得到帮贩y域 片薄膜的層製品。 4片薄膜,以及形成該聚醋移 根據本發明2 ’是提供一種半導體塑膠封裝之印刷插線 Ϊ爲ί印刷插線板之形$:是提供了-個以銅洛形成的覆 叉層製品、# 一個以熱固性樹脂組合物來浸潰、15〇㈣到 4〇 Am厚的玻璃纖維之基體材料,—鋼猪在該基板的一表 面而一銅箔在該基板的另外一表面,排列了至少一個半導 體晶片接合終端、一個焊球連接墊、一個連接接合終端和 該墊的鋼箔電路、以及在該覆鋼層製品中的一個通孔導電 材料、來形成一個電路板,然後,在全部的正反表面上、 堆積了玻璃纖維之基體材料/熱固性樹脂的聚醋膠月薄 膜’在加壓和加熱下層合形成該合成物組合,然後再移開 在該接合終端的至少部份表面、和該焊球連接塾的至少部 89102305.ptd 第9頁 454312 ________ 五、發明說明(4) 份表面上之玻璃纖維和熱固性樹脂組合物形成之基體材 料,來露出電路。 根據本發明2,進一步提供上述的半導體塑膠封裝之印 刷插線板,其中的玻璃纖維,至少一個厚度為5 0 ± 1 〇 y m、重量為35到60g/m2、以及氣體滲透度為5到25cm3/cm2. sec的織物。 根據本發明2,更進一步提供上述的半導體塑膠封裝之 印刷插線板,其中的熱固性樹脂組合物,是一種包含多官 能性氰酸酯和該氰酸酯的預聚物為主要成份之熱固性樹脂 組合物。
根據本發明’是提供一種晶片級封裝之印刷插線板,其 中’烊球對基板的附著性是優良的,而且再者,由於使用 上述的樹赌,使得像是熱阻、在吸附水氣後的電絕緣,以 及防徙動性質之類的性質都很優良。 ;§j_之詳細玆.sq 附於本專利說明書的圖示中 ^入在上方表面的一個銅墊^代表直徑為— =氣親’ C代表焊球,〜dA表 料
势,熱周悚教脂層,e代表在下方表面的一個焊球 :銀膏U鍍·,g代表一個電鍍絕緣塗料,匕代表· 表-個封桿樹脂(Sealing resin) 面、其/卜Λ 騎電材料,n代表—個鍍鋼表 其為上方表面塾的反面,。代表—個鋼箱,p代表f
4543 1 2
五、發明說明(5) 電路,q代表一個通孔,r代表一個聚酯膠片薄膜,s代表 一個譽導體晶片接合墊的部份,t代表一個焊球墊的部 份,u代表一個未滿的樹脂(under η u resin ), v代表 一個緩衝墊(bump ) β 根據本發明1,是提供一種晶片級封裝之印刷插線板, 其中,焊球對基板的附著性是優良的,而且再者,由於 用特定的樹脂,使得像是熱阻、在吸附水氣後的電絕緣, 以及防徙動性質之類的性質都报優良。 2據本發明2 ,是提供一種晶片級封裝之印刷插線板, 中,該印刷插線板的曲扭被降低了,而且由於 白勺樹脂,使得像是熱阻、在吸附水氣後的電絕緣,以及^ 徙動性質之類的性質都很優良。 防 將所提供:晶片級封裝之印刷插線板的組成, 媸故ί圖 ',以引線接合法來接合半導體晶片和印刷插 線板的系統為基礎,來解釋。 使用厚度為0. 2mm或更小的雙面覆銅 ί導=片的基板。在該覆鋼層製= 印刷插線板時,則形成一倒連接半導體晶片和 ,接到上面引線接合的終端’並且可、=可以 (b )的導電材才4 )、來、由隱蔽"層洞 面覆鋼的層製品的表面。利用在該雙 的上方表面上之㈣,來形成該上方表 4 5 4 3 1 2. 五、發明說明----- 的鋼塾(a)。在下方表面上的障蔽介®、n 中,形成一焊球固定塾之圓周範圍 的ΐ 來形成該固定墊(〇。本發明 的特色為:在一個固定墊(e )中,?小 ; 7洞。該鋼墊(a ),和該隱蔽介層洞的導電:η蔽” ΚΙ;接1隱蔽介層洞的導電材料^ Si上方 定墊()“1的2上之鍍銅表面(η)、以及該焊球固 成的。以像是銀膏(h)的熱導黏著劑,將半導體 ;主1"接5並固定在基板上。再以一接合線⑴,將 體:'片⑴=到該接合終端(1)。最後再以封 3月:⑴’將該半導體晶片、接合線和接合終端密封 在本發明1中,基板的材料並無特別要求。上面的材料 ::從已知的材料來選擇’例如’像是一種雙面覆銅的層 卜、其形成係將銅结直接或以黏著劑貼到薄膜的兩表面 雔一種如此層製品之多層板,一種厚度為0·2關或更小 =面覆銅之層製品、其形成係以熱固性樹脂組合物來浸 >貝有機或無機纖維的非織造物或織物、乾燥此被浸潰的纖 維來得到聚i旨膠月、使用一層聚酯膠片薄膜或是二或多層 的聚酯膠片薄膜的疊層、放置銅謂在該薄膜的兩表面上、 在加壓和加熱下接合這些薄膜,以及一種如此層製品之多 層板。 上面的有機纖維’包括一般已知的纖維,像是液晶聚酯
89102305.ptd 第12頁 4543 1 2 五、發明說明(7) 纖維和全芳香族聚醯胺纖維。該無機纖維包括一般已知的 玻璃纖維《可以使用上面任何一個纖維之織物或非織造 物。也可以使用這些的混合纖維。 上面的薄膜可以從一般已知的薄膜來選擇。特別是,可 以從聚醯亞胺薄膜或是乙二醯酯(parabanate )薄膜中來 選擇。 在一個塾中,製造至少兩,隱蔽介層洞的方法,可以從 已知的方法來選擇。例如’可以從一般已知的方法來選 擇’像是:一種方法、其中具有小直徑的洞、分別在銅箔 中經由前蝕刻製得、雨具I能量為5到 )之.低能量.;.氧.化..破.氣搫雷射來輻.射該洞、在.雙面覆觀,激 層.製'品本a v來製摄具有.特孤九真良 雙面覆銅的層製品成多層板中、以二氧化碳氣體雷射來製 得隱蔽介層洞的方法、其中處理被雷射輻射的表面來形成 一金屬氧化層,一種輔助材料、像是包含金屬化合物粉末 或碳粉的至少一種粉末、具有熔點至少自0 0 °c以及鍵能至 少30 OU/mol之塗層組合物、以水溶性樹脂應用到上面表 面而形成一塗層,或是排列一個將該輔助材料貼到熱塑性 薄膜的一表面而製得的製造洞的輔助薄膜;為了要使得該 輔助材料面向一銅箔表面,並且經由該輔助材料、以二氧 化碳氣體雷射直接輻射該銅箔表面、來進行並移去鋼箔, 較佳的是,一種以準分子(exc i mer )雷射或是釔鋁石榴 石(YAG )雷射來製造洞的方法;以及一種以電漿來製造 洞的方法。該辅助材料或是該辅助薄膜的總厚度,為3 〇到
89102305.ptd 第13頁 4543 1 2 五、發明說明(8) 2 Ο Ο μ m較佳。 在本發明中,以一氧化碳氣體雷射來製造洞之辅助薄 膜,可以使用現有的。然而,為了製造具有好晶面式的 洞,在製造洞時,將該辅助薄膜放置在一多層板上,並且 使其與該多層板緊密接觸,儘可能接近為佳。通常,該輔 助薄膜是以膠帶或其他,來固定並緊密地貼在多層板、或 是雙面覆銅的層製品的表面上。為了達到該辅助薄膜對於 多層板、或疋雙面覆鋼的層製品、更完全的接觸,該辅助 薄膜被貼在多層板、或是雙面覆鋼的層製品上,使得該薄 膜之塗有樹脂的表面、面向上面的板或層製品、並且在加 熱和加壓下被層合,或者是塗有樹脂的表面、預先以水濕 潤3 μ m或更小的深度,和上述一樣貼上該薄膜、並且在^ 溫和加壓下被詹合較佳々,▲毖顧應表史:該薄應氣氣 可以使用非水溶性’但溶於有機溶劑的樹脂組合物,來 作為樹脂组合物。然而,因為在以二氧化碳氣體雷射來韓 射時、如此的樹脂組合物可能會附著在洞的附近,在這個 例子中’需要有機溶劑而非水來移去該樹脂。因此,很不 情願地使用’由製程看來很麻煩的有機溶劑,並且進— 步’在後步驟中引起污染的問題。 用於本發明的基板、或是用作部份基板的熱固性樹脂組 合物之樹脂,可以從一般已知的熱固性樹脂來選擇。特別 是’從環氧樹脂、多宫能性氰酸酯樹脂、多宫能性馬來醯 亞胺氰酸酯樹脂(mal eimide-cyanate ester )、多官能
89102305. ptd 第14頁 4543 1 2 五、發明說明(9) 性馬來酼亞胺樹脂、或是包含未飽和基之聚伸苯喊 (polyphenylene ether)樹脂中,選擇出來。可以單獨 或者合併使用這些樹脂。爲具有..高輸出功..率的A氧化 ^ ^ ^ ^ M ^. ^ it. ?L λ. ^ 玻:璃轉〔化溫卷為1 5 〇 t:.或更高之熱固悻樹賸組會物轉焦:。 由防潮性能、防徙動、以及在吸附水氣後的電子性質看 來’以使用多官能性氰酸酯樹脂組合物較佳。 多官能性氰酸酯化合物,為本發明中的一個適當的熱固 性樹脂成份,屬於在每個分子中至少有兩個氰氧基的化合 物。它的特殊例子包括有:1 3_或丨,4-二氰氧基苯 (dicyanatobenzene ) ,1,3,5 -三氰氧基苯,1,3-、1,4- 、1,6-、1,8-、2,6 -或2,7-二氰氧基萘,1,3,6-三氰氧基 萘’4, 4-二氰氧基聯苯,雙(4_二氰氧基苯基)甲烷 (bis(4-dicyanatophenyl)methane) ,2,2-雙(4-氰氧 基苯基)丙烷,2, 2-雙(3, 5二溴基-4-氰氧基苯基)丙 院’雙(4-氰氧基苯基)醚,雙(4_氰氧基苯基)硫醚, 雙(4-氰氧基苯基)颯,三(4-氰氧基苯基)亞磷酸鹽, 以及由盼酸清漆(novo 1 ak )和氰基鹵化物之間反應所得 到的氰酸酯。 除了上面的化合物之外’也可以使用在日本專利公告號 碼41-1928 、 43-18468 、 44-4791 、 45-11712 、 46-41112 、 和47-26853以及JP-A-51-63149中,所揭示的多官能性氰 酸醋化合物。再者’赢叉嚴像j康f # 且憂有以霁H(dimeriziAg..)這些任何一個多官難性氰
454312 五、發明說明(ίο) I廳Jfc .倉物.中的养氧基來形成的三氮畊環之預聚物。上面 的預聚物,係在像是礦物酸或路易士酸的酸類、像是經氣 基納(sodium alcoholate)或四級胺的驗類、或像是碳 酸鈉的鹽類存在中,聚合上面的多官能性氰酸酯單體來獲 得的。該預聚物部份包含了未反應的單體、為單體和預聚^ 物的混合的形態,並且上面形態的預聚物也適合用於本&
明。通常,在使用之前,將它溶解在可被溶解的有機溶 中。 W .該農氧樹脂通常,是從已知的環氧樹脂來選擇。它的牲訑 例子包括有:液態或固態的雙酚A (bisphenol A )型環氧 樹脂’雙齡*F型環氧樹脂’驗(phenol )紛酸清漆型環氧 樹脂’甲酌 ( c r e s ο 1 )紛醛清漆型環氧樹脂,脂環族 (alicyclic)環乳樹脂’以環氧化(epox^dizing) 丁二 稀、戌—婦、環己婦乙烯(vinylcyclohexene)、或是二 環戊基醚(dicyclopentyl ether)中的雙鍵來得到的聚 環氧化合物,多元醇(po丨y 〇丨),以及由含羥基的矽樹脂 和環i化醇(epohalohydrin)之間反應所得到的聚環氧 丙基化合物。可以單獨或者合併使用這些樹脂。 違聚醯亞胺樹脂通常是從已知的聚醯亞胺樹脂來選擇。 特別是從多官能性馬來醯亞胺和聚胺類的反應產物中選 的,更特別從JP-B-57-00 540 6中揭示 '具有末端三鍵的聚 醯亞胺中選的β 卜了以單獨使用上面的熱固性樹脂,然而考慮性質的平 衡’以適當地合併使用較佳。
454312 五、發明說明(11) ~ ----- 了以加不同的添加劑到本發明的熱固性樹脂組合物 中只要不損害到該組合物的附著性質。上面的添加物包 括:具有像是未飽和聚酯的可聚合雙鍵之單體,這些的預 聚物,具有低分子量的液態彈性橡膠,或是具有高分子量 的彈性橡膠、像是聚丁二烯、環氧化丁二烯、馬來酸丁二 烯、丁二烯-丙烯腈共聚物、聚氯丁二烯、丁二烯—苯乙烯 共聚物、聚異戊二烯、丁基橡膠、氟橡膠和天然橡膠,聚 乙烯,聚丙烯,聚異丁烯,聚4-甲基戊烯,聚苯乙烯,丙 婦腈-本乙稀(AS)樹脂,丙缚腈-丁二稀-苯乙稀(abs) 樹脂,MBS樹脂,苯乙烯-異戊二烯橡膠,聚乙烯_丙烯共 聚物,4-氟乙烯-6-氟乙烯共聚物,像是聚碳酸酯、聚伸 笨醚、聚颯、聚酯和聚伸苯硫(p〇lyphenyiene suifide )’以及聚胺基甲酸酯之高分子量的預聚物或寡聚物。視 需要來使用這些添加劑。再者,也可以視需要來單獨、或 者合併使用不同的已知添加劑,像是有機或無機的填料、 染料、色素、增稠劑、潤滑劑、消泡劑、散佈劑 (dispersing )、均染劑(level ing )、感光劑、阻燃 劑、拋光劑(brightener )、阻聚劑和觸變劑 (thixotropic )。視需要地將固化劑(curing )或是催 化劑,納入具有活化基的化合物中。 用於本發明的熱固性樹脂組合物,加熱會進行自身固 化。然而,由於固化速率很低,在可操作性和經濟效益等 等不良時,將已知的熱固性催化劑納入該熱固性樹脂中。 以重量計每1 〇〇部份的該熱固性樹脂中,催化劑的量是以
4543 1 2 五、發明說明(12) 重量計0. 0 0 5到1 0部份,而以重量計0 ‘ 〇 1到5部份較佳。 用於皮.致J:的”擁助:材.料立’:炼跸I少為9〇0 °c、以及鍵 熊U|3 0.0.kj/mol.的金屬化合魏.’通常是從已知的金屬 來選擇。例如’使用氧化物。該氧化物包括:像是 'itanias),像是氧化鎂的鎂氧 化合物來選擇 氧化鈦的鈦氧、丄as; ,1豕疋乳1G姨的鎮氧 (magnesia),像是氧化鐵的鐵氧化物,像是氧化鎳的鎳 氧化物,像是二氧化錳的錳氧化物,像是氧化鋅的鋅氧化 物,二氧化矽,氧化鋁,稀土族金屬氧化物, 物m的錫氧化物’以及像是氧化鶴的 包括-般已知的氧化物:像是碳化矽,碳化鎢、物 :發’氮化鈦’氮化銘,硫酸鋇,稀土族金, 風氧化紹和氫氧化鎂。再者,也可以使:化物, 末混合物之不同的玻璃。再者,可以^屬虱化物粉 敍、鋼、鐵、鎂、鐘、相 口銀、銘、叙、 鈒、鶴、和鋅:單物;粉;:::!、碎、踢、鈦、 末。再者,可以使用碳粉i ^疋绝些合金的金屬粉 這些的粒子直徑並無特別限:以:獨或者合併使用這些。 澧嚴··^氣化..碳.氟體雷射來輕私押以1 #m或更小較佳。 教散..X。因此,當其附著到;ί子被離.鮮或義^ 是洞壁的附著性質,沒有 ’對半導體晶片或 體可靠度有不利的影響,含有鈿、4響者較佳。因為對半導 不佳。上面的粉末的量以體蚪鉀或是氣離子的粉末較 到95 %較佳。將上面的粉末又=到97 %,而以體積計5 ___ 水溶液並且均句地分散 89102305,ptd 第18頁 “43 12 五、發明說明。3) 較佳。 辅=材料中的水溶性樹脂,並沒有特別的限制,而是 ^ 1搓揉、應用到該銅箱表面、並且乾燥或形成在一薄 時、不會從鋼箔表面上剝落下來之水溶性樹脂中選出 ’例如,從已知的樹脂,像是聚乙烯醇、聚酯、聚醚 殿粉中選出。 含金屬化合物粉末、碳粉或金屬粉末、以及樹脂的組合 之製造方法’並沒有特別要求。上面的方法包括已知的 才,像是種方法’氣在高溫X不用任' 何農象 ,來搓樣材料,並且擠出該被提揉的混合物、以幾輝兔# t接金;到熱塑性樹脂的表面;以及一種方法,係溶解一水 冷性樹脂於水中,添加上面的粉末,以攪拌均勻地混合, 應用該作為塗層組合物的混合物、到熱塑性薄膜的表面, 並乾燥之而形成一塗層。該薄膜或塗層的厚度,並無特別 的限制’然而其乾燥後總厚度為3 0到2 〇 〇 y 。 再,’可以使用一具體例,其中處理銅箔表面來形成一 金,氧化物,然後再同樣地來製造洞β然而,由洞的形成 看來,以使用上面的輔助材料較佳。 當·^面的輔助薄膜在加熱和加壓下、被層合在一銅箔表 面t日宁’其被應用樹脂層的一面被貼到該銅猪表面’並且 在咖·度通常為4 〇。〇到1 5 0 °C之間、而以6 0 °C到1 2 0。(:較佳, ,性壓力通常為0. 5到30kg、而以1到1 〇kg較佳,鏗由鬼、解 ^樹長層、以康筒將該輔助薄膜層合在銅箱泰面上,來繁 祖地將該樹脂層貼到鋼落表面。所應用的溫度不同,是因
89102305.ptd 第19頁 固性樹脂組合物 強固材料至B階 。堆積預定數量 酯膠片薄膜的至 該合成物組合, 製品每一面上的 箔的厚度為9到 454312 五、發明說明(14) 其所選擇的水溶性樹脂的熔點而定,也因其所選擇的線性 壓力和層合速率而定。通常,在高於該水溶性樹脂的熔點 5到20C的溫度下’完成層合作用。在室溫下、當該辅助 薄膜緊密地貼在銅箔表面時,該塗有樹脂的層表面、以水 濕潤3 v m或更小的深度、來多少溶解該水溶性樹脂,並且 在上面的壓力下層合該輔助薄膜。以水來濕潤該樹脂層的 方法並無特別限制’例如可以應用:一種方法,係以滾筒 持續將水應用到塗有樹脂的層表面,並且持續將該輔助薄 膜層合在覆銅的層製品上;或是一種方法,係持續噴灑水 到塗有樹脂的層表面,並且持續將該輔助薄膜層合在覆鋼 的層製品上。 該強固多層板的製法如下。首先,以熱 來浸潰一強固材料,並且乾燥該被浸潰的 (stage )的組合物,因此得到聚酯膠片, '龙盧機,或無.應,的 '非織造物或織物氣選擇的 的聚酯膠片薄膜’放置鋼箔在該堆積的聚 少一面上,然後在加熱和加壓下層合形成 ^成覆銅的層製品。在所得到的覆鋼層 η度為3到較佳。作為= 3 5 // m較佳。 ns⑴ 係以在為多層★。製造覆銅的多層板 加商Si;體鋼層製品中、形成-電路 9膝片或是無基體材料的一樹!
4543 1 2 五、發明說明(15) 薄,、貼有樹脂的一銅箔、以及利闬塗層組合物形成的一 樹脂層,並放置一銅箔或多個鋼箔在最外層的—個或多個 表面上’然後在加熱和加壓下、以在真空中較佳、來層合 形成該合成物組合。該強固材料的厚度小時,則具有高^ ,^佳(基板的空隙降低)。例如,厚度為5G心的玻璃 織物之強固材料,其密度為5 0到6 0 g/m2。 在反面表面上的焊球墊,直徑通常為2〇〇到5〇()"爪,並 f在焊球墊亡至少有兩個洞。每個洞的直徑並無特別的要 ,,當製造高密度的印刷插線板時,通常為5 〇到丨5 〇 。 當該辅助材料被排列在表面時,以二氧化碳氣體雷射來製 is·洞較it °亥/同被製作為隱蔽介層洞。即使一個洞穿透了 在相反表面上部份的銅落,則在相表面上的銅箱中 Ϊ屢巧 Ί。像得.面的洞的部份、對製造印刷插線板尊绛有影… •"f;. vVAin:'.*' 1放置該辅助材料在覆銅層製品上、並且以例如 6^/PUlSe的雷射能量來直接輻射、製造 洞時,在㈣圓周範固中產生銅㈣焊片(bu ;非常電路時,則必須降低該表面銅箱的厚度? 在:二氧化碳氣體雷射來輻射之後,該銅错的表面被:次 元機械性触刻、或以化學藥品來移去在厚度方向4二 個別銅箱較佳。在這個例子t,該烊片:可以被 且可以製得有mi殘留= f格(pattern),而 留在母一個洞附近、並適合用於高密
454312
五、發明說明(16) 度的印刷插線板的介層洞。在這個例子中,蝕刻較機械拋 恭為_佳.,因'為可....以..谷易'地移夫在:?同·部份的焊片、並且因為 蝕刻並沒有由拋光所引起的尺寸改變。 移去在洞部份上產生的銅焊片、和移去在厚度方向中部 份的表面銅箔的方法’並沒有特別的限制,包括例=在 JP-A-02-00887 、 JP-A-02-22896 、 JP-A-02-25089 JP-A-02-25090 ' JP-A-02-60189 ' JP-A-02-166789 JP-A-03-25995 ' JP-A-03-60183 ' JP-A-03-94491 JP-A-04-1 99592和JP-A-04-263488中所揭示的,以化學藥 品溶解移除金屬表面的方法(稱為SUEP方法)。速率=乂 為0.02到1.0#m/sec完成触刻。 ^爷 當以二氧化碳氣體雷射來製得該隱蔽介層洞時,從開於 到結束,可能選擇20到60mJ/pulse的能量來完成轄射:^ 而’當作為前面表面和内層的銅箔先被移去時,則選擇& 高的能量來移去銅猪較佳,並且因鋼箔的厚度而定、來^ 擇5到35mJ/pulse的能量、用來輻射而形成洞的洞底部、 份。製造該洞的條件,可能因其作為内層的鋼箱是否 而不同。 +
可以依據一般已知的鍍銅的方法來完成鍍銅。再者,可 以用喷鍍來部份地充填該隱蔽介層洞。 ° 本發明2使用厚度為150以m到40 μ m的玻璃纖維之雙面覆 鋼的層製品’來作為一基板。本發明2提供一種印刷插線 板,其形成是由:排列了至少一個半導體晶片接合終端、 一個煤球連接塾 個連接接合終端和該塾的銅箱電路
454312 五、發明說明(Π) 以及在該覆銅層製品中 電路板,然後,在全部的一個通孔導電材料、來形成一個 基體材料/熱固性樹脂的、正反表面上、堆積了玻璃纖維之 層合形成該合成物組合/酯膠片薄膜,在加壓和加熱下 部份表面、和該烊球^扳^後再移開在該接合終端的至少 和熱固性樹脂組合物,也的至少部份表面上本破鬼;鱗專 .的鋼箱表面,並且完成妙趟出電路,選撣性地預處琿終蠕 , :^ Λ戮鎳和鍍金。 半導體塑膠封裝的形忐一-^ ^ 曰Κ垃人* η门―—成如下。以熱導黏著劑’將半導體 日日月接合並且固定在, ’V月a * 面印刷插線板的表面,再以引線接 合法連接,然後用一封焊 W深接 4坪树月曰將该表面密封起來。否則, 半導體晶片下方表面的緩衝墊被熔解、敢且以倒裝片接合 法貼到該印刷插豢板.的終端,以未滿(under fiu )的樹 脂、將該半導體晶片的下方表面接合並且固定,然後, 解焊球並貼到該印刷插線板的反面。 當使用多官能性氰酸酯樹脂組合物、作為雙面覆銅的層 製品之熱固性樹脂組合物時,篇鼻得到套熱息、屬衣屬慮 理後晚電絕,緣士私及见徙氣性質都根優良之:、印胤氣線想: 本發明2之雙面覆銅的層製品,包括有,以熱固性樹脂 來浸潰一般已知的玻璃纖維織物、並且乾燥該被浸潰的玻 璃織物、所製得的雙面覆銅的層製品,以及如此層製品之 多層板。該玻璃纖維織物、通常包括像是E、S、和D玻璃 纖維的已知玻璃纖維之織物,並且該玻璃纖維織物、厚度 通常為30到1 50 y m。該玻璃纖維的製法,是使得一樹脂組 合物附著於一玻璃纖維上’在加熱下、B階化(B-staging
;r 454312 五、發明說明(18) )該樹脂組合物,並形成厚度為4 〇到1 5 0以m的層製品。也 可以使用這些絲線(f ilament )的混合產品。作為一個基 體材料’厚度小的基體材料以高密度較隹。該基體材料, 厚度為50±l〇em、重量為35到60g/m2、以及氣體滲透度 為5到25cm3/cm2· sec。至少使用一個如此的基體材料。再 者’可以使用厚度為3 0到1 5 0 # m的玻璃纖維織物。該編織 的方法並無特別要求,而以簡單编織(plain„woveri )的 纖維較佳。 用於本發明2中熱固性樹脂組合物的樹脂 所描述的熱固性樹脂中選擇較佳 不只在本發明2中,在本發明1中也可以使用無機的絕緣 填料。該無機的絕緣填料,是從一般已知的填料來選擇。 它的特殊例子包括有:像是天然矽石、緞燒(calined) 石夕石和非晶梦的石夕石’白碳(wh i te carbon ),二氧化 鈦(titanium white ),氣凝膠(aer〇gei ),黏土 (c 1 ay,水合矽酸鋁),滑石(ta丨c,天然含水的矽酸鎂 )’.矽灰石(wollastonite,天然矽酸鈣),天然雲母 (mica :矽鹽),合成雲母,高嶺土(kaolin,中國黏土 氧化ί氧’氧化銘’珍珠岩(PerUte) ’ 1氧化紹和氫 、。上面填料的量,基於該組合物以重量計為1 〇到 丄:以重量計20到7〇%較佳。該無機的絕緣填料之 氧;:i?、:i更小較佳。在本發明中’使用氫氧化鉬和氫 燃性,、並ΐ:物較佳,®為上面的混合物適合用來賦予阻 ,並適°以一氧化碳雷射來製造洞。
4543 1 2 五、發明說明(19) a具有玻璃纖維的基體材料之覆鋼廣製品的製 先,以熱固性樹脂組合物來浸潰該基 h ;=物^一聚酿膠片,;:=聚=二 ^面上,然後在加熱和加壓下、而在真 ^合?組合…表面上的每一層㈣,厚度二: 。:美::/發明2中’具有玻璃纖維厚度為4。到 150㈣的基體材料之覆鋼層製品,由於 =L(nerve),並且因為在上方和下方表面絕緣焊料 =異性:以及㈣剩餘比例的差異,極有可能被曲扭。 ,此’作為印刷插線板時,其可操作性不^,並且缺陷的 ==报,。本發明2'可以提供一種印刷插線板,鬼太灰地 萨I了二曲扭性質Λ是將玻璃纖維之基體材料/熱固性樹 ^的聚嚴廉片.薄膜、耕巧在吾有電路和通孔的印刷基板之 正尽奉。面上,並且視需要地以化學方法處理表面,來代g ^用上面的絕緣塗料,在其外部放置放鬆(r e丨ease )的 ,膜,以及在加熱和加壓下、而在真空中較佳、形成層合 物來整合(integrating)。 在該接合終端的部份表面、和在反面表面的焊球連接墊 的邛伤表面上之玻璃纖維之基體材料/熱固性樹脂層,以 喷砂法(sand b 1 as t )來移去較佳,然後例如以軟蝕刻, 來處理該銅箔表面,並且依據習知的方法完成鍍鎳和鍍 當然’該印刷插線板可以由二氧化礙氣體雷射來處 根據本發明1的半導體晶片尺寸級封裝之印刷插線板,
ί 4543 1 2 五、發明說明(20) ', 是提供一種印刷插線板’其.中,煤球的剪力太太地改良 、‘d °再者,當使用多官能性氰酸酯和該多官能性氰酸酯的 預聚物、作為覆銅層製品之樹脂的必要成份時,係提供了 一種晶片尺寸級封裝之印刷插線板,其在熱阻、壓力鍋處 理後的電絕緣,以及防徙動性質都很優良。 根據本發明2的半導體塑膠封裝之印刷插線板,可以得 到一印刷插線板,其中該印刷插線板的曲扭被降低了,而 且以引線接合法或是倒裝片接合法、來固定半導體晶.片的 半導體塑膠封裝的曲扭,也被降低了。再者,當使用多官 能性氰酸酯或是該多官能性氰酸酯的預聚物、作為熱固性 樹脂组合物的必要成份時,係提供了一種印刷插線板,其 在熱阻、壓力銷處理後的電絕緣’以及防徙動性質都很優 良’並且其大量生產能力也很優良。 實施例 本發明將參考在下文中的實施例和比較例來詳細解釋, 保某 <亦 威,^知:&〜蠢 熏· 總’ 除非另外指定。 實施例1 將900部份的2,2 -雙(4-氰氧基苯基)丙烧,和1〇〇部份 的雙(4 -馬來亞胺基苯基)甲院,熔解到1 5 0 °C並揽摔使 得反應4小時,而得到一預聚物。溶解該預聚物於甲基乙 基酮和二甲基曱醯胺的混合溶劑中。在該合成混合物中, 加入400部份的雙酚A型環氧樹脂(商品名稱:Epikote 1001’由丫1^3-81^11£?〇又7 1(.1^所提供),以及6 00部份 的甲酚酚醛清漆型環氧樹脂(商品名稱:ESCN-220F,由
89102305.ptd 第26頁 454312 五、發明說明(21)
Sumitomo Chemical Industry Co. , Ltd.所提供),然後 均勻地溶解並混合這些物質。再者,加入〇 · 4部份的辛基 鋅鹽(zinc octy late )作為催化劑,溶解並混合之。在 該合成混合物中’加入5 0 0部份的無機填料(商品名稱:
Calcined Talc BST #200 ’ 由Nippon Talc K.K.所提供 ),和8部份的黑色素,然後均勻地攪拌並混合這些物 質,來製得清漆A ( varnish )。重量53g/m2,厚50 的 玻璃織物,以上面的清漆浸潰,然後在1 50eC下、乾燥該 被浸潰的玻璃織物,而製得具有凝膠時間為120秒(在170 °C下)、以及具有樹脂組合物成份以重量計為51 %之聚酯 膠片(聚醋膠片B)。個別厚度為12从m的電解銅箱,被放 置在合併上面聚酯膠片B的兩層薄膜之上方和下方表面, 一銅箔在一表面而一銅箔在另一表面’然後在3〇mmHg或更 小的真空下、溫度2 0 0 °C和壓力2 0kgf / cm2下2小時、層合 形成 5亥合成物組合 134鼻m的.雙面、覆銅的層製品C。 分別地,以溶解聚乙稀醇粉末於水中而製得的清漆中, 加入800部份的滑石(平均粒子直徑:0. 4 e m,商品名 稱:BST #200 ),然後均勻地攪拌該混合物。該混合物 被應用到’厚50 /zm的聚對苯二甲酸乙@旨(polyethylene terephthalate)薄膜的一表面上,使得形成厚3〇#m的塗 層,然後在11 0 °C下、乾燥所形成的塗層3 0分鐘,來得到 具有滑石成份以體積計為40 %之輔助材料d ^放置該辅助 材料在上面的覆銅層製品上,使得該樹脂表面面向銅箔
89102305.ptd 第 27 頁 4543 1 2
五、發明說明(22) ------ 面,然後在加壓下、以10:(rc熱滾筒、將該輔助材料貼在 上面。在7mm Χ7ιπιη正方形區域的銅箔中,用輸出功率為 4〇mJ/pulse的二氧化碳氣體雷射、以i脈波直接輻射,'來 製得100個洞。然後,將二氧化碳氣體雷射的輸出功率降 低至20mJ/pulse,並以輸出功率為2〇mJ/pulse輻射丨脈波 在該洞底部。再者,該介層洞底部,即在上方表面鋼箔的 樹腊面’以輸出功率為7mJ/Pulse輻射][次,像得在直3 0 0 //m ^ ^ ^ ^ Μ; Mm ¥] m ( ® 1中b )。元成SUEP處理來溶解銅,直到銅箔的剩餘厚度為 5/zm’並放置該合成板於電漿裝置中,以氧氣氛圍處理1〇 分鐘、再以鼠氣祝圍處理5分鐘’來移去在介層洞中殘餘 的樹脂層、也移去在正面和反面的表面上銅箔的前面層, 因此該板的厚度為4#m。放置該合成板於過錳酸鉀水溶液 中’以超音波的濕式處理,然後將其一般的無電極電鍍和 以銅電鍍(圖1中f和m )。軟蝕刻該合成物表面,以習知 的方法、在正面和反面的表面形成電路(線/空隙=5 〇 / 5 〇 # m )’並且’在至少除了半導體晶片部份、接合墊部份 (圖1中1 )、和焊球墊部份(圖1中e )之外.,以電鍍絕緣 塗料(圖1中g)來覆蓋該板的任何範圍。以錄和金來電錢 該板而得到印刷插線板。以銀膏(圖1中h )、將半導體晶 片(圖1中i )接合並固定在該印刷插線板上,再以一接合 線(圖1中j )、連接到該接合墊(圖1中1 ),然後以樹脂 (圖1中k)完成密封。再者’熔解並貼上焊球(圖1中c )。評估因此得到的印刷插線板,結果顯示於表1。
89102305.ptd 第28頁 五、發明說明(23) S^MlM2 氧樹脂(商品名稱:Epikote 5°45), 雔f脸氧脂(商品名稱:ESCN-220F) ,35部份的 ϊ和二甲ίΠ份的2_乙基+甲基咪°坐,溶於曱基乙基 物。胺的混合溶劑中’然後均勾地授拌該混合 璃镳雜面的混合物來浸潰和實施例1中所使用的相同破 時門η並且乾燥該被浸潰的玻璃纖維,而得到具有凝膠 夺間為1 5 0秒之聚酯廢片ε。 产合併上面聚輯膠片Ε的三層薄膜,將厚12//1^的電解銅 冶》放置在該合併薄膜的兩表面上,一銅箔在一表面而一 鋼箔在另一表面。在3〇mmHg或更小的真空下、溫度19〇它 和壓力20kgf/cm2下、層合形成該合成物組合,而得到包 括銅箔厚度的總厚度為丨89# m的雙面覆銅的層製品。同樣 地衣一個個別直徑為1 2 5 // m的隱蔽介層洞,以終波喷梦 (Pulse Plating) (Japan LeaRonal 方法 .'_教·,燕.,屬,...薦,麗..',,,以體積计2 7 % 。其後,以和實施例1中相同 的方法製造印刷插線板,並連接一焊球。評估因此得到的 印刷插線板’結果顯示於表1。 __比較例1和2 除了在焊球墊上’沒有隱蔽洞或者1個直徑為丨〇 〇 # m的 隱蔽洞之外’重複實施例1來得到印刷插線板。評估因此 伸到的印刷插線板,結果顯示於表I。 比較例3 除了以重量為48g/m2和厚度為50 的玻璃纖維,來取
89102305.ptd 苐29頁 4543 1 2 五、發明說明(24) 代該玻璃纖維而製得一聚酯膠片,並且使用上面的聚酯膠 片之兩層薄膜來取代使用聚酯膠片E的三層薄膜’來重複 實施例2。然而,在焊球墊中並無隱蔽洞。評估因此得到 的印刷插線板,結果顯示於表1。 表1 實施例 比較例 1 2 1 2 3 玻璃轉化溫度 235 160 235 235 160 球形剪力 1.15 1.09 0.52 0.71 0.48 黏彈性 2.0 1.9 " - 1.0 壓力鍋處理後絕緣電阻(Ω ) 正常狀態 4x10" 6xlO,3 處理後200小時 6xl〇'2 2xlO,J 處理後500小時 6X1011 < mo】1 處理後700小時 4xl〇'° - 處理後1000小時 2xl0,fl 防徙動性質(Ω ) 正常狀態 6x10" 2x 1013 處理後200小時 5xl0M 1x10'° 處理後500小時 3x10” 4xl09 處理後700小時 1x10" < 1x10s 處理後1000小時 9xl0,tt - 熱循環測試 1.6 2.3 - 2.5 - 註:玻璃轉化溫度:°C,球形剪力:kgf,黏彈性:xl 01G 達因(dyne) /cm2 <測量方法> 1 )玻璃轉化溫度 依據DMA方法來測量。 2 )球形剪力 在橫向張力,(1 a t er a 1 t ens i on )下測量。
89102305.ptd 第30頁 454312 五、發明說明(25) 3 )黏彈性 依據DMA方法,使用以蝕刻移去銅箔之層製品,來測 量。 4 )壓力鍋處理後絕緣電阻之值 形成聚有線/空隙= 50/50弘m的梳形晶格’將所使用的 聚酯膠片放置其上,層合形成該合成物組合’並在121 'ΐ、2大氣壓力下、持續預定的一段時間來處理該合成層 製品,然後在25 °C、相對溼度60 %下持續2小時,使用 500VDC、在處理60秒後測量在終端之間的絕緣電阻。 5 )防徙動性質 和上面4 )中相同的測試件,在8 5 °C、相對溼度8 5 % 下,使用50 VDC,然後測量在終端之間的絕緣電阻。 6 )隱蔽介層洞的熱循環測試 其中具有隱蔽洞的1〇〇個墊,由一個表面到另一個表 面’交互地連接,然後該被連接的墊,作200個熱循環測 試’其中每一個循環是由:在260 °C下浸潰在烊料中持續 30秒-> 室溫持續5分鐘,所組成的。顯示電阻值變化比例 的最大值。 實施例3 製備和實施例1中所使用的相同清漆A,然後以和實施例 1相同方法來製備清漆F,其中除了省略了加入5 〇 〇部份的 無機填料和8部份的黑色素。厚50的玻璃織物(重量: 53g/m2 ’氣體參透度:7cm3/cm2.sec),以該清漆a浸潰, 然後在150 下、乾燥該被浸潰的玻璃織物,而得到具有
4543 12 五、發明說明(26) 一 ---- ,膠時間為1 20秒(在1 70 t下)、以及具有樹脂組合物成 知以重量計為5 1 %之聚酯膠片G丨’或是具有凝膠時間為 1 〇 3秒、以及具有樹脂組合物.份以重量計為6 〇 %之 膠片G2。 將個別厚度為的電解鋼箔(圖2中〇),放置在合 併該聚醋膠片G1的兩層薄膜的兩表面上,然後在3〇關 量ΛΙ暮息X,、眞
舍衆成廣今成物粗会,來得到絕緣層厚度為〗2!·的雙面 覆銅的層製品Η (圖2中步,驟(i ))。以機械鑽孔機,在 上面的雙面覆銅層製品中,製造直徑為15〇vm的通孔(圖 中Q),,並且以銅來電鍍整個的雙面覆銅層製品。在兩表 面上製付電路(圖2中p),並處理該表面來形成黑色的氧 化鋼’因此得到印刷插線板I (圖2中步驟(2 ))。將上 面的聚酯膠片G2 (圖2中r )的薄膜,放置在該印刷插線板 的f表^面上’一薄膜在一表面而一薄膜在另一表面,將 拳各的薄膜放置在其上’再同樣地層合形成該合成物組合 p圖2中步驟(3 )和(4 ))。然後,該放鬆的薄膜被剝 洛’並使用液態UV選擇性熱固性塗層組合物在整個板的正 2反^ ^ ’並乾燥之°然後’除了在正面的接合塾部份(圖 之3 ’以及在反面的球形墊部份(圖2之七)之外,以uv 二射該板’來固化該塗層紐合物。以鹼性水溶液完成顯 二來移去該接合墊部份和球形墊部份的絕緣塗料,並以 =法將坡璃纖維之基體材料/熱固性樹脂組合物移去, 出接合塾和焊球墊(圖2中步驟(5 ))。然後溶解移
89102305.ptd 第32頁 454312
去該塗層組合物。然後,敕舳丨 據習知方法來完成鍍錄和鍍金銅箱表面’並依 大小的印刷插線板j。評估因金此x 25mm正方形 顯示於表2…艮膏(圖2中因J:印刷插線板J ’結果 ,认出.故_ H 、固)、將15mm XI 5mm正方形大 :的:導片(圖2中"接合在該印刷插線板的 二並:引線接合’然後以環氧樹腊化合物(圖, 2個表面以樹脂密封,因此得到半導體塑膠封裝κ (則 ^驟(6 ))。砰估因此得到的半導體塑膠封裝,結果 顯不於表2。 實施例4 將3290部份的氫氧化鋁,和141〇部份的氫氧化鎂(平均( 粒子直徑為1 0. 8只in ),加到和實施例3相同的清漆F中, 並充分地槐拌這些物質而得到一清漆乙。以清漆[來浸潰和 實施例3中所用相同的玻璃織物,得到具有凝膠時間為15〇 秒、以及樹脂組合物成份以重量計為γ 1 %之聚酯膠片Μ。 輿.一龙得嚴杀有氣踢時間岑35秒、以及樹觸組舍物成份以 熏量計為60 %之聚酯膠片Ν。 • - '._; .·· .·.... . 合併聚酯膠片Ν的兩層#膜,將厚1 2以m的電解銅箔,放 置在其兩表面上,一銅箔在一表面而一鋼箔在另一表面, 和在實施例3中相同的方法、層合形成該合成物組合,而 得到具有絕緣層厚度為11 9 # m的雙面覆銅的層製品。包含 : 以體積計為40%的氧化銅粉末(平均粒子直徑:〇.8从爪) a 之水溶性聚醚樹脂組合物,其在水和曱醇的混合物中之溶 液,被應用於上面的雙面覆1銅層製品的表面,使得形成厚
89102305.ptd 第 33 頁 4543 1 2 五、發明說明(28) 度為40 # m的塗層,並乾燥來形成塗層。以能量為35mJ /pulse的二氧化碳氣體雷射、輻射4次塗層、來製造直徑 為1 0 0 # m的通孔,在洞部份產生銅箔焊片、並溶解移去該 銅箔表面,使得該銅箔的個別厚度為3 # m,並移去焊片。 整個前面、反面和通孔’被鋼喷鍍丨5//111厚,而在兩表面 上形成電路。將聚g旨膠片Μ的薄膜放置在兩表面上,放鬆 的薄膜放置在其上,再同樣地層合形成該層製品,並且該 放鬆的薄膜被剝落。 同樣地使用UV絕緣塗料在上面得到層製品的兩表面上, 並乾燥之。然後,除了在正面的半導體倒裝片緩衝墊部 份、以及在反面的球形墊部份之外、以υν輻射該層製品, 以驗性水溶液同樣地完成顯影,並以噴砂法將玻璃纖維之 基體材料和熱固性樹脂組合物移去,並完成鍍鎳和鍍金, 而^到印刷插線板〇。評估因此得到的印刷插線板,結果 顯不於表2 °以倒裝片接合法、將1 5mm X 15mm正方形大小 的半導體日日片、固定在方形大小的上面的印 席板〇上’半導體晶片的下方以充滿或是未满樹脂 之11)來固定,並以溶解焊球將焊球固定到反面的表 塞雜Ξ得到半導體塑膠封裝p (圖3)。評估因此得到的半 =塑腰封裝,結果顯示於表2。 姐& ^成厚度為50/zm的塗層,應用兩層UV選擇性熱 兩表面' 付’〃在和實施例3所製備的相同印刷插線板J的 上’並乾燥之’並且在曝光後,經由顯影來移去在
4 5 4 3 12 五、發明說明(29) 反面的半導體晶片接合墊部份釦 加熱來固化該絕緣塗料後,塾部份的絕緣塗料。 插線板Q。將半導體晶片同二鍍定鎳=鍍金’而得到印: 引蠄垃人^ 像地固定在印刷插線板Q上,並 引線接σ ’而且用樹脂完成密封 R。評估該半導體塑膠封裝,結果顯示於表t 比較例5 衣z 解7_份的環氧樹脂(商品名稱:EPik〇te 環氧樹脂(商品名稱H220F)、 基乙基輞和二甲基甲醯胺的二乙[甲基咪唆、於甲 該混合物,所製得的熱固性;:::、f 2句地攪拌 r生樹月日組合物’來作為實施例3 ίίΞΓϊΐ脂組合物:以上面的熱固性樹脂組合物來浸 盡mi : Pf /並且重量為48g/m2、厚度為51心、以及 睥η mVCm2.咖的玻璃纖維,而得到具有凝膠 以及樹脂組合物成份以重量計為則之聚 #合併上面的聚酯膠片s的兩層薄膜,將厚12#爪的電解銅 μ,放置在兩表面上,一銅箔在一表面而一鋼箔在另一表 面,在3〇mmHg或更小的真空下、溫度〗9(rc和壓力 2Gkgf 下、層合形成該合成物組合,.而得到雙面覆銅 的層製品。其後,以和比較例丨中相同的方法來處理該雙 ,覆j的層製品,而得到印刷插線板τ。將半導體晶片固 定在前面上,並將前面以引線接合,然後以樹脂完成密 封。將焊球連接到反面上,而得到半導體塑膠封裝U $評
89102305.ptd 第35頁 4543 1 2 五、發明說明(30) 估該半導體塑膠封裝U,結果顯示於表2。 第36頁 89102305.ptd
III 454312 五、發明說明(31) 表2 實施例 比較例 3 4 4 5 玻璃轉化溫度(°c ) 235 235 . 235 160 黏彈性 (xl01Q 達因/cm2) 2.0 1.9 - 1.2 壓力鍋處理後絕緣電PJ 1 ( Ω ) 正常狀態 4x10" - - 6x10" 處理後200小時 6xl012 - ' - 2xlOu 處理後500小時 6X10】1 - < 1x10s 處理後700小時 4xlO】0 - - - 處理後1000小時 2x10" - - - 防徙動性質(Ω ) 正常狀態 6xl013 2x10" 處理後200小時 5x10" 7xl09 處理後500小時 3x10" < lxlO8 處理後700小時 1x10" - 處理後1000小時 9xl〇'° - 阻燃度(UL94) - v - 0 " - 曲扭(250x250mm),印刷插線板(mm) J 0.6 0 0.5 P 9 S 15 半導體塑膠封裝(ym) K <150 P < 150 Q 850 U 1,020 1·_ΙΙ 89102305.ptd 第37頁 454312 五、發明說明(32) <測量方法> 1 )曲扭 •印刷插線板 放置在基板 將工作尺寸為2 5 Ο X 2 5 0mm的印刷插線板 上’並測量曲扭的最大值。 •半導體塑膠封裝 固定在16mm 將15mm X 1 5mm正方形大小的半導體晶片 X 1 6_正方形大小或2 5隨X 2 5mm正方形大小的印刷插線板 上,並測量該半導體塑膠封裝的曲扭最大值。 2 )阻燃度 以蝕刻來移去印刷插線板的鋼箔,並依據UL94測試該印 刷插線板》
89102305.ptd 第38頁 454312
圖1是顯示在實施例丨,製於焊墊中,個別具有直徑 〇. lmm的三個隱蔽介層洞,和焊球之接合狀態(junction state ) ° 圖2諸圖是顯示在實施例3中,印刷插線板.和半導體塑膠 封裝之各製造步驟: 圖2(1)是顯示具有一絕緣層之雙面覆銅。 . 圖2(2)是顯示在其二表面上具有通孔及電路之印刷插線 , 板。 圖2(3)是顯示置於印刷插線版之二表面上之聚酯膠片。 圖2(4)是顯示圖2(3)中聚酯膠片與印刷插線板組合之層 〇 合狀態。 圖2(5)是顯示具有用於接合墊與烊球墊之暴露部分的層 合組合。 圖2(6)是顯示一半導體塑膠封裝。 圖3是顯示使用實施例4的印刷插線板之半導體邀膠封 裴。 立件編號說明 a 鋼塾 b 隱蔽介層洞
c 烊球 V J d 熱固性樹脂層 __ e 焊球墊 f 鍛銅 g 電鍍絕緣塗料
89102305.ptc 第39頁 修正頁 4543 12
89102305.ptc 第39-1 頁 修JE頁

Claims (1)

  1. 4543 12
    六、申請專利範圍 > 1. 一種半導體塑膠封裝之印刷插線板,其印刷插線板, 係具有叫厚度〇. 2厕或更小的絕緣層所形成的雙面覆鋼’ 層製品,並具有銅箔在其兩表面上,一銅箔在—表面3而:一 銅箔在另外一表面,其中雙面覆铜的層製品、 伎主I > 另上方的銅 V白表面以及下方的銅箔表面’該上方的鋼箔表面有—引線 接合或是倒裝片接合的終端、將半導體晶片的終端連接到 該基板上’和有一銅墊、其位置在該銅墊可以電路連接到 該引線接合或是倒裝片接合的終端、並且可以連接到在不 方的鋼表面所形成的隱蔽介層洞,該下方的鋼箔表面有一 焊球固定墊、其位置符合於該銅墊,碎坪氣固寒摯本身革 虞.氣,调障蔽.介ϋ.. ’並且以導電材料連接到該銅塾的 反面之焊球固定塾、為了要固定、用熔解的焊球電路連接 到導電材料、並充填到隱蔽介層洞。 如申請專利範圍第1項之印刷插線板,其中,半導體 塑膠封裝之印刷插線板’為晶片級封裝之印刷插線板β 3.如申請專利範圍第1項之印刷插線板,其中,雙面覆 鋼的層製品之絕緣層,係由塗有包含多官能性氰酸醋和該 III氣瑪聚氣為息要成份之熱固性樹脂組合物的薄膜, 或是這類薄膜的多層板,所形成。 _ 4.如申請專利範圍第1項之印刷插線板,其中,雙面覆 ,的層製品之絕緣層、或是經由層合形成聚酯膠片薄膜所 传到的多層板,是以一種包含多官能性氰酸酯和該氰酸酯 的預聚物為主要成份之熱固性樹脂組合物、來浸潰一強固 一 g # ΐ!4 ’並具乾燥此被浸潰的強固基體材料,來得到
    454312 、申請專利範圍 的。 ’如申請專利範圍第4項之印刷插線板,其中,強固基 ,料’友轰教農惠屬農痕敗或是織造敷。 ^如申請專利範圍第1項之印刷插線板,其中,隱蔽介 同’為一種以二氧化碳雷射來輻射處理銅箔的表面、來 =成金屬氧化層’或者,將您點為9 Q〇°C或更高以及鍵 T一 、由金屬化合物粉末或碳粉之塗層組 ^ 所形成的輔助材料、以水溶性樹脂、放置在將被以二 _化碳雷射來輻射的銅箔上,然後以二氧化破氣體雷射來 幸虽射該鋼箔,所製得的隱蔽介層洞。 人7·如申請專利範圍第6項之印刷插線板,其中,金屬化 合物粉末’為至少一個從金屬氧化物、金屬非氧化物、金 屬、金屬合金和玻璃的族群中選擇的粉末。 /8.、一種半導體塑膠封裝之印刷插線板,其印刷插線板之 形成:是提供了一個以銅箔形成的覆銅層製品、和一個以 熱固性樹脂組合物來浸潰、1 5 0 // m到4 0 # m厚的玻璃纖維 之基體材料’一銅箔在該基板的一表面而一銅箔在該基板 的另外一表面’排列了至少一個半導體晶片接合終端、一 個焊球連接墊、一個連接接合終端和該墊的銅箔電路、以 及在該覆銅層製品中的通孔導電材料、來形成一個電路 板,然後在全部的正反表面上、堆積了玻璃纖雒之基體 材料/熱固性樹脂的聚酯膠片薄膜’在加壓和加熱下層合 形成該合成物組合,然後再移開在該接合終端的至少部份 表面、和該焊球連接墊的至少部份表面上之玻璃纖維和熱
    89102305.ptd 第41頁 454312 申請專利範圍 固性樹脂組合物形成之基體 9.如申請專利範圍第8印/露出電路。 薄的球狀柵極陣列型半導體之塑= 1 0 ·如申請專利範圍第8 、 維,為至少-個厚度為50 =印刷插線板,其中’玻璃纖 α Ά ^ ^ ^ ^ ^ ^ 為50 士10 、重量為35 到 60g/m2、 Λ為5到25。〜._的織物。 2 ^ ^ °卩伤表面、和該焊球連接墊的至少部份表 面十璃纖維和熱固性樹脂組合:體材料,以 喷砂法來移去,來露出電路。物开/成之暴骽 12.如申請專利範圍第8項之立 熱固性 樹脂組合物,為& j " '、 & #聚物 A必I Ρ μ舭 :|1氰酸酯和該氰酸酯的預 為乂要成如的熱固性樹脂組合物。 i 3.如申請專利範圍第8項之其 覆銅層 料。 〇物包含以重量計10到80 %的絕緣無 益:填如料申請圍第13項之印刷插線板,其中,絕緣 無機填枓,為氫氧化㉝或氫氧化鎂。
TW089102305A 1999-02-15 2000-02-11 Printed wiring board for semiconductor plastic package TW454312B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11036365A JP2000236041A (ja) 1999-02-15 1999-02-15 ハンダボール密着性に優れたチップスケールパッケージ用プリント配線板
JP11089782A JP2000286362A (ja) 1999-03-30 1999-03-30 極薄bgaタイプ半導体プラスチックパッケージ用プリント配線板

Publications (1)

Publication Number Publication Date
TW454312B true TW454312B (en) 2001-09-11

Family

ID=26375409

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089102305A TW454312B (en) 1999-02-15 2000-02-11 Printed wiring board for semiconductor plastic package

Country Status (5)

Country Link
US (2) US6362436B1 (zh)
EP (1) EP1030366B1 (zh)
KR (1) KR100630482B1 (zh)
DE (1) DE60023202T2 (zh)
TW (1) TW454312B (zh)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000015015A1 (fr) * 1998-09-03 2000-03-16 Ibiden Co., Ltd. Carte imprimee multicouches et son procede de fabrication
JP4348785B2 (ja) * 1999-07-29 2009-10-21 三菱瓦斯化学株式会社 高弾性率ガラス布基材熱硬化性樹脂銅張積層板
JP3258308B2 (ja) * 2000-02-03 2002-02-18 株式会社日鉱マテリアルズ レーザー穴開け性に優れた銅箔及びその製造方法
JP3414696B2 (ja) * 2000-05-12 2003-06-09 日本電気株式会社 半導体装置のキャリア基板の電極構造
JP4075306B2 (ja) * 2000-12-19 2008-04-16 日立電線株式会社 配線基板、lga型半導体装置、及び配線基板の製造方法
KR100716866B1 (ko) * 2000-12-27 2007-05-09 앰코 테크놀로지 코리아 주식회사 반도체패키지의 제조 방법
KR20020065705A (ko) * 2001-02-07 2002-08-14 삼성전자 주식회사 테이프 배선 기판과 그 제조 방법 및 그를 이용한 반도체칩 패키지
US20020197465A1 (en) * 2001-04-24 2002-12-26 Butner Steven Carl Damage tolerant CMC using sol-gel martix slurry
JP3461172B2 (ja) * 2001-07-05 2003-10-27 日東電工株式会社 多層配線回路基板の製造方法
US7356916B2 (en) * 2001-07-18 2008-04-15 Matsushita Electric Industrial Co., Ltd. Circuit-formed substrate and method of manufacturing circuit-formed substrate
JP2003046034A (ja) * 2001-07-31 2003-02-14 Nec Kagobutsu Device Kk 樹脂封止型半導体装置
US6657134B2 (en) * 2001-11-30 2003-12-02 Honeywell International Inc. Stacked ball grid array
US6866919B2 (en) * 2002-02-21 2005-03-15 Mitsubishi Gas Chemical Company, Inc. Heat-resistant film base-material-inserted B-stage resin composition sheet for lamination and use thereof
TW561797B (en) * 2002-03-27 2003-11-11 United Test Ct Inc Circuit board free of photo-sensitive material and fabrication method of the same
TW564530B (en) * 2002-07-03 2003-12-01 United Test Ct Inc Circuit board for flip-chip semiconductor package and fabrication method thereof
SG114561A1 (en) * 2002-08-02 2005-09-28 Micron Technology Inc Integrated circuit and method of fabricating an integrated circuit that includes a frame carrier interposer
JP2004103849A (ja) * 2002-09-10 2004-04-02 Fuji Xerox Co Ltd 電子部品実装基板及び電子部品交換方法
US6650022B1 (en) * 2002-09-11 2003-11-18 Motorola, Inc. Semiconductor device exhibiting enhanced pattern recognition when illuminated in a machine vision system
US7015590B2 (en) 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
EP1636842B1 (en) 2003-06-03 2011-08-17 Casio Computer Co., Ltd. Stackable semiconductor device and method of manufacturing the same
TWI278048B (en) * 2003-11-10 2007-04-01 Casio Computer Co Ltd Semiconductor device and its manufacturing method
JP3925809B2 (ja) * 2004-03-31 2007-06-06 カシオ計算機株式会社 半導体装置およびその製造方法
DE102004029584A1 (de) * 2004-06-18 2006-01-12 Infineon Technologies Ag Anordnung zur Erhöhung der Zuverlässigkeit von substratbasierten BGA-Packages
US20050287714A1 (en) * 2004-06-29 2005-12-29 Michael Walk Enhancing epoxy strength using kaolin filler
US20060019110A1 (en) * 2004-06-30 2006-01-26 Sumitomo Chemical Company, Limited Films
US8487194B2 (en) * 2004-08-05 2013-07-16 Imbera Electronics Oy Circuit board including an embedded component
US20060097400A1 (en) * 2004-11-03 2006-05-11 Texas Instruments Incorporated Substrate via pad structure providing reliable connectivity in array package devices
JP2006210480A (ja) * 2005-01-26 2006-08-10 Nec Electronics Corp 電子回路基板
KR100597995B1 (ko) 2005-01-27 2006-07-10 주식회사 네패스 반도체 패키지용 범프 및 제조 방법, 이를 이용한 반도체패키지
US20060211167A1 (en) * 2005-03-18 2006-09-21 International Business Machines Corporation Methods and systems for improving microelectronic i/o current capabilities
KR100664500B1 (ko) * 2005-08-09 2007-01-04 삼성전자주식회사 돌기부를 갖는 메탈 랜드를 구비하는 인쇄회로기판 및 그의제조방법
KR100699874B1 (ko) * 2005-11-08 2007-03-28 삼성전자주식회사 삽입형 연결부를 갖는 비. 지. 에이 패키지 그 제조방법 및이를 포함하는 보드 구조
JP4929784B2 (ja) * 2006-03-27 2012-05-09 富士通株式会社 多層配線基板、半導体装置およびソルダレジスト
KR100771873B1 (ko) * 2006-06-19 2007-11-01 삼성전자주식회사 반도체 패키지 및 그 실장방법
SG138501A1 (en) * 2006-07-05 2008-01-28 Micron Technology Inc Lead frames, microelectronic devices with lead frames, and methods for manufacturing lead frames and microelectronic devices with lead frames
CN101611490B (zh) * 2007-02-16 2011-07-27 住友电木株式会社 电路板的制造方法、半导体制造装置、电路板和半导体器件
US7709744B2 (en) * 2007-03-30 2010-05-04 Intel Corporation Gas venting component mounting pad
KR100850243B1 (ko) * 2007-07-26 2008-08-04 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR100870840B1 (ko) * 2007-10-04 2008-11-27 주식회사 고려반도체시스템 범프 패턴에 따른 홈이 형성된 범프 전사용 소자의 제조 방법.
JP2009182004A (ja) * 2008-01-29 2009-08-13 Elpida Memory Inc 半導体装置
US9208937B2 (en) * 2009-02-27 2015-12-08 Cyntec Co., Ltd. Choke having a core with a pillar having a non-circular and non-rectangular cross section
JP5487010B2 (ja) * 2010-05-27 2014-05-07 日本発條株式会社 回路基板用積層板及び金属ベース回路基板
CN101873763B (zh) * 2010-06-24 2012-12-26 海洋王照明科技股份有限公司 一种印刷电路板
US8642384B2 (en) 2012-03-09 2014-02-04 Stats Chippac, Ltd. Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability
US9659844B2 (en) * 2015-08-31 2017-05-23 Texas Instruments Incorporated Semiconductor die substrate with integral heat sink
US10818621B2 (en) 2016-03-25 2020-10-27 Samsung Electronics Co., Ltd. Fan-out semiconductor package
JP6610497B2 (ja) * 2016-10-14 2019-11-27 オムロン株式会社 電子装置およびその製造方法
EP3740460A4 (en) * 2018-01-16 2021-01-20 Central Glass Co., Ltd. COATING REMOVAL FOR ELECTRICAL CONNECTION ON A VEHICLE WINDOW
US10381322B1 (en) 2018-04-23 2019-08-13 Sandisk Technologies Llc Three-dimensional memory device containing self-aligned interlocking bonded structure and method of making the same
JP7261545B2 (ja) * 2018-07-03 2023-04-20 新光電気工業株式会社 配線基板、半導体パッケージ及び配線基板の製造方法
US10879260B2 (en) 2019-02-28 2020-12-29 Sandisk Technologies Llc Bonded assembly of a support die and plural memory dies containing laterally shifted vertical interconnections and methods for making the same
US11910531B2 (en) 2020-03-13 2024-02-20 Ascensia Diabetes Care Holdings Ag Flexible printed circuit board having a battery mounted thereto

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6097089A (en) * 1998-01-28 2000-08-01 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package
US5207585A (en) * 1990-10-31 1993-05-04 International Business Machines Corporation Thin interface pellicle for dense arrays of electrical interconnects
WO1992020097A1 (en) * 1991-04-26 1992-11-12 Citizen Watch Co., Ltd. Semiconductor device and manufacturing method therefor
US5402314A (en) * 1992-02-10 1995-03-28 Sony Corporation Printed circuit board having through-hole stopped with photo-curable solder resist
US5313365A (en) * 1992-06-30 1994-05-17 Motorola, Inc. Encapsulated electronic package
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device
US5535101A (en) * 1992-11-03 1996-07-09 Motorola, Inc. Leadless integrated circuit package
US5291062A (en) * 1993-03-01 1994-03-01 Motorola, Inc. Area array semiconductor device having a lid with functional contacts
TW368745B (en) * 1994-08-15 1999-09-01 Citizen Watch Co Ltd Semiconductor device with IC chip highly secured
US5798909A (en) * 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips
JP3287181B2 (ja) * 1995-08-15 2002-05-27 ソニー株式会社 多層配線の接続構造
JP3123638B2 (ja) * 1995-09-25 2001-01-15 株式会社三井ハイテック 半導体装置
JP3432982B2 (ja) * 1995-12-13 2003-08-04 沖電気工業株式会社 表面実装型半導体装置の製造方法
JP3437369B2 (ja) * 1996-03-19 2003-08-18 松下電器産業株式会社 チップキャリアおよびこれを用いた半導体装置
US5879787A (en) * 1996-11-08 1999-03-09 W. L. Gore & Associates, Inc. Method and apparatus for improving wireability in chip modules
JP2975979B2 (ja) * 1996-12-30 1999-11-10 アナムインダストリアル株式会社 ボールグリッドアレイ半導体パッケージ用可撓性回路基板
JP2982729B2 (ja) * 1997-01-16 1999-11-29 日本電気株式会社 半導体装置
JP2891254B2 (ja) * 1997-02-18 1999-05-17 日立エーアイシー株式会社 面付実装用電子部品
US5808873A (en) * 1997-05-30 1998-09-15 Motorola, Inc. Electronic component assembly having an encapsulation material and method of forming the same
JPH11186294A (ja) * 1997-10-14 1999-07-09 Sumitomo Metal Smi Electron Devices Inc 半導体パッケージ及びその製造方法
CN1971899B (zh) * 1997-10-17 2010-05-12 揖斐电株式会社 封装基板
JPH11284006A (ja) * 1998-03-31 1999-10-15 Fujitsu Ltd 半導体装置
US6157085A (en) * 1998-04-07 2000-12-05 Citizen Watch Co., Ltd. Semiconductor device for preventing exfoliation from occurring between a semiconductor chip and a resin substrate
JP4075178B2 (ja) * 1998-12-14 2008-04-16 三菱瓦斯化学株式会社 信頼性に優れたブラインドビア孔を有するプリント配線板用銅張板の製造方法
US6175152B1 (en) * 1998-06-25 2001-01-16 Citizen Watch Co., Ltd. Semiconductor device
US8035214B1 (en) * 1998-12-16 2011-10-11 Ibiden Co., Ltd. Conductive connecting pin for package substance

Also Published As

Publication number Publication date
EP1030366A3 (en) 2003-08-06
US6479760B2 (en) 2002-11-12
US6362436B1 (en) 2002-03-26
KR100630482B1 (ko) 2006-10-02
EP1030366A2 (en) 2000-08-23
DE60023202D1 (de) 2006-03-02
EP1030366B1 (en) 2005-10-19
KR20000058035A (ko) 2000-09-25
DE60023202T2 (de) 2006-07-20
US20020039644A1 (en) 2002-04-04

Similar Documents

Publication Publication Date Title
TW454312B (en) Printed wiring board for semiconductor plastic package
US6350952B1 (en) Semiconductor package including heat diffusion portion
KR101482299B1 (ko) 수지 조성물, 수지 시트, 프리프레그, 적층판, 다층 프린트 배선판 및 반도체 장치
JP5353241B2 (ja) 多層プリント配線板および半導体装置
TWI405523B (zh) 積層體、基板之製造方法、基板以及半導體裝置
US6396143B1 (en) Ball grid array type printed wiring board having exellent heat diffusibility and printed wiring board
TW200915955A (en) Multiple layer wiring circuit board and semiconductor device
EP0926729A2 (en) Semiconductor plastic package and process for the production thereof
KR19980703607A (ko) 접착제, 접착 필름 및 접착제-부착 금속박
TW201731948A (zh) 樹脂組成物
JP2010174242A (ja) ビフェニルアラルキル型シアン酸エステル樹脂、並びにビフェニルアラルキル型シアン酸エステル樹脂を含む樹脂組成物、及び、当該樹脂組成物を用いてなるプリプレグ、積層板、樹脂シート、多層プリント配線板、並びに半導体装置
TW200929403A (en) Method of manufacturing semiconductor package and semiconductor plastic package using the same
JP5130698B2 (ja) 多層プリント配線板用絶縁樹脂組成物、基材付き絶縁シート、多層プリント配線板及び半導体装置
TW200922396A (en) Insulating resin composition for multilayer printed wiring board, insulating resin sheet with substrate, multilayer printed wiring board and semiconductor device
JPH1117346A (ja) 多層配線板
JP2012041386A (ja) 回路基板用熱硬化性樹脂組成物
JP5053593B2 (ja) スルーホール用充填剤及び多層配線基板
JP2010245704A (ja) 弾性表面波素子用基板および弾性表面波装置
JPH1140950A (ja) 多層配線板
JP3806593B2 (ja) ビルドアップ用絶縁材料およびビルドアップ多層プリント配線基板
JP2000332393A (ja) 厚さ方向導電シート
JPH11176973A (ja) 半導体プラスチックパッケージ
JP3985342B2 (ja) 半導体プラスチックパッケージ
CN113201294A (zh) 高导热胶膜及其制备方法
JP4481733B2 (ja) 多層配線基板用導電性ペースト組成物

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees