TW434755B - Method for making semiconductors - Google Patents

Method for making semiconductors Download PDF

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Publication number
TW434755B
TW434755B TW87118397A TW87118397A TW434755B TW 434755 B TW434755 B TW 434755B TW 87118397 A TW87118397 A TW 87118397A TW 87118397 A TW87118397 A TW 87118397A TW 434755 B TW434755 B TW 434755B
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TW
Taiwan
Prior art keywords
resin
semiconductor device
island
semiconductor
common substrate
Prior art date
Application number
TW87118397A
Other languages
English (en)
Inventor
Haruo Hyodo
Takayuki Tani
Takao Shibuya
Original Assignee
Sanyo Electric Co
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Publication date
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Publication of TW434755B publication Critical patent/TW434755B/zh

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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
    • Y10T29/49172—Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

五、發明說明（1) [發明所屬技術領域] 本發明關於一種半導體襞置，尤其是關於可使安裝面 積縮小，並提高安裝效率之半導體裝置製造方法。 [習用技術] 習用1C，分立（discrete)元件等半導體裝置係使用如 第6圖（A)所示之聲封技術。1為矽基板，2為用以固定矽半 導體晶；5 }之島（1 s land) ’ 3為導線端子，8為鍵合線^ (bondi ng wi re) ’ 9為密封用樹脂。 舉例來說，形成有NPN型電晶體元件之半導體晶片}， 係藉焊接材料固定在島2上，並與半導體晶片1週邊所配置 導線端子3及電晶體元件之基板、射極、.分別以連接線4電 氣連接。島2將成為集極。 半導體晶片1經安裝於島上後，再以環氧樹脂等熱硬 化型樹脂4’以傳遞模塑法將半導體晶片1及導線端子3之 一部分完全覆蓋保護’而_属供三端子結構之半導體裝置。 導出樹脂5之外部之專線端子3谛折成z字型。 上述半導體裝置之製造步驟中，島2及導線端子3係以 由銅材料’或鐵材料所成之帶鋼（h〇〇p)狀或窄長詩箋狀導 線框架之狀態供給。該導線框架上，例如，形成有2〇個份 半導體裝置之島2及導線端子3。 其次’參照第6圖（B ) ’以上模7及下模8構成分別符 合半導體裝置外形形狀之空間，即空腔（cavity ，在空 腔9内部設置經施予晶片黏合（die bond)導線鍵合（wire bond)之導線框架。於此狀態下’將樹脂注入空腔9内，即 4347Sg 五、發明說明（2) 可施行傳遞模塑。然後，將密封樹脂後的前述導線框架 由導線部份切斷’使半導體裝置個別元件分離。 [本發明欲解決之問題] (第1個問題）
Jr'J a
裝（P 後之半導體裝置，通 基板上，並與其他同 連接，構成所希望之 5外之半導體裝置，其 展面積，故有安裝面 經施予模塑樹 氧樹脂基板等的印 板上的其他元件電 導線端子3引出樹脂 間之距離1 0會佔去 (第2個問題） 傳遞模塑技術♦ 按每一欲製造的半 在模表面上設置通駱 滿空腔及供注入樹g 通常使用於密封技柙 行利用，致殘留於4 樹脂，則勢必不再 別需要小型化封 物處分的樹脂量反销 利用效率不良之缺點 [解決問題之手段] 本發明係針對 在具有多數個元件, 步驟；以共同樹脂& 在由上下模所形成之 體裝置各自設置空腔 以供注入樹脂之用》 的通路之狀態下令樹 之環氧樹脂係屬熱硬 注入樹脂的通路等之 做製品使用而須作廢 ackage)之製造來說 比成為半導體製品樹 述習用技術之缺點而 載部之共同基板上搭 蓋全部之步驟；把共 T裝設於玻璃環 時裝設在印刷基 電路。此時，將 導線端子3兩端 積大之缺點。 空腔内惟以往係 ，並按每一空腔 密封係以樹脂填 脂硬化而完成。 化性’不可能再 狀態下所硬化之 。因此，對於特 成為前述廢棄 脂之量更多，有 創作，包括有： 載半導體晶片之 同樹脂層上部加
43479S 五、發明說明（3) :成：坦面之步驟；以及按每一元件搭載部 、 板一起切斷前述樹脂層之步驟。 共同基 [發明實施形態] 以下詳細說明本發明之製造方法。 第1步驟：第1圖 :先’準備共同基板30，施行半導體晶片之 連接。表示第1形態之金屬製導線框。^圖(片黏合 八同基板30之平面圖，第i圖⑶）為第i囷（九）*ΑΑ剖）為 本發明所使用之共同基板30，像將供搭載半圖》 之多數個元件搭載部31、31Α…以複數個重複方式晶片 列。行方向（或於其中一方向）所成，該多數個元件置於 31係以包圍該等之方式所配置之框體部32保持之。 栽部 元件搭載部31至少具備固定半導體晶片之島33， ，與外部連接用電極之複數個導線端子34。此時 及做 定之島33，則有用以連接鄰接於其隔壁的島33Α之導於特 子34，與該島33相對應而構成1個元件搭載部3丨。島⑸$ 導線端子34連結部份近旁之導線端子34係形成有將部份 寬加工成窄小之凹部36 β如此將元件搭載部31在列行方 向複數配置’便可在1個窄長詩箋狀共同基板3〇上配置， 例如100個元件搭載部31。圖中di至μ表示預定在後續步 驟切斷之切斷線，該切斷線所包圍區域即元件搭載部31。 上述共同基板30，係例如準備由厚度约〇.4inm之鋼系 金屬材料所形成帶狀或矩形狀導線框架用金屬薄 >;，而以 往下挖除0·2 mm左右之方式將此導線框架用金屬薄片加以
五、發明說明（4) :1::痘n面側未受到蝕刻之部位定義為裏板5〇。也 可以另外準備1枚片狀材料作為裏板5〇，而與開口成與第i 圖（A)所示同樣圖案的導線框架相貼合而形成亦可行β 其次，施行晶片黏合步驟及導線連接步驟。在各島 33、33Α之一主面上塗佈Ag糊斧（paste)，焊錫等導電糊 膏’介著該導電糊膏’在各島33、33A上固定半導體晶片 39 »然後，再以導線40將形成在半導體晶片“之表面之 焊接區（bonding pad)，與對應於此之導線端子34做導線 連接。導線40為例如直徑20私之金線。於此，導線4〇係用 以將固定在各島33上之半導體晶片39之表面電極，與鄰近 的其他島33A所伸出之導線端子34相連接。 固定半導想晶片39之島33背面，可用做此種半導體晶 片39之外部連接用電極。將島33背面做為連接用端子之一 而使用之形態’適合於半導體晶片39,例如電晶體，功率 (poffer)MOSFET等，電流路經為垂直方向之半導體裝置元 件。 第2步驟：第2圈（A)(B) 其次，施行全體之樹脂模塑》其係在作業台上欐放已 完成晶片黏合與導線連接之共同基板3〇，而由基板30上方 以分配器（dispenser)51滴下（potting)預定量之液體樹脂 52。樹脂52使用例如CV576AN (松下電工製造）所滴下之 液艎樹脂具有表面張力’以被覆基板30全趙之方式供給 時’則其表面會構成第2 ®(B)所示弩曲面。樹脂52並非將 各半導想晶片39......以個別封裝’而係將半導體晶片39全
A:\310188.ptc 第7頁 2000.10. 27. 007 A 年lD月？％I錢正/更元/¾充 修正 _ g 案號8Ή18397 打年⑺月彡0日 五、發明說明（5) 部共同瑗蓋形成。另外，如第2圖（C)所示，也可採取先在 共同基板30之框艘部32，形成高數mm，寬數㈣之環狀堰堤 (dam)，而可以填滿由該堰堤所包圍區域之方式填充液狀 樹脂52之方法》 如上所述，將半導體晶片39密封後，以100至200度， 做數小時熱處理（固化）使樹脂52硬化β 第3步騨：第2圖（D) 其次，將樹脂52f曲表面切削形成平坦面《使用切割 裝置以高速旋轉之切割刀片（bi ad e)54，略為切割樹脂52 之表面’使所有樹脂52表面距自共同基板30之高度齊平。 平坦面，至少擴大至位於最外側的半導體晶片39之端部， 俾把半導體晶片39分離成個別半導體裝置時，也能夠構成 經予規格化的封裝大小應具備之樹脂外形。前述切割刀片 備有各種不同之板厚，可視所使用之板厚而反復複數次， 使全雜形成為平坦面β而且，切割刀片以較第4步麻之切 斯程序所使用者稍厚為佳β另外，除使用切割刀片外，也 可藉砂輪的磨削加工等方法形成平坦面。 第4步驟：第2圃（Ε) -其次，將各元件搭載部31切斷，分離出元件Α、元件 Β元件C β在分離之前，如是第1圖所示導線框架， 則預先余除襄板5〇。褢板50如果是貼合式時，則剝下裏板 1° * ί=身一塊板狀材料經以半钱刻所形成者，則將相當 ϊίίΙϊΓ位予以削•，形成為由背面側也可看到島33 及導f端子34之結構之狀態。切削裏板50之方法與第3步 驊令一樣，可採用_刀片肖切到或其他例如姓刻法或砂
A:\310188.ptc 第8頁 2000.10.27. 008
然後，以能夠分離成包圍島33與連接於固定在該島上 的半導體晶片39的導線端子3 4之區域之方式循切斷線di至 D6予以切斷’藉此以形成按每一元件搭載部31所分割而成 的半導體裝置。切斷係使用切割裝置，而以切割裝置之高 速旋轉刀片同時切斷樹脂52與共同基板30。經予切斷的導 線端子34之另一方則以連接於島33之突起部而殘留下來。 經予切斷的導線端子34及突起部之切斷面，係與樹脂52之 切斷面形成同一平面’而露出於該同一平面》在切斷步 称，則在背面貼附發藍退火的薄鋼片（blue sheet;例 如’商品名：UV sheet ’Lintech公司製），而以切割刀片 能夠到達該薄鋼片之表面的切削深度進行切斷》此時，可 以在切割裝置側自動識別出預先形成在框體32之合對記號 37，以其為位置基準進行切割。而且，以切割刀片能夠通 過導線端子33之凹部36的方式進行切割。因此，切斷後之 導線端子33之前端部即成為前端光細之形狀，可加工成不 容易自樹脂52脫落之形狀。 切斷步驟以使用厚約20&ιη程度之切割刀片為佳。 第3圖為以上述製造方法所形成完成後之半導體裝 置，由背面側所看時之斜視圖。島33及導線端子34’包含 半導體晶片39及導線40在内，係由樹脂52模塑，形成大約 直方體之封裝形狀。樹脂41之外形尺寸，縱X橫X高為約 0.7 mm X 1.0 mm X 0.6 mm。在形成直方體封裝外形之6面中， 至少4個側面係由切斷榭脂52(參照第4步驟）之切斷面所構 成。沿該切斷面露出導線端子34之切斷面34a。島33含有
A:\3I0188.ptc 第9頁 2000.10.27.009 五、發明說明（7) 切斷導線端子34所殘餘之突起部33a。這些突起部之切斷 面也會露出。導線端子34及島33之背面側係露出於樹脂52 之表面。 然後’該半導體裝置即以焊接安裝於印刷基板。在自 動安裝機（chip mounter)則執行以真空吸附夾套（c〇net) 级住已切斷成個別之半導艎裝置，使所吸住半導體裝置設 置在基板上所希望位置之作業。此時，係以半導體裝置之 上側表面C與露出島之面相反之面）能夠與真空吸附夾套表 面接觸之方式吸住。因此，吸附側半導體裝置須維持規格 化尺寸及精確度《本發明由於具備可以將因灌注 (pott i ng)所彎曲之樹脂52表面加以平坦化之步驟（第3步 驟）’所以可維持供吸附的樹脂52表面之尺寸精確度，不 致損害自動安裝之作業性。 第4圖表示安裝於印刷基板上之狀態，係將露出於背 面之導線端子34與島33之突起部33a之位置對準於安裝基 板24上所形成元件連接用印刷配線25，而以焊錫26等連接 兩者而成。 以下說明本發明第2實施形態。上述實施形態係使用 金屬導線框架為支持基扳，而本實施形態則使用陶瓷或環 氧樹脂等絕緣性基板為支持基板。 第5囷（A)表示在預先準備妥的共同基板3 0表面，將半 導體晶片39做晶片黏合及導線連接之狀態平面圖。共同基 板3 0之表面形成有由鍍金所成之導電圖案。圖中D1至D 7表 示以切割裝置分離之切斷線。切斷線D1至D7所圍矩形區為
第10頁 4a4?i§ 五、發明說明（8) 元件搭載部3 1。 锻金圖案含有搭載半導體晶片39用的岛60及用以形成 連接導線40之二次連接區（second bond area)之導線部 61。元件搭載部31内之島部60與導線部61不連接，而於切 斷線D1至D7分離處則連接島部60及導線部61之間。另外， 在切斷線D1至D7之交叉處（相對於元件搭載部之4隅）形成 貫通共同基板30之貫通孔（through hole)62 ,連接於形成 在共同基板30背面，以後將成為表面電極之導電圖案。如 此’島部60及導線部61即分別與各背面側表面電極做電氣 連接。 經對這樣的共同電極30施予：藉灌注法將全部半導體 晶片39以樹脂52被覆之步驟；將樹脂52表面平坦化之步 驟；及按每一元件將樹脂52與共同基板同時切斷之步驟， 即得第5圖（B)所示半導體裝置。該圖中表示完成後之半導 體裝置剖面圖，相同部分均以相同符號標註並省略其說 明。此外’共同基板30表面之側島部6Q及導線部61，與共 同基板30背面側之表面電極63，係經過貫通孔相連接^表 面電極63為以锻金形成之導電圖案。對印刷基板上之安裝 方法，則與前述實施形態相同。 上述方法所製造之半導體裝置有以下優點β 本發明製造方法所製造半導體裝置，因為金屬製導線 端子不會突出封裝之外，所以可使安裝面積做成為與半導 趙裝置之封裝大小相同之大小。因此，有源部份（意指半 導體晶片39之晶片尺寸）相對於半導體裝置安裝面積之比
第11頁
4347SS 五、發明說明（9) 的安裝有效面積’與第6圖所示者相比可大幅增加，使電 子機器可以輕薄短小化。 與以傳遞模塑技術做個別封襞相比，浪費之樹脂較 少，可降低材料費。 由於採取以切割裝置之刀片切斷封裝外形之構成，可 提高封裝外形尺寸之精確度，使小型封裝得以良好精確度 生產。即意味著共同基板30使用導線框架時，可增大島33 之面積。換言之’相對於依傳遞模塑技術之金屬模與導線 框架之對準精確度高達正負50从左右之情形，依切割裝置 之切割刀片與導線框架之對準精確度則可抑小至正負 左右。對準精硪度可小，表示可以增大島33面積，此點也 能使可搭載半導體晶片39之晶片面積增大，同時使上述有 效安裝面積效率提高。
上述實施形態係就三端子型半導體裝置之情形加以說 明’但亦可適用於具備3個以上導線端子之裝置D 又’上述實施形態係在各島固定一個半導體晶片39。 但亦可在1島上固定，例如複數個電晶體，及將電晶體與 縱型功率MOSFET等其他元件複合固定。 、 此外’上述實施形態雖係在半導體晶片39形成電晶 體’但例如形成功率M〇SFET，IGBT，HBT等裝置之半導體 裝置，亦可應用於本發明自不待言β此外，如予以增加導 線端子之個數’則也可應用於B IP，MOS型等集體電路。 [本發明之效果;1 如上所述’本發明可得不使導線端子34突出封裝之半
第12頁 434755 五、發明說明（10) 導體裝置β從而可獲得能減少安裝半導體裝置時之無用空 間而適合高密度安裝之半導體裝置。 由於封裝外形係以切割刀片所切斷之切斷面構成，可 使島33及樹脂52端面之尺寸精確度提高。從而，可使島33 之面積增大’可收容半導體晶片39之晶片大小亦可增大。 與使用傳遞模塑技術個別封裝之方式相比，可減少浪 費之樹脂，降低材料費。 由於對經以灌注技術所被覆樹脂52之歪曲表面，施行 平坦化加工後，以仞割裝置將各半導體的裝置切離，因此 可維持封裝外形尺寸之精確度。因以，可製造適合自動安 裝之半導體裝置。 [附圖簡單說明] 第1圖為用以說明本發明製造方法之（Α)平面圖，（Β) 剖面圖。 第2圖為用以說明本發明製造方法之剖面圖。 第3圖為用以說明本發明製造方法之斜視圖。 第4圖為用以說明本發明製造方法之剖面圖。 第5圖為用以說明本發明第2實施形態之（Α)平面圖，（ Β)剖面圖。 第6圖為用以說明習用半導體裝置之圖。
第13頁

Claims (1)

  1. 4347 5 5 六、申請專利範圍 1. 一種半導體裝置之製造方孝，包括： 準備具有用以固定複數個半導體晶片的元件搭載 部之共同基板之步驟； 對前述各元件搭載部固定半導體晶片之步驟； 由前述共同基板上方供給樹脂，以連續樹脂層被 覆包含半導體晶片在内之複數個元件搭載部之步驟； 將前述連續樹脂層上面加工成平坦面之步驟，·以 ..旌速^續樹脂I，按每一元件搭載部，與前述 共同基皈一起切斷，使半導體裝置個別分離之步驟。 2. 如申請專利範圍第1項之半導體裝置之製造方法，其中 該共同基板為導線框架者。 3. 如申請專利範圍第1項之半導體裝置之製造方法，其中 該共同基板為絕緣基^板I。 如申請專利範圍第1項之半導體裝置之製造方法，其中 該加工為平坦面名r步驟係以切割刀>{切割者。 5.如申請專利範圍第1項之半導體裝置之製造方法，其中 該分離為個別半導體裝置之步驟係以切割刀片切割 者0
    第14頁
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