TW201947054A - 用於在圖案化基材的表面上選擇性形成材料的製程 - Google Patents

用於在圖案化基材的表面上選擇性形成材料的製程 Download PDF

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TW201947054A
TW201947054A TW108114884A TW108114884A TW201947054A TW 201947054 A TW201947054 A TW 201947054A TW 108114884 A TW108114884 A TW 108114884A TW 108114884 A TW108114884 A TW 108114884A TW 201947054 A TW201947054 A TW 201947054A
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passivation layer
deposition
reactant
dielectric
substrate
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TW108114884A
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TWI773897B (zh
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艾娃 多益斯
維爾傑米 波爾
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荷蘭商Ａｓｍ Ｉｐ控股公司
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
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    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Abstract

本發明提供用於在基材的相對於先前沉積於第二表面上的鈍化層的第一表面上選擇性沉積介電膜的方法和系統。該方法可包括至少一用於在該第一表面上沉積材料的循環沉積製程，同時移除該鈍化層，藉以防止該鈍化層上方的沉積。

Description

使用沉積與移除之選擇性層的形成
本發明通常有關半導體裝置製造的領域，更具體係，有關使用沉積和移除膜的選擇性形成層。
在半導體產業中，逐漸增加有關選擇性製程的需求。例如，在一表面上可能想要膜生長，但可能不想要在第二個不同的表面上膜生長。這兩個不同表面可包括不同材料，例如一金屬和一介電質。良好的選擇性製程可藉由避免更複雜的用於沉積材料的分離式圖案化（separate patterning）製程（諸如光刻遮罩（photolithographic masking）和圖案化）而減少製程步驟的次數，因而節省時間和金錢。
相關申請案之交叉參考
本專利申請案主張2018年5月2日申請的美國臨時申請案第62/666,039號的優先權，在此所有目的透過引用方式將其整個內容併入本說明書供參考。
在一態樣中，提供一種用於在圖案化基材的第一表面上選擇性形成介電材料的原子層沉積（Atomic Layer Deposition，ALD）製程之方法。該方法包括提供含有第一表面和第二表面的基材，其中該第二表面包含在其上的鈍化層。該方法更包括進行至少沉積循環，該沉積循環包括交替及依序使該基材接觸第一前驅物和含氧的第二反應物。該方法更包括該第二反應物與該第一前驅物起反應以在該第一表面上形成該介電材料，而且其中在每個沉積循環期間，該第二反應物使該鈍化層灰化。
在一些實施例中，該用於ALD製程的方法更包括該第一表面是介電質表面。在一些實施例中，該介電質表面包含氧化矽。在一些實施例中，該第一表面包含低k材料。在一些實施例中，該第二表面是金屬表面。在一些實施例中，該金屬表面包含Co、Cu或W之至少一者。在一些實施例中，該介電材料是氧化物。在一些實施例中，該氧化物是氧化矽。在一些實施例中，該氧化物是金屬氧化物。
在一些實施例中，該第一前驅物包含金屬前驅物、矽前驅物或其混合物。在一些實施例中，該第一前驅物是烷基胺基矽烷（alkylaminosilane）。
在一些實施例中，該鈍化層包含有機材料。在一些實施例中，先選擇性地將該鈍化層沉積在相對於該第一表面的該第二表面上，然後開始該第一沉積循環。在一些實施例中，沉積循環重複多次，以在該介電質表面上形成想要的厚度的氧化物膜。在一些實施例中，在每個沉積循環的開始和結束之間，選擇性沉積額外的鈍化層在該鈍化層上。
在一些實施例中，ALD製程是電漿輔助原子層沉積（Plasma Enhanced Atomic Layer Deposition，PEALD）製程。在某些實施例中，該至少一沉積循環是先從使該基材接觸所述第二反應物開始，然後接觸該第一前驅物。在一些實施例中，該至少一沉積循環更包括在每個循環中使該基材接觸至少一額外的反應物。在一些實施例中，該第二反應物更包含電漿。在一些實施例中，使該基材接觸該第二反應物更包括使用電漿活化該第二反應物。
在一些實施例中，選擇性地將該介電材料形成在相對於該鈍化層的該第一表面上。在一些實施例中，該介電材料形成在該鈍化層上，且藉由該鈍化層的灰化而從該鈍化層移除該介電材料，藉此選擇性地在該第一表面上形成該介電材料。
在另一態樣中，提供一種用於在圖案化基材的表面上選擇性形成材料的循環沉積製程。該方法包括提供含有第一表面和第二表面的基材，其中該第二表面包含在其上的鈍化層。該方法更包括至少一沉積循環，所述沉積循環包括交替及依序使該基材接觸第一前驅物和第二反應物。該第二反應物與該第一前驅物起反應，以在該第一表面上形成該材料，且在每個沉積循環期間，藉由該第二反應物蝕刻該鈍化層。
在一些實施例中，該製程包括原子層沉積（ALD）。在一些實施例中，該製程包括電漿輔助ALD（PEALD）。在一些實施例中，該第二反應物包含電漿活化物質。在一些實施例中，該第二反應物包含氧，該鈍化層包含有機層，且蝕刻包括灰化。在一些實施例中，該鈍化層包含聚合物。
在一些實施例中，先停止沉積，然後該鈍化層的蝕刻暴露該第二表面。在一些實施例中，該方法包括在停止沉積之後且在繼續沉積之前，在該第二表面上方進一步沉積額外的鈍化層。
在另一態樣中，提供一種用於在圖案化基材的第一介電質表面上選擇性形成氧化物材料的電漿輔助原子層沉積（PEALD）製程。該方法包括提供含有第一介電質表面和第二金屬表面的基材，其中該第二金屬表面包含在其上的有機鈍化層。該方法更包括進行至少一沉積循環，該沉積循環包括交替及依序使該基材接觸第一前驅物及含氧和電漿的第二反應物。該第二反應物與該第一前驅物起反應，以在該第一介電質表面上形成氧化物材料，且在每個沉積循環期間，該第二反應物使該有機鈍化層灰化。
熟習該項技藝者將明白，諸如金屬氧化物或氧化矽(例如，SiO)膜的介電膜例如在積體電路製造中具有廣泛應用。根據本發明的一些實施例，提供各種介電膜，特別是氧化物膜；前驅物；及用於沉積此類膜的方法。
在一些實施例中，藉由選擇性沉積製程使材料形成於基材的相對於第二表面的第一表面上。在一些實施例中，該材料是氧化物材料。在一些實施例中，在基材的相對於金屬表面上的鈍化層的介電質表面上，使用循環沉積製程以選擇性地形成介電膜。
例如，圖1A為示意說明在第一表面上沉積材料的選擇性沉積製程，同時減小在第二表面上方的鈍化層的厚度的流程圖100。在第一個繪示的方塊102中，提供具有第一表面和第二表面的基材，其中該第二表面包含在其上的鈍化層。在方塊104中，該基材接觸第一反應物，且在方塊106中，該基材接觸第二反應物。在一些實施例中，交替及依序執行方塊104和方塊106。在所示的判斷方塊108中，在形成足夠厚度的材料之前，方塊104和方塊106可使該基材重複暴露於該第一反應物和該第二反應物。在一些實施例中，形成足夠厚度的材料，因此不重複方塊104和方塊106。在一些實施例中，沒有形成足夠厚度的材料，因此重複方塊104和方塊106，且重複的方塊104和方塊106稱為循環沉積製程。在每個重複中，方塊104和方塊106不需採用相同順序，亦不需要相同地執行。在一些實施例中，連續執行方塊104和方塊106。在一些實施例中，藉由一或多個間歇性製程分開方塊104和方塊106。在一些實施例中，連續執行重複的方塊104和方塊106。在一些實施例中，藉由一或多個間歇性製程分開重複的方塊104和方塊106。在一些實施例中，間歇性製程可選自過量的反應物和副產物的移除（例如，真空及/或惰性氣體清除（purge））、選擇性沉積額外的鈍化層、額外的清潔蝕刻、先重複暴露相同反應物然後暴露另一反應物及/或在一些或所有循環中暴露於額外的反應物之至少一者。涉及過量反應物和副產物的移除有助於分開不同反應物的供應，以最小化氣相交互作用的風險及限制對表面反應的沉積反應。熟習該項技藝者將明白，可容忍殘餘氣體的一些交互作用，以最小化中間移除（例如，清除（purge））步驟的持續時間。避免反應物供應至反應空間的重疊通常足以減少氣相反應，而且經最佳化的流動路徑連同介入清除（intervening purge）可進一步最小化殘餘氣體交互作用。一旦形成想要厚度的材料，在方塊110中完成選擇性沉積製程，其中在第一表面上選擇性地獲得材料，且在所述第二表面上獲得具有減小厚度的鈍化層。反應物可為在沉積膜中留下一或多個元素的前驅物。在一些實施例中，一或多個反應物可用於化學還原、氧化或沉積材料的吸氣（getter）產物。
類似於圖1A，圖1B為示意說明在第一表面上選擇性沉積材料，同時減小鈍化層厚度的示例性流程圖200，然而圖1B包括在第二表面上選擇性地形成鈍化層。應瞭解，關於圖1A討論的任何相同或類似特徵或功能亦可應用於圖1B的相同或類似特徵或功能。在第一個繪示的方塊202中，鈍化層是選擇性地形成在基材的相對於第一表面的第二表面上。在方塊204中，使該基材接觸第一反應物，且在方塊206中，使該基材接觸第二反應物。在所示的判斷方塊208中，可形成足夠厚度的材料，因此如方塊212所示，使用減小厚度的鈍化層在該第一表面上選擇性地獲得材料。如果尚未形成足夠厚度的材料且如果該鈍化層不是在暴露於反應物而完全消耗的風險，判斷方塊210示意說明在方塊204和方塊206中，基材可重複及交替暴露於該第一反應物和該第二反應物。或者，如果該鈍化層存在暴露於反應物而被完全消耗的風險情況下，判斷方塊210示意說明可重複第一個繪示的方塊202，其中鈍化層先選擇性地形成在該基材相對於第一表面的第二表面上，然後在方塊204和方塊206中使基材暴露於該第一反應物和該第二反應物。
在一些實施例中，該循環沉積製程是原子層沉積（ALD）。在一些實施例中，循環沉積製程是循環化學氣相沉積（Chemical Vapor Deposition，CVD）。在一些實施例中，該鈍化層預先沉積在第二表面（例如，金屬表面）上。在一些實施例中，在循環沉積製程期間，部分地移除鈍化層。在ALD製程期間，例如，可在ALD階段（phase）期間緩慢移除該鈍化層，例如藉由蝕刻法。例如，對於有機（例如，聚合物）鈍化層，可在供應氧化劑的沉積階段期間完成蝕刻（例如，灰化），同時在介電質表面上沉積介電膜。在另一實例中，當在ALD製程中使該基材暴露於第二反應物期間，在介電質表面上沉積氧化物材料時，同時移除鈍化層。該鈍化層的緩慢蝕刻可防止在該鈍化層上和在金屬上沉積介電質。
在一些實施例中，ALD製程可為電漿輔助原子層沉積（PEALD）製程。在一些實施例中，提供電漿功率以從含氧的反應物產生更多的反應性物質。在一些實施例中，含氧的反應物包含O2 氣體，其間經歷電漿產生功率。在一些實施例中，電漿可從沉積腔室遠距產生，且電漿產物供應到沉積腔室。在一些遠距電漿實施例中，傳輸路徑最佳化中性氧（O）物質的傳輸，同時最小化離子傳輸至基材。在一些實施例中，電漿可在沉積腔室內原位（in situ ）產生。
在一些實施例中，該基材的該第一表面包含介電質表面。在一些實施例中，該基材的該介電質表面包含氧化矽（例如，SiO2 ）。在一些實施例中，該基材的該介電質表面包含低k材料。
在一些實施例中，該第二表面包含金屬表面。除非另有說明，否則如果表面在本說明書中稱為金屬表面，則其可為金屬表面（metal surface）或金屬性表面（metallic surface）。在一些實施例中，金屬表面或金屬性表面可包含金屬、金屬氧化物及/或其混合物。在一些實施例中，金屬表面或金屬性表面可包含表面氧化。在一些實施例中，金屬表面或金屬性表面之金屬材料或金屬性材料在存在或不存在表面氧化的情況下具有導電性。在一些實施例中，金屬表面或金屬性表面包含一或多種過渡金屬。在一些實施例中，金屬表面或金屬性表面包含Al、Cu、Co、Ni、W、Nb、Fe之一或多者。在一些實施例中，金屬表面或金屬性表面包含Co、Cu或W的至少一者。在一些實施例中，金屬表面或金屬性表面包含一或多個貴金屬，諸如Ru。在一些實施例中，金屬表面或金屬性表面包含導電金屬氧化物、氮化物、碳化物、硼化物或其組合。例如，金屬表面或金屬性表面可包含RuOx 、NbCx 、NbBx 、NiOx 、CoOx 、NbOx 和WNCx 之一或多者。在一些實施例中，該基材可包含金屬氮化物，包括但沒有限於TiN及/或TaN。在一些實施例中，該金屬表面可包含金屬碳化物，包括但沒有限於TiC及/或TaC。在一些實施例中，該金屬表面可包含一金屬硫屬化物（chalcogenide），包括但沒有限於MoS2 、Sb2 Te3 及/或GeTe。在一些實施例中，金屬表面是TiN表面。在一些實施例中，金屬表面是W表面。
選擇性
選擇性可如式子[(第一表面上的沉積)-(第二表面上的沉積)]/(第一表面上的沉積)計算出的百分比取得。沉積可以多種方式中之任一者加以測量。在一些實施例中，沉積可如沉積材料的測量厚度取得。在一些實施例中，沉積可如測量的沉積材料量取得。
在一些實施例中，選擇性大於約10%、大於約50%、大於約75%、大於約85%、大於約90%、大於約93%、大於約95%、大於約98%、大於約99%或甚至大於約99.5%。在本說明書描述的實施例中，所述選擇性可針對沉積的持續時間或厚度來改變。
在一些實施例中，諸如氧化物的介電質沉積僅發生在該第一介電質表面上，而不是發生在該第二金屬表面上方的鈍化層上。在一些實施例中，在該基材的相對於鈍化層的第一表面上的沉積是至少約80%選擇性，這對於一些特定應用可為足夠選擇性。在一些實施例中，在該基材的相對於鈍化層的第一表面上沉積是至少約50%選擇性，這對於一些特定應用可為足夠選擇性。在一些實施例中，在該基材的相對於鈍化層的第一表面上的沉積是至少約10%選擇性，此對於一些特定應用可為足夠選擇性。
在一些實施例中，可先選擇性地將該鈍化層形成在金屬表面上，然後選擇性地在介電質表面上沉積該介電材料。例如，在一些實施例中，鈍化層可毯式（blanket）沉積在圖案化基材上，而且藉由習知製程進行圖案化和蝕刻，以選擇性地留下該鈍化層，以避免後續沉積，諸如在金屬表面上方。在其他實施例中，可選擇性地將鈍化層沉積在金屬層上。鈍化層的選擇性沉積可例如如下的描述實現，而且如美國專利公開案第2017-0352533 A1號（專利申請案第15/170,769號）或美國專利公開案第2017-0352550 A1號（專利申請案第15/486,124號）中的描述，其每個專利案的全部揭露內容是整個併入本說明書供參考。
如前述，在金屬表面上方選擇性形成鈍化層不需要100%選擇性以實現100%選擇性。例如，鈍化層沉積可為部分選擇性，使得其在金屬表面上方形成的厚度較在該介電質表面上方的厚度厚。鈍化材料的隨後短暫蝕刻可持續一段時間以暴露介電質表面，同時留下覆蓋該金屬表面的一些鈍化層。
ALD製程
根據一些實施例，使用以氧為基礎的ALD製程使介電膜沉積在基材的第一表面上。在一些實施例中，沉積的介電膜可為例如氧化矽（例如，SiO2 ）或可使用PEALD製程生長的其他金屬氧化物。在一些實施例中，沉積的介電膜可包含SiO2 、TiO2 、ZrO2 、HfO2 、Nb2 O5 、Ta2 O5 、WO3 、NiO及其組合。鈍化層可覆蓋該基材的第二表面。在一些實施例中，該鈍化層是有機層。該有機鈍化層可為聚合物，諸如聚醯亞胺（polyimide）或聚醯胺（polyamide）。
在一些實施例中，使用以氧為基礎的ALD製程使氧化物材料膜沉積在基材的第一表面上。在一些實施例中，沉積的氧化物材料膜可為導電氧化物膜。例如，在一些實施例中，導電氧化物膜是氧化銦錫（Indium Tin Oxide，ITO）膜。在一些實施例中，沉積的氧化物材料膜可為介電膜，如本說明書的描述。
在一些實施例中，該鈍化層抑制在其的氧化物材料膜及/或介電膜沉積。然而，在一些實施例中，該鈍化層不抑制氧化物材料膜或介電膜的沉積，亦即，氧化物材料膜或介電膜化學物質在下面的介電質基材表面和該鈍化層之間可不具有選擇性。這是因為選擇條件以確保在ALD製程期間一些鈍化層的移除，如此底切（undercutting）及移除在該鈍化層上方的氧化物材料膜或介電膜的任何沉積。當該鈍化層是犧牲層時，在該循環沉積階段之一者期間緩慢移除（例如，蝕刻）鈍化層。例如，在ALD序列（sequence）中，有機（例如，聚合物）鈍化層可被ALD序列的氧化劑階段（oxidant phase）緩慢灰化，這防止氧化物材料膜或介電膜在該鈍化層上生長。在另一示例中，在ALD序列中，在ALD製程中將基材暴露於第二反應物期間移除鈍化層，這防止氧化物材料膜或介電膜在該鈍化層上生長。相對於在該鈍化層上的生長，氧化物材料膜或介電膜通常（非選擇性或使用低選擇性）沉積在介電質表面上。無論氧化物材料膜或介電材料是否正常或選擇性沉積在該介電質表面上，藉由ALD序列的氧化劑階段緩慢蝕刻（例如，灰化）犧牲鈍化層具有選擇性地形成氧化物材料膜或介電材料在相對於該鈍化層的介電基材上的最終效果。因此，使用圖1A或圖1B的製程可有效提高形成氧化物材料膜或介電膜的選擇性。
在一些實施例中，在執行氧化物材料膜或介電膜的沉積之前但在形成該鈍化層之後，可使用具有適當參數的電漿預處理來移除留在介電質表面上的任何鈍化層。在一些實施例中，不是從介電質表面上方移除任何鈍化材料的單獨製程，而是藉由ALD製程的初始階段（包括氧化階段）或藉由在啟動完整ALD製程之前僅進行ALD製程的氧化階段來移除留在介電質表面上的任何鈍化層，其中在完全灰化介電質上的較薄鈍化層之後，開始氧化物材料膜或介電膜沉積製程。因此，在該第一表面上選擇性沉積之前，ALD序列可從包含氧化劑的第二反應物開始，用於從該第一表面短時間蝕刻不想要的鈍化材料，而不從該第二表面移除所有鈍化材料。
在一些實施例中，ALD製程的氧化階段是PEALD序列中的電漿處理。在一些實施例中，電漿是以氧為基礎的。例如，電漿可採用O2 氣體或O2 和惰性氣體（諸如Ar）的混合物。在一些實施例中，電漿可採用含氧的氣體產生，或可另外包含激發的氧氣物質。在一些實施例中，ALD製程的氧化階段是非電漿氧化製程（例如，H2 O或O3 ）。
在一些實施例中，電漿（例如含氧電漿）可藉由施加從約10W至約2000W、從約50W至約1000W、從約100W至約500W、從約30W至100W或在一些實施例約100W的RF功率來產生。在一些實施例中，RF功率密度可從約0.02 W/cm2 至約2.0 W/cm2 或從約0.05 W/cm2 至約1.5 W/cm2 。RF功率可施加到在電漿接觸時間期間流動的反應物，其連續流過反應腔室，及/或流過遠距電漿產生器。因此，在一些實施例中，電漿是原位產生，而在其他實施例中，電漿是遠距產生。在一些實施例中，使用噴淋（showerhead）反應器且在基座（基材所位於的上方）和噴淋板之間原位產生電漿。在一些實施例中，基座和噴淋板之間的間隙是從約0.1cm至約20cm、從約0.5cm至約5cm或從約0.8cm至約3.0cm。
完全移除鈍化層前可在該介電質表面上形成該氧化物膜的厚度，取決於該鈍化層初始厚度、鈍化層的灰化速率和氧化物沉積製程的生長速率。例如，圖2呈現在灰化速率為~0.2 Å/循環、20nm犧牲聚醯亞胺層在金屬表面上及每循環生長（Growth Per Cycle，GPC）為1Å/循環的情況下，施加500個循環之以氧為基礎的PEALD製程可在介電質表面上沉積50 nm的SiO2 。圖2顯示氬氣以700 sccm供應、O2 以100 sccm供應、壓力保持在2 Torr、電漿功率設定為100W、基材溫度保持在100ºC，且每個氧化劑階段包括1秒O2 電漿和1秒清除（purge）的情況下所暴露於氧化劑階段時的聚醯亞胺灰化速率。PEALD將包括前述氧化劑階段交替供應矽前驅物與清除的一階段，其中矽前驅物係經選擇吸附在介電質或生長的氧化矽膜上，而且隨著氧化劑階段起反應以形成氧化矽。在其他實施例中，氧化劑階段可交替供應一或多個金屬前驅物階段和伴隨清除階段，其中選擇金屬前驅物以吸附在介電質表面或生長金屬氧化物膜，且隨著氧化劑階段起反應以形成想要的氧化物。
在一些實施例中，可調整犧牲鈍化層的蝕刻速率最佳化，使得在ALD製程期間的氧化物材料膜或介電膜的生長不會導致在鈍化層上的淨沉積（net deposition）。在一些實施例中，用於在鈍化層上沉積的孕育時間足夠長，使得在該介電質表面上沉積想要的氧化物層厚度。在一些實施例中，在金屬表面上方形成足夠厚的鈍化層，使得可使用ALD製程在該介電質表面上方沉積足夠厚的氧化物膜，而不會進一步沉積另一鈍化膜層，即，沒有完全消耗初始鈍化層。
在一些實施例中，選擇性鈍化層沉積和該選擇性ALD製程是採用迭代方式（iterative manner）執行，例如，諸如使用圖1B所示的製程。所述迭代製程可允許在執行ALD製程之後添補鈍化層的厚度，因此允許執行隨後的ALD製程。例如，在沉積的氧化物以較快於藉由底切將其移除而開始形成在該鈍化層上之前，如果該鈍化層在100個循環中被灰化或如果鈍化層上的孕育時間是100個循環，可執行90個循環的第一ALD製程以選擇性地在該介電質表面上沉積氧化物，可在先前鈍化層上方執行一後續鈍化層的沉積，及可執行第二90個循環的ALD製程。在一些實施例中，所述迭代製程可視需要來重複多次，以在該介電質表面上獲得想要的氧化物層厚度。熟習該項技藝者將明白，必要的迭代製程次數將隨著各種因素而變化，諸如，例如想要的沉積氧化物厚度、鈍化層厚度及鈍化層的灰化率或孕育時間。
在一些實施例中，所述PEALD沉積可基本上如前述實現。在其他實施例中，基材交替及依序接觸含有包含在沉積材料（諸如金屬或矽）中元素的第一反應物及含氧的第二反應物；及第二電漿反應物。在一些實施例中，該第二電漿反應物不包含氧物質。在一些實施例中，除該第二反應物之外不使用含氧物質的反應物。所述電漿和前驅物（即所述第一反應物和第二反應物）可藉由移除製程（例如清除）分離的脈衝中提供，其中移除在反應空間中的過量反應物和反應副產物（若存在）。在一些實施例中，PEALD沉積製程是從電漿脈衝開始，然後是前驅物，且反應序列或沉積循環可重複想要的次數(A)：
A x (電漿脈衝/清除/前驅物/清除)
在一些實施例中，所述沉積循環是從非電漿前驅物開始，然後是電漿脈衝。
根據一些實施例，使用的PEALD製程可為任何適當的以氧為基礎的電漿處理。在一些實施例中，沉積的介電膜是氧化物膜。在一些實施例中，沉積的介電膜是金屬氧化物膜。在一些實施例中，沉積的介電膜可選自由SiO2 、TiO2 、ZrO2 、HfO2 、Nb2 O5 、Ta2 O5 、WO3 和NiO所組成的群組。在一些實施例中，沉積的介電膜是氧化矽。在一些實施例中，氧化物前驅物是用於沉積氧化矽膜的烷基胺基矽烷。
在一些實施例中，藉由以氧為基礎的PEALD製程，氧化物膜選擇性地形成在相對於該基材的第二不同金屬表面或金屬性表面的該基材的第一介電質表面上。例如，氧化矽可藉由以氧為基礎的PEALD製程而選擇性地沉積在相對於金屬表面的低k介電質表面（例如，以氧化矽為基礎的表面）。
圖3顯示一些實施例的示意圖，其中基材302包括第一結構304的第一表面（例如，介電層的介電質表面）和具有不同材料成分的第二結構306的第二表面（例如，金屬層的金屬表面，諸如鈷、銅或鎢表面），其更包含具有第一厚度的初始鈍化層308A（例如，20 nm聚醯亞胺有機層），其中材料312是選擇性地沉積在相對於該第二表面的該第一表面上（由於選擇性相對於所覆蓋的初始鈍化層308A）。在一些實施例中，選擇性地沉積的材料312是氧化物材料。在一些實施例中，該氧化物材料是介電材料。在本說明書描述的實例中，該介電氧化物是氧化矽膜。如圖3所示，在一或多個循環的選擇性沉積製程310（例如，500個循環的以氧為基礎的PEALD氧化矽沉積製程）之後，材料312（例如，50nm的SiO）沉積在該第一結構304的第一表面上方，殘餘鈍化層308B已減小到第二厚度（例如，10 nm的聚醯亞胺有機層）。在一些實施例中，先停止該選擇性沉積製程，然後移除所有初始鈍化層。在一些實施例中，在完成該選擇性沉積製程之後，可隨後移除減小厚度的殘餘鈍化層308B（例如，藉由灰化法）而沒有沉積暴露該第二結構306的第二表面。
在一些實施例中，揭露的PEALD製程可實現在介電質表面上選擇性形成氧化矽或其他氧化物。在一些實施例中，相較於習知的圖案化製程，揭露的PEALD製程可實現減少各種裝置製造製程流程中形成想要圖案的步驟次數。
熟習該項技藝者應瞭解可進行許多和各種修改，不致悖離本發明的精神。所描述的特徵、結構、特性及前驅物可以任何合適方式組合。因此，應該清楚理解本發明之形式僅為說明性而不是意欲限制本發明之範圍。所有修改及變化意欲歸屬於如由隨附申請專利範圍所界定之發明範疇內。
100、200‧‧‧流程圖
102、104、106、110、202、204、206、212‧‧‧方塊
108、208、210‧‧‧判斷方塊
302‧‧‧基材
304‧‧‧第一結構
306‧‧‧第二結構
308A‧‧‧初始鈍化層
308B‧‧‧殘餘鈍化層
310‧‧‧選擇性沉積製程
312‧‧‧材料
圖1A為示意說明用於在第一表面上沉積材料，同時減小在第二表面上方的鈍化層厚度之選擇性沉積製程的流程圖。
圖1B為示意說明用於在第一表面上沉積材料，同時減小選擇性地沉積在第二表面上方的鈍化層厚度之選擇性沉積製程的流程圖。
圖2為顯示聚醯亞胺層（polyimide layer）的厚度與進行氧化的循環次數一些實施例之圖式，其中計算鈍化層灰化速率（passivation ash rate）。
圖3示意說明藉由循環沉積製程在基材的第一表面上選擇性沉積材料，同時循環沉積製程移除第二表面上方的鈍化層。

Claims (30)

  1. 一種用於在圖案化基材的第一表面上選擇性形成介電材料的原子層沉積（ALD）製程，其包括： 提供含有第一表面和第二表面的基材，其中該第二表面包括在其上的鈍化層； 進行至少一沉積循環，該沉積循環包括交替及依序使該基材接觸第一前驅物和含氧的第二反應物； 其中該第二反應物與該第一前驅物起反應，以在該第一表面上形成介電材料；及 其中在每個沉積循環期間，該第二反應物使該鈍化層灰化。
  2. 如申請專利範圍第1項所述之方法，其中該第一表面是介電質表面。
  3. 如申請專利範圍第2項所述之方法，其中該介電質表面包含氧化矽。
  4. 如申請專利範圍第1項所述之方法，其中該第一表面包含低k材料。
  5. 如申請專利範圍第1項所述之方法，其中該第二表面是金屬表面。
  6. 如申請專利範圍第5項所述之方法，其中該金屬表面包含Co、Cu或W之至少一者。
  7. 如申請專利範圍第1項所述之方法，其中該介電材料是氧化物。
  8. 如申請專利範圍第7項所述之方法，其中該氧化物是氧化矽。
  9. 如申請專利範圍第7項所述之方法，其中該氧化物是金屬氧化物。
  10. 如申請專利範圍第1項所述之方法，其中該第一前驅物包含金屬前驅物、矽前驅物或其混合物。
  11. 如申請專利範圍第1項所述之方法，其中該第一前驅物是烷基胺基矽烷。
  12. 如申請專利範圍第1項所述之方法，其中該鈍化層包含有機材料。
  13. 如申請專利範圍第1項所述之方法，其中先選擇性地將該鈍化層沉積在相對於該第一表面的該第二表面上，然後開始該第一沉積循環。
  14. 如申請專利範圍第1項所述之方法，其中該沉積循環重複多次，以在介電質表面上形成想要的厚度的氧化物膜。
  15. 如申請專利範圍第14項所述之方法，更包括在每個沉積循環的開始和結束之間，選擇性沉積額外的鈍化層至該鈍化層。
  16. 如申請專利範圍第1項所述之方法，其中該ALD製程是電漿輔助原子層沉積（PEALD）製程。
  17. 如申請專利範圍第1項所述之方法，其中該至少一沉積循環是先從使該基材接觸該第二反應物開始，然後接觸該第一前驅物。
  18. 如申請專利範圍第1項所述之方法，其中該至少一沉積循環更包括在每個循環中使該基材接觸至少一額外的反應物。
  19. 如申請專利範圍第1項所述之方法，其中使該基材接觸該第二反應物更包括使用電漿活化該第二反應物。
  20. 如申請專利範圍第1項所述之方法，其中選擇性地將該介電材料形成在相對於該鈍化層的該第一表面上。
  21. 如申請專利範圍第1項所述之方法，其中該介電材料形成在該鈍化層上，且其中藉由該鈍化層的灰化而從該鈍化層移除該介電材料，藉此選擇性地在該第一表面上形成該介電材料。
  22. 一種用於在圖案化基材的表面上選擇性形成材料的循環沉積製程，其包括： 提供含有第一表面和第二表面的基材，其中該第二表面包含在其上的鈍化層； 進行至少一沉積循環，該沉積循環包括交替及依序使該基材接觸第一前驅物和第二反應物； 其中該第二反應物與該第一前驅物起反應，以在該第一表面上形成該材料；及 其中在每個沉積循環期間，藉由該第二反應物蝕刻該鈍化層。
  23. 如申請專利範圍第22項所述之循環沉積製程，其中該製程包括原子層沉積（ALD）。
  24. 如申請專利範圍第23項所述之循環沉積製程，其中該製程包括電漿輔助原子層沉積（PEALD）。
  25. 如申請專利範圍第22項所述之循環沉積製程，其中該第二反應物包含電漿活化物質。
  26. 如申請專利範圍第25項所述之循環沉積製程，其中該第二反應物包含氧，該鈍化層包含有機層，且蝕刻包含灰化。
  27. 如申請專利範圍第26項所述之循環沉積製程，其中該鈍化層包含聚合物。
  28. 如申請專利範圍第22項所述之循環沉積製程，其中先停止沉積，然後該鈍化層的蝕刻暴露該第二表面。
  29. 如申請專利範圍第28項所述之循環沉積製程，更包括在停止沉積之後且在繼續沉積之前，在該第二表面上方進一步沉積額外的鈍化層。
  30. 一種用於在圖案化基材的第一介電質表面上選擇性形成氧化物材料的電漿輔助原子層沉積（PEALD）製程，其包括： 提供含有第一介電質表面和第二金屬表面的基材，其中該第二金屬表面包含在其上的有機鈍化層； 進行至少一沉積循環，該沉積循環包括交替及依序使該基材接觸第一前驅物及含氧和電漿的第二反應物； 其中該第二反應物與該第一前驅物起反應，以在該第一介電質表面上形成氧化物材料；及 其中在每個沉積循環期間，該第二反應物使該有機鈍化層灰化。
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KR20230051653A (ko) 2023-04-18
CN110444476A (zh) 2019-11-12
US20190341245A1 (en) 2019-11-07
TWI820967B (zh) 2023-11-01
JP2022177198A (ja) 2022-11-30
TW202242172A (zh) 2022-11-01
KR20190127578A (ko) 2019-11-13
US20210118669A1 (en) 2021-04-22
TWI783909B (zh) 2022-11-11

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