TW201830700A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW201830700A
TW201830700A TW106120148A TW106120148A TW201830700A TW 201830700 A TW201830700 A TW 201830700A TW 106120148 A TW106120148 A TW 106120148A TW 106120148 A TW106120148 A TW 106120148A TW 201830700 A TW201830700 A TW 201830700A
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Taiwan
Prior art keywords
gate
opening
metal
metal silicide
layer
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TW106120148A
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English (en)
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TWI738795B (zh
Inventor
王喻生
林鈺庭
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台灣積體電路製造股份有限公司
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    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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Abstract

一種半導體裝置，包括：金屬矽化物區域，形成於半導體材料中，金屬矽化物區域包括第一材料及第二材料，第一材料包括金屬，第二材料包括氯、氟或其組合，金屬矽化物區域之最上部有具有第一濃度之第二材料；蓋層，於金屬矽化物區域及接觸栓塞開口之側壁上；以及接觸栓塞，形成於蓋層之上，填充接觸栓塞開口。

Description

半導體裝置
本發明係關於一種半導體裝置，且更關於可降低鰭式場效電晶體的源極/汲極區上形成的接點電阻的一種半導體裝置。
隨著對積體電路的微縮化以及積體電路速度的要求越來越高，電晶體需要有較高的驅動電流以及越來越小的尺寸，因而發展了鰭式場效電晶體(Fin Field-Effect Transistors，FinFET)。鰭式場效電晶體包括基板上方垂直的半導體鰭片。半導體鰭片用於形成源極和汲極區域，並且在源極和汲極區域之間形成通道區。形成淺溝槽隔離(Shallow Trench Isolation，STI)區域以定義半導體鰭片。鰭式場效電晶體還包括形成於半導體鰭片的側壁及頂表面上的閘極堆疊。雖然現有的鰭式場效電晶體裝置及其製造方法通常已經足以滿足其預期目的，但還沒有在所有方面都完全令人滿意。
由於隨著技術和製造使半導體的其他方面微縮化，使得可用於產生接點(contact)的總面積也跟著微縮化，所以低電阻接點越來越重要。
在一些實施例中，本發明揭露了一種半導體裝 置，包括：金屬矽化物區域，形成於半導體材料中，金屬矽化物區域包括第一材料及第二材料，第一材料包括金屬，第二材料包括氯、氟或其組合，金屬矽化物區域之最上部有具有第一濃度之第二材料；蓋層，於金屬矽化物區域及接觸栓塞開口之側壁上；以及接觸栓塞，形成於蓋層之上，填充接觸栓塞開口。
在另一些實施例中，本發明揭露了一種半導體裝置，包括：鰭式場效電晶體，具有第一閘極結構及第二閘極結構，每個第一閘極結構及第二閘極結構各自包括第一閘極間隔物及第二閘極間隔物，每個第一閘極間隔物係與每個第二閘極間隔物分離；源極/汲極區，介於第一閘極結構及第二閘極結構間；接點，包括：側壁，包括第一金屬材料，第一金屬材料與第一閘極之第一閘極間隔物及第二閘極之第二閘極間隔物重合；底部，包括於源極/汲極區之頂表面上之金屬矽化物；栓塞，介於接點之側壁間及接點之底部上，栓塞包括導電材料；蓋層，介於栓塞及金屬矽化物間；其中金屬矽化物延伸至第一閘極結構之第一閘極間隔物及第二閘極結構之第二閘極間隔物下。
在又一些實施例中，本發明揭露了一種半導體裝置形成方法，包括：於第一閘極及第二閘極間形成開口；清洗開口；以第一材料轟擊開口之底部，從而於第一材料及接觸區域之頂表面間引發化學反應；於開口中沉積金屬層；於金屬層上沉積蓋層；於接觸區域之頂表面生成金屬矽化物；以及於生成金屬矽化物後，於開口中沉積金屬栓塞。
30‧‧‧鰭式場效電晶體
32‧‧‧基板
34‧‧‧隔離區
36‧‧‧鰭片
38‧‧‧閘極介電質
40‧‧‧閘極電極
42、43、44‧‧‧源極/汲極區
100‧‧‧半導體裝置
102‧‧‧鰭片
103a、103b‧‧‧半導體鰭片材料
105a、105b、105c‧‧‧源極/汲極材料
110a、110b‧‧‧閘極堆疊
111a、111b‧‧‧閘極介電層
115a、115b‧‧‧閘極電極
119a、119b‧‧‧硬罩幕
119-1、123-1、127-1、131-1、229-1‧‧‧頂表面
123a、123b‧‧‧第一閘極間隔物
127a、127b‧‧‧第二閘極間隔物
127c、127d‧‧‧閘極間隔物
131‧‧‧介電層
135‧‧‧光阻
136、201、211‧‧‧開口
205‧‧‧預清洗製程
207‧‧‧物理轟擊
215’‧‧‧金屬層
219‧‧‧蓋層
225‧‧‧金屬矽化物層
229‧‧‧導電栓塞
305、310、315、320、325、330、335、340‧‧‧步驟
A-A‧‧‧剖面
h1‧‧‧深度
w1、w2、w3‧‧‧寬度
以下將配合所附圖式詳述本發明之實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪示且僅用以說明例示。事實上，可能任意地放大或縮小元件的尺寸，以清楚地表現出本發明的特徵。
第1圖是鰭式場效電晶體範例的三維視圖。
第2-9圖係根據一些實施例繪示在不同顯影階段的鰭式場效電晶體的範例。
第10圖係根據一些實施例繪示的流程圖。
第11圖係根據一些實施例繪示之源極/汲極接點的金屬矽化物區域之化學指數圖。
以下公開許多不同的實施方法或是範例來實行所提供之標的之不同特徵，以下描述具體的元件及其排列的實施例以闡述本發明。當然這些實施例僅用以例示，且不該以此限定本發明的範圍。例如，在說明書中提到第一特徵形成於第二特徵之上，其包括第一特徵與第二特徵是直接接觸的實施例，另外也包括於第一特徵與第二特徵之間另外有其他特徵的實施例，亦即，第一特徵與第二特徵並非直接接觸。此外，在不同實施例中可能使用重複的標號或標示，這些重複僅為了簡單清楚地敘述本發明，不代表所討論的不同實施例及/或結構之間有特定的關係。
此外，其中可能用到與空間相關用詞，例如“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，這些空間相關用詞係為了便於描述圖示中一個(些) 元件或特徵與另一個(些)元件或特徵之間的關係，這些空間相關用詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，則其中所使用的空間相關形容詞也將依轉向後的方位來解釋。
本發明實施例提供降低接點電阻的能力。通常可以藉由增加接點的接觸面積，或降低接點材料的電阻，以提高接點的電導率進而降低接點的電阻。例如，一些內連線可使用種子層(seed layer)，以改善於兩種分離材料界面處的電導率。根據本發明一些實施例，可在兩種材料的界面形成金屬矽化物，以增加接點的電導率(或降低其電阻)。此外，於一些實施例中，可於接觸界面施加預清洗和化學反應，從而增加金屬矽化物的寬度和深度。可以在接觸界面上形成接點。雖然接點的形成解釋為與鰭式場效電晶體相關，本領域具有通常知識者應理解，於此討論之接點的應用、結構和其形成方法並不限於在鰭式場效電晶體結構中使用。
第1圖是鰭式場效電晶體30範例的三維視圖。鰭式場效電晶體30包括基板32上的鰭片36。基板32包括隔離區34，和突出於相鄰的隔離區34且位於其之間的鰭片36。於此範例中，鰭式場效電晶體30包括兩個閘極電極38/40，然而，鰭式場效電晶體可以包含一個閘極或兩個以上的閘極。閘極介電質38係沿著鰭片36的側壁和位於鰭片36的頂表面上，閘極電極40係位於閘極介電質38上。源極/汲極區42和43以及43和44係設置在閘極電極38/40相反側的鰭片中。第1圖更繪示於隨後的圖 式中所使用之參考剖面。剖面A-A沿著鰭片36的長平分鰭片36。後續附圖係參照本參考剖面。
第2圖至第9圖係根據一示例性實施例，繪示形成接點之中間步驟的剖面圖。附圖中使用的標號可包括用於區分一種特定結構與另一種特定結構的字母，否則它們是相同的、可互換的或功能上不可區分的。在使用這種字母的情況下，沒有相應字母的標號表示兩個/所有特定結構。舉例來說，標號103本身包括對應於103a、103b、103c等的廣義結構。
第2圖包括具有半導體基板115以及形成於其上的鰭片102的半導體裝置100。半導體裝置100可以是主動裝置，如電晶體，雖然其它實施例可以包括各種主動和被動裝置，如電阻、電容、電感、二極體、可變電容等或其組合。鰭片(如第1圖的鰭片36或第3圖的鰭片102)係由半導體鰭片材料103a/103b和源極/汲極材料105a/105b/105c所形成。可從半導體基板115形成半導體鰭片材料103a/103b。半導體基板115可以是半導體晶圓或半導體裝置的一部分。根據本發明一些實施例，半導體基板115包括結晶矽。可以用於半導體基板115中的其它材料包括碳、鍺、鎵、硼、砷、氮、銦及/或磷等。半導體基板115也可以包括其他半導體材料，例如III-V族化合物半導體材料。半導體基板115可為塊體(bulk)基板或絕緣體上半導體(Semiconductor-on-Insulator，SOI)基板。此外，半導體基板115可以包括其他特徵。舉例來說，上述基板可以根據設計要求包括各種摻雜區(例如p型基板或n型基板)。舉例來說，摻雜區可摻雜有p型摻質(如硼或BF2)、n型摻質(如磷 或砷)及/或其組合。可配置用於n型鰭式場效電晶體的摻雜區，或者可替換地配置用於p型鰭式場效電晶體的摻雜區。
根據一些實施例，可於半導體鰭片102上形成一或多個閘極堆疊110。半導體鰭片102包括源極/汲極材料105a/105b/105c和半導體鰭片材料103a/103b。閘極堆疊110可包括金屬閘極電極115a/115b、閘極絕緣體或介電質111a/111b、可選的(optional)第一閘極間隔物123a/123b、第二閘極間隔物127a/127b和形成在金屬閘極電極115a/115b上的自我對準(self-aligned)接點/硬罩幕119a/119b。
於一些實施例中，可使用先閘極方法(gate-first approach)形成閘極堆疊110，然而於其他實施例中，可使用後閘極方法(gate-last approach)形成閘極堆疊110。閘極堆疊110a和110b係形成在基板103a/103b上。
於一些實施例中，可先形成虛置閘極堆疊。虛置閘極堆疊可以包括虛置閘極介電質、硬罩幕和虛置閘極。閘極堆疊110a/110b可替代虛置閘極堆疊。可蝕刻並去除虛置閘極電極和虛置閘極介電質。可於去除虛置閘極電極和虛置閘極介電質後所留下之凹槽中共形地(conformally)沉積閘極介電質111a/111b。閘極介電層111a/111b可以包括氧化矽、氮化矽或其多層。於一些實施例中，閘極介電層111a/111b包括高介電常數(high-k)介電材料，並且可以包括如Hf、Al、Zr、La、Mg、Ba、Ti、Pb及其組合的金屬氧化物或金屬矽化物。形成閘極介電層111a/111b的方法可包括分子束沉積(molecular-beam deposition，MBD)、原子層沉積(atomic layer deposition， ALD)、電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition，PECVD)等。
閘極電極115a/115b分別沉積於閘極介電層111a/111b上，且填充凹槽的剩餘部分。可以由含金屬材料(如TiN、TaN、TaC、Co、Ru、Al、其組合或其多層)形成閘極115a/115b。於填充閘極電極40之後，可以實行平坦化製程，如化學機械拋光(chemical mechanical polishing，CMP)製程，以去除閘極介電層111a/111b的多餘部分和閘極電極115a/115b的材料。於一或多個蝕刻步驟凹蝕閘極電極115a/115b和閘極介電質111a/111b，以使凹槽係形成於閘極間隔物123/127之中。可使用可接受的蝕刻製程，如對閘極電極115a/115b及閘極介電質111a/111b的材料有選擇性的蝕刻製程。上述凹槽允許隨後於凹槽內形成硬罩幕119a/119b以保護取代閘極電極115a/115b。
在閘極電極115a/115b和閘極介電質111a/111b上的凹槽內形成硬罩幕119a/119b。可由SiN、SiON、SiO2等或其組合製成硬罩幕119a/119b。可以由化學氣相沉積(chemical vapor deposition，CVD)、物理氣相沉積(physical vapor deposition，PVD)、ALD、介電材料旋轉塗佈(spin-on-dielectric)製程等或其組合形成硬罩幕119a/119b。
可於半導體基板115中形成源極/汲極區105a/105b/105c。可於形成虛置閘極堆疊或形成閘極堆疊110a/110b之後形成源極/汲極區105a/105b/105c。於一些實施例中，可藉由實行佈植製程摻雜源極/汲極區105a/105b/105c以植 入適當摻質，進而補充半導體基板115中的摻質。在其它實施例中，可以藉由在半導體基板115中形成凹槽(未示出)及於上述凹槽中磊晶生長材料，以形成源極/汲極區105a/105b/105c。可以藉由使用任何可接受的蝕刻製程來蝕刻以形成凹槽，如反應離子蝕刻(reaction ion etching，RIE)、中性束蝕刻(neutral beam etching，NBE)、四甲基氫氧化銨(tetramethyalammonium hydroxide，TMAH)、氫氧化銨(NH4OH)、對矽及隔離區的材料(未示出)有良好蝕刻選擇性之能夠蝕刻矽的濕蝕刻劑等或其組合。蝕刻可以是非等向性的。可實行單一蝕刻製程或多重蝕刻製程來蝕刻半導體鰭片102。可在凹槽中磊晶地生長材料105a/105b/105c以形成源極/汲極區105a/105b/105c於凹槽中，例如藉由金屬有機化學氣相沉積(metal-organic CVD，MOCVD)、分子束磊晶(molecular beam epitaxy，MBE)、液相磊晶(liquid phase epitaxy，LPE)、氣相磊晶(vapor phase epitaxy，VPE)、選擇性磊晶生長(selective epitaxial growth，SEG)等或其組合。
可以藉由如上所述之佈植方法或於材料生長時同時摻雜源極/汲極區105a/105b/105c。磊晶源極/汲極區105a/105b/105c可包括任何可接受的材料，如適合n型場效電晶體及/或p型場效電晶體的材料。舉例來說，在n型構造中，若半導體基板115為矽，磊晶源極/汲極區105a/105b/105c可包括Si、SiC、SiCP、SiP等。舉例來說，在p型構造中，若半導體基板115為矽，磊晶源極/汲極區105a/105b/105c可以包括SiGe、SiGeB、Ge、GeSn等。磊晶源極/汲極區105a/105b/105c 可以具有比半導體基板115的頂表面高的表面，並且可以具有晶面(facets)。
於形成鰭式場效電晶體之後，於一些實施例中，可在上述結構上形成介電層131。可以在介電層中形成接點，以電性耦接閘極和源極/汲極區至其它裝置或結構。於一些實施例中，介電層131可包括多層。
第2圖的元件135顯示額外的光阻層或氧化矽光阻層135，其沉積在半導體基板115上然後被圖案化，從而在光阻層135中形成開口136。一般來說，微影技術利用沉積的光阻材料(如光阻135)、照射(曝光)和顯影以去除部分光阻材料。剩餘的光阻材料於後續的製程步驟如蝕刻中保護其下的材料，例如本範例中的介電材料131。在這個範例中，圖案化光阻材料以定義將被蝕刻的區域，以及相反地，定義將被保護以免被蝕刻劑蝕刻的區域。在未使用介電材料131的實施例中，不使用光阻135。
值得注意的是，開口136可以比閘極結構110a/110b之間的寬度更寬。或者換句話說，開口136不必精確地位於閘極結構110a/110b上方。於一些實施例中，開口136可以跨越多個閘極堆疊。
第3圖係繪示在蝕刻由光阻罩幕135曝光所留下的介電質後的鰭式場效電晶體的剖面圖。可由任何適合的技術蝕刻介電質，如使用對介電材料131具有選擇性的乾蝕刻劑或濕蝕刻劑。於蝕刻之後可去除光阻135。蝕刻在閘極結構110a/110b之間形成開口201並露出源極/汲極105b的頂部。
當露出源極/汲極105b時，可形成氧化物。例如，如果源極/汲極105b是基於矽的(silicon-based)，源極/汲極105b的頂部可在鰭片頂部具有氧化矽(SiO)。氧化物可藉由引起增加的電阻以干擾源極/汲極105b上之接點的形成。因此，可以在形成接點之前清洗/去除氧化物。
第4圖繪示預清洗製程205和物理轟擊207。使用氬(Ar)氣作為清洗蝕刻劑來實行預清洗製程205。可以使用其它清洗蝕刻劑如NF3、NH3、H2、N2、混合氣Ar/H2和Ar/N2。可於實行預清洗製程205之後、交替或同時實行物理轟擊207。
於一些實施例中，可於蝕刻腔室(未示出)或沉積腔室(未示出)中使用射頻(radio-frequency,RF)訊號產生器(未示出)，以產生使用功率高達約1.5kW的電漿，如約200W。在其它實施例中，可提高功率至高達約1.5kW，如至約400W。在預清洗製程205中，在腔室中填充氬氣，且露出開口201於蝕刻腔室中所產生的電漿。在物理轟擊207製程中，可加入轟擊材料至蝕刻腔室中。轟擊材料可以是氯氣、氟氣、氨氣或其組合。開口201係露出於電漿。當露出開口201於預清洗製程和轟擊材料時，開口201將變寬而成為開口211。開口211具有包括閘極間隔物127c/127d的側壁，其在清洗蝕刻/物理轟擊製程中被薄化。
根據一些實施例，使用如上所述之製程氣體作為轟擊材料實行物理轟擊。也可存在其它製程氣體，包括氬、氦、氮(N2)、氫(H2)、氙、砷、鍺、磷等。從轟擊材料產生離子並用於轟擊開口201。在真空環境(如蝕刻腔室)中實行轟擊。 製程氣體的流速可介於約1sccm至約20000sccm。製程氣體的壓力可介於約0.1mTorr至約1Torr。偏壓可介於約20eV至約5keV。轟擊的持續時間可介於約1秒至約90秒。
被轟擊的表面區包括源極/汲極105b的頂表面和閘極間隔物表面127c/127d。閘極間隔物和源極/汲極105b可包括原生氧化物。作為轟擊的結果，表面區變得更粗糙且閘極間隔物127c/127d變薄。此外，經轟擊的表面區的材料(如氧化物)之間的鍵結可能被破壞或鬆動。因此，經轟擊的表面區可在隨後的化學反應步驟中吸附更多製程氣體。
可於轟擊中將離子植入源極/汲極區105b中。植入的離子可以具有減少隨後形成的金屬矽化物區域之間以及接觸栓塞和源極/汲極區105b之間的電阻的功能。這可降低接觸栓塞的接觸電阻。可藉由調整轟擊離子種類和轟擊能量以進一步調整接觸電阻。
在物理轟擊製程207中，化學反應將發生於轟擊材料與源極/汲極區105b之間源極/汲極區105b之露的表面處，且轟擊材料將被併入源極/汲極區105b的頂部中。舉例來說，當使用氟化銨(ammonium fluoride)氣體作為轟擊材料時，氟化銨可與氧化矽反應，以產生氟矽酸銨(ammonium fluorosilicate)化合物。物理轟擊製程207可包括多個循環，以提供多個氣體反應。可根據電漿製程來調節氣體注入，以由跨越開口211底部的特定區域將氣體注入。
可藉由將氣體清洗蝕刻劑(如氬氣)和物理轟擊材料(如氯、氟、氨或其組合)同時填充至蝕刻腔室以同時實 行預清洗製程205和物理轟擊207。可存在額外的氣體，包括氫氣和氮氣。
參照第5圖，可於開口211露出的表面上形成金屬層215。於一些實施例中，隨後形成第7圖的金屬矽化物層225的製程將大抵消耗金屬層215。可由鈦、鎳、鈷、鎢、鉑、鉬、鉭等或其組合形成金屬層215。如第5圖所示，金屬層215包括與源極/汲極區105b的頂部接觸之開口的底部的一部分、沿著開口211的側壁延伸的部分及延伸於閘極堆疊110a/110b上方的部分。於一些實施例中，金屬層215也可延伸至介電材料131上方。於一些實施例中，可藉由如PVD、CLD、ALD、濺鍍沉積等或其組合以形成厚度為約30Å至約200Å的金屬層215。於一些實施例中，可於由RF訊號產生器施加偏壓的同時藉由PVD、CLD、ALD或濺鍍實行沉積。可共形地沉積金屬層32，以使其在沿著開口211的底部和側壁及於閘極堆疊110a/110b上方具有大致均勻的厚度。
參照第6圖，在金屬層215上及開口211中形成蓋層219。蓋層219改善第7圖中隨後形成的導電栓塞229之間的黏著力，且亦預防金屬層225的氧化。蓋層219也可作為幫助形成金屬矽化物的阻障層。蓋層219有助於穩定金屬層215且預防金屬層225穿透至導電栓塞229。可由多層形成蓋層219。可由氮化鈦、氮化鉭等或其組合形成蓋層219。如第6圖所示，蓋層219包括在開口211之底部的一部分、沿開口211的側壁延伸的部分和延伸至閘極堆疊110a/110b上方的部分。於一些實施例中，部分的蓋層219可以延伸至介電質131上方。於一些實施例中， 藉由CVD、PVD、ALD等或其組合的單一或多次循環以形成厚度約5Å至約50Å的蓋層219。可以共形地沉積蓋層219，以使其在沿開口211的底部和側壁及於閘極堆疊110a/110b上方具有大抵均勻的厚度。
參照第7圖，矽化製程從金屬層215形成金屬矽化物層225。金屬矽化物層225的形成包括於半導體裝置100上實行退火製程。退火製程使轟擊材料和轟擊源極/汲極區105b與金屬層215反應以形成金屬矽化物層225。於一些實施例中，使用快速熱退火(rapid thermal anneal)、熱浸泡(thermal soaking)、尖波退火(spike annealing)、快速加熱退火(flash annealing)、雷射退火(laser annealing)、微波退火(microwave annealing)等或其組合實行退火製程。於一些實施例中，在介於約100℃至約900℃的溫度下，於包括如N2、NH3、H2、混合氣體等或其組合的製程氣體的環境中，及介於1Torr至約760Torr的壓力下實行退火製程。
於一些實施例中，退火腔室可包括加熱載台(heater stage)(未繪示)以支撐晶圓使其可被加熱到約30℃至約120℃。退火腔室可以是電漿蝕刻腔室(plasma etching chamber)，其具有用於輸送製程氣體至電漿蝕刻腔室的蓮蓬頭式腔室蓋(shower head chamber lid)(未繪示)，其中所述腔室蓋還具有退火功能，例如上述之退火功能。
於一些實施例中，在形成金屬矽化物層225後，可以留下部分未轉化為金屬矽化物層225的金屬層215'。
如第7圖所示，金屬矽化物層225包括深度h1和寬 度w3。相較於無化學反應而能夠形成金屬矽化物層225的情況，轟擊材料與鰭片105b頂部的化學反應有助於形成具有更大寬度和深度的金屬矽化物層225。於一些實施例中，寬度w1可以介於約10nm至約20nm。寬度w2可以介於約15nm至約25nm。寬度w3可以介於約15nm至約30nm。於一些實施例中，w3與w1的比例增加了約6%或以上。於一些實施例中，金屬矽化物的深度h1大於約6nm或7nm。轟擊材料與開口211底部的轟擊可以增加接點開口211側壁的節距(pitch)，使得它們比轟擊之前更加垂直。在側壁是相鄰閘極結構的閘極間隔物處，相較於閘極堆疊的閘極間隔物127a和127b，相應之開口211側壁的閘極間隔物(如閘極間隔物127c及127d)，可更加垂直及更薄。於一些實施例中，開口211的寬度w1與開口211的底部寬度w2的尺寸比值大於約90%。
於形成金屬矽化物層225後，轟擊材料(如氟或氯)的元素濃度可以在金屬層215’和金屬矽化物層225的界面處的化學指數(chemical index)中找到。於第11圖中，如下所述，使用氟作為代表顯示這些元素之間的關係。在靠近金屬矽化物層225的頂部之金屬層215'和金屬矽化物層225的界面處，可以找到轟擊材料的第一濃度。轟擊材料的第一濃度可為金屬矽化物層225中轟擊材料的峰值濃度。形成金屬矽化物層225的矽化製程也可以導致轟擊材料浸入回到(leech back)金屬層215'中。因此，於一些實施例中，可以在金屬層215'的化學指數中找到轟擊材料。進一步往金屬矽化物層225中移動，轟擊材料的化學指數會下降直到其為微量(trace amount)。於一些實 施例中，於金屬矽化物深度的大約一半處將存在微量的轟擊材料。轟擊材料的第二濃度可以開始於金屬矽化物深度的大約一半處，且以大約相同的濃度持續遍及至剩餘的金屬矽化物層225。
參照第8圖，可以導電材料229填充第7圖的開口211。於一些實施例中，導電材料229填充開口211，且亦延伸至介電層131上方。於一些實施例中，導電材料229可填充開口211，且不延伸至介電層131上方。導電材料229包括第9圖的隨後將形成之導電栓塞229'。導電材料229包括任何合適的金屬或合金，例如鎢、鋁、銅、氮化鈦、氮化鉭等或其組合。可實行CVD、ALD、PVD、濺鍍等或其組合以形成導電材料。可藉由沉積多層的多重步驟形成導電材料229。
參照第9圖，可於導電材料229上實行平坦化製程以形成導電栓塞229'。於一些實施例中，平坦化製程是化學機械拋光製程、蝕刻製程等或其組合。於平坦化製程後，導電栓塞229’的頂表面229-1與介電層131的頂表面131-1、閘極硬罩幕119a/119b的頂表面119a-1/119b-1、閘極間隔物123/127的頂表面123-1/127-1、金屬層215'的最頂表面及蓋層219的最頂表面大抵共面。金屬矽化物層225、未反應的金屬層215’(若存在)、蓋層219和導電栓塞229’形成接觸結構233。
於一些實施例中，可於矽化源極/汲極區105b的同時或之後矽化源極/汲極區105a/105c，且於其中形成相應的接觸結構。可使用上述與矽化源極/汲極區105b相同的製程以矽化源極/汲極區105a/105c。細節不於此處重複。
於一些實施例中，可在閘極堆疊110a/110b上形成閘極接點。於一些實施例中，可使用上述的矽化製程以形成用於閘極接點的閘極金屬矽化物。於一些實施例中，上述矽化製程可以用於形成接點或其它類型的半導體裝置，例如其它類型的電晶體、奈米線(nano-wire)電晶體和中介層(interposer)。
第10圖係根據一些實施例繪示之流程圖。在步驟305中，於形成源極/汲極區(如第2圖的源極/汲極區105a/105b/105c)和閘極堆疊(如閘極堆疊110a/110b)後，於源極/汲極區上形成開口。
在步驟310中，使用清洗劑清洗開口。於一些實施例中，清洗劑可以是氬氣或電漿，用於蝕刻開口以除去任何殘留的氧化物或介電材料(如第3圖的來自介電材料131的殘留物)。
在步驟315中，藉由轟擊材料轟擊開口。轟擊材料可為氯、氟或其組合。如上所述，可藉由RF產生器產生電漿。於一些實施例中，可以同時進行步驟310和315。於一些實施例中，可交替重複步驟310和315。於一些實施例中，可重複約1至5次清洗和物理轟擊。於一些實施例中，可重複更多次清洗和物理轟擊，例如10或20次。藉由清洗和物理轟擊，可薄化形成開口之側壁的閘極間隔物。
在步驟320中，於開口中形成金屬層。金屬層的形成已在上述關於第5圖中詳細討論，在此不再重複。
在步驟325中，在金屬層上形成蓋層。金屬層的形成已在上述關於第6圖中詳細討論，在此不再重複。
在步驟330中，在源極/汲極區中形成金屬矽化物。由於轟擊材料在源極/汲極區表面的反應，金屬矽化物的形成可以比原本更寬廣和更深。舉例來說，金屬矽化物可以包括閘極間隔物下方的區域。矽化物的形成已在上述關於第7圖中詳細討論，在此不再重複。
在步驟335中，以導電材料填充開口。在步驟340中，將導電材料平坦化以使其與閘極堆疊大抵共面。
第11圖係根據一些實施例繪示之金屬矽化物區域225的化學指數圖表。垂直虛線位於圖表上的大概區域中，其被定義為金屬矽化物區域。每個虛線都是約略的，並且可理解為在由每個虛線上方的箭頭所示的範圍內。化學指數顯示形成金屬矽化物區域的鈦和矽。於金屬矽化物區域也存在氟，其於本範例中用作轟擊材料。用於形成金屬矽化物的退火製程可引起轟擊材料浸入或擴散回到金屬層215'和蓋層219中。因此，可以在金屬層215'和蓋層219中找到轟擊材料的濃度。轟擊材料在金屬矽化物層的最上部分或表面處具有其峰值濃度。轟擊材料的濃度在金屬矽化物層深度約一半時顯著下降到第二濃度。對於金屬矽化物層的剩餘深度，轟擊材料的濃度在第二濃度處保持大約相同。
接觸結構233電性耦接源極/汲極區105a/105b/105c至其上的結構(未示出)，如導電線/通孔及/或其它主動和被動裝置。舉例來說，可在接觸結構233和介電層131上形成包括交替的介電材料層和導電材料層的內連線結構。接觸結構233可電性耦接源極/汲極區105b至這種內連線結構。
本發明實施例可提供降低形成於鰭式場效電晶體的源極/汲極區上之接點的電阻的能力。藉由以預清洗製程和諸如氯或氟之材料的物理轟擊來預處理接點開口，隨後形成的金屬矽化物相較於未經由預清洗製程和物理轟擊所形成之金屬矽化物可具有較低的電阻。金屬矽化物可更寬且更深入源極/汲極區。接觸孔本身的底部也可以比以前更寬。
在一些實施例中，本發明揭露了一種半導體裝置，包括：金屬矽化物區域，形成於半導體材料中，金屬矽化物區域包括第一材料及第二材料，第一材料包括金屬，第二材料包括氯、氟或其組合，金屬矽化物區域之最上部有具有第一濃度之第二材料；蓋層，於金屬矽化物區域及接觸栓塞開口之側壁上；以及接觸栓塞，形成於蓋層之上，填充接觸栓塞開口。
在另一些實施例中，本發明揭露了一種半導體裝置，包括：鰭式場效電晶體，具有第一閘極結構及第二閘極結構，每個第一閘極結構及第二閘極結構各自包括第一閘極間隔物及第二閘極間隔物，每個第一閘極間隔物係與每個第二閘極間隔物分離；源極/汲極區，介於第一閘極結構及第二閘極結構間；接點，包括：側壁，包括第一金屬材料，第一金屬材料與第一閘極之第一閘極間隔物及第二閘極之第二閘極間隔物重合；底部，包括於源極/汲極區之頂表面上之金屬矽化物；栓塞，介於接點之側壁間及接點之底部上，栓塞包括導電材料；蓋層，介於栓塞及金屬矽化物間；其中金屬矽化物延伸至第一閘極結構之第一閘極間隔物及第二閘極結構之第二閘極間隔物下。
在又一些實施例中，本發明揭露了一種半導體裝置形成方法，包括：於第一閘極及第二閘極間形成開口；清洗開口；以第一材料轟擊開口之底部，從而於第一材料及接觸區域之頂表面間引發化學反應；於開口中沉積金屬層；於金屬層上沉積蓋層；於接觸區域之頂表面生成金屬矽化物；以及於生成金屬矽化物後，於開口中沉積金屬栓塞。
如本發明一實施例所述之半導體裝置，更包括一金屬層，介於該金屬矽化物及該蓋層間，該金屬層包括該第一金屬。
如本發明一實施例所述之半導體裝置，其中該金屬層包括具有一第二濃度之該第二材料。
如本發明一實施例所述之半導體裝置，其中該金屬矽化物區域係形成於一鰭式場效電晶體之一源極/汲極區中。
如本發明一實施例所述之半導體裝置，其中該接觸栓塞開口之一側壁與一閘極堆疊之一第一閘極間隔物接觸。
如本發明一實施例所述之半導體裝置，其中該第一閘極間隔物比該閘極堆疊之一第二閘極間隔物薄，該第二閘極間隔物係與該閘極堆疊之閘極相對。
如本發明一實施例所述之半導體裝置，其中該金屬矽化物區域比該接觸栓塞開口之一底部寬。
如本發明一實施例所述之半導體裝置，其中該接觸栓塞之一最頂表面與一相鄰閘極堆疊之一最頂表面大抵共面。
如本發明另一實施例所述之半導體裝置，更包括一金屬層，介於該蓋層及該金屬矽化物之間，該金屬層包括該第一金屬材料。
如本發明另一實施例所述之半導體裝置，其中該第一閘極結構之該第一閘極間隔物比該第二閘極結構之該第二閘極間隔物更垂直。
如本發明另一實施例所述之半導體裝置，其中於該金屬層及該金屬矽化物層之一界面有氯或氟。
如本發明另一實施例所述之半導體裝置，其中該第一閘極結構之該第一閘極間隔物較該第二閘極結構之該第二閘極間隔物薄。
如本發明又一實施例所述之半導體裝置形成方法，更包括平坦化該金屬栓塞，以使該金屬栓塞之一最頂表面與該第一閘極之一最頂表面及該第二閘極之一最頂表面大抵共面。
如本發明又一實施例所述之半導體裝置形成方法，其中該金屬矽化物比該開口之一底部寬度寬。
如本發明又一實施例所述之半導體裝置形成方法，其中該清洗及該轟擊係同時進行。
如本發明又一實施例所述之半導體裝置形成方法，其中該第一材料包括氟、氯或其組合。
如本發明又一實施例所述之半導體裝置形成方法，其中生成該金屬矽化物係由一快速熱退火進行。
如本發明又一實施例所述之半導體裝置形成方 法，其中該金屬矽化物之深度大於約6nm。
上述內容概述許多實施例的特徵，因此任何所屬技術領域中具有通常知識者，可更加理解本發明之各面向。任何所屬技術領域中具有通常知識者，可能無困難地以本發明為基礎，設計或修改其他製程及結構，以達到與本發明實施例相同的目的及/或得到相同的優點。任何所屬技術領域中具有通常知識者也應了解，在不脫離本發明之精神和範圍內做不同改變、代替及修改，如此等效的創造並沒有超出本發明的精神及範圍。

Claims (1)

  1. 一種半導體裝置，包括：一金屬矽化物區域，形成於一半導體材料中，該金屬矽化物區域包括一第一材料及一第二材料，該第一材料包括一金屬，該第二材料包括氯、氟或其組合，該金屬矽化物區域之一最上部有具有一第一濃度之該第二材料；一蓋層，於該金屬矽化物區域及一接觸栓塞開口之一側壁上；以及一接觸栓塞，形成於該蓋層之上，填充該接觸栓塞開口。
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CN108122980B (zh) 2023-01-06
CN108122980A (zh) 2018-06-05
US20180151679A1 (en) 2018-05-31
US20200119152A1 (en) 2020-04-16
US10510851B2 (en) 2019-12-17

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