JP5431752B2 - 半導体集積回路装置の製造方法 - Google Patents
半導体集積回路装置の製造方法 Download PDFInfo
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- JP5431752B2 JP5431752B2 JP2009051667A JP2009051667A JP5431752B2 JP 5431752 B2 JP5431752 B2 JP 5431752B2 JP 2009051667 A JP2009051667 A JP 2009051667A JP 2009051667 A JP2009051667 A JP 2009051667A JP 5431752 B2 JP5431752 B2 JP 5431752B2
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- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Description
先ず、本願において開示される発明の代表的な実施の形態について概要を説明する。
(a)半導体ウエハのデバイス面上にエッチ・ストップ絶縁膜を介して、プリ・メタル絶縁膜を形成する工程;
(b)前記プリ・メタル絶縁膜および前記エッチ・ストップ絶縁膜を貫通するコンタクト・ホールを開口する工程;
(c)前記コンタクト・ホールの底のニッケル系メタル・シリサイド膜の上面に対して、窒素水素間結合を有するガスを主要なガス成分の一つとして含む第1の非プラズマ還元性気相雰囲気中で、熱処理を実行する工程;
(d)前記工程(c)の後、前記プリ・メタル絶縁膜の上面および前記コンタクト・ホールの内面に、チタン系バリア・メタル膜を形成する工程;
(e)前記プリ・メタル絶縁膜の上面および前記コンタクト・ホールの前記内面の前記チタン系バリア・メタル膜上に、プラグ・メタル層を形成する工程;
(f)前記コンタクト・ホール外の前記チタン系バリア・メタル膜および前記プラグ・メタル層を除去する工程。
(d1)前記工程(c)の後、前記プリ・メタル絶縁膜の上面および前記コンタクト・ホールの内面に、チタン系メタル膜を形成する工程;
(d2)前記チタン系メタル膜の上面に対して、プラズマ窒化処理を実行することにより、前記チタン系メタル膜の前記上面に窒化チタン膜を形成する工程。
(d3)前記下位工程(d1)の後であって前記下位工程(d2)の前に、前記チタン系メタル膜を介して、前記ニッケル系メタル・シリサイド膜の前記上面に対して、窒素水素間結合を有するガスを主要なガス成分の一つとして含む第2の非プラズマ還元性気相雰囲気中で、熱処理を実行する工程。
(d4)前記下位工程(d1)の後であって前記下位工程(d3)の前に、前記半導体ウエハの前記デバイス面側に対して、水素ガスを主要な成分とする気相プラズマ処理を実行する工程。
(d5)前記工程(c)の後であって前記下位工程(d1)の前に、プラズマを印加しない状態で、前記下位工程(d1)と、ほぼ同一の処理を実行する工程。
(d5)前記下位工程(d2)の後に、前記チタン系メタル膜および前記窒化チタン膜を介して、前記ニッケル系メタル・シリサイド膜の前記上面に対して、窒素水素間結合を有するガスを主要なガス成分の一つとして含む第3の非プラズマ還元性気相雰囲気中で、熱処理を実行する工程。
1.本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクションに分けて記載する場合もあるが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しを省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
実施の形態について更に詳述する。各図中において、同一または同様の部分は同一または類似の記号または参照番号で示し、説明は原則として繰り返さない。
また、本実施の形態では、本発明者によってなされた発明をその背景となった利用分野であるSRAM(Static Random Access Memory)のメモリセルに適用した場合について説明する。
このセクションでは、セクション1に続き、本願の一実施の形態の半導体集積回路装置の製造方法におけるウエハプロセスの主要部であるコンタクト・ホール埋め込み工程100(図19)およびそれに使用する成膜装置等を中心に説明する。
この時、還元反応により生成された生成物((NH4)2SiF6)がコンタクト・ホールC1、ならびに第1及び第2配線溝HM1,HM2の内部を含む半導体ウエハSWの主面上に残留する。
この後、上層の配線、例えば第0、第1及び第2層配線が形成される。引き続き、これら配線の形成工程について説明する。
このように、本実施の形態によれば、コンタクト・ホールC1、ならびに第1及び第2配線溝HM1,HM2の内部にバリア・メタル膜21を形成する前に行うドライ・クリーニング処置(図10でのチャンバ54での処理)により、コンタクト・ホールC1、ならびに第1及び第2配線溝HM1,HM2の底面及び側面に化学量論的組成から僅かにずれた生成物が残留するが、この生成物はドライ・クリーニング処理の後に行う150℃よりも高い温度の熱処理により除去されるので、コンタクト・ホールC1、ならびに第1及び第2配線溝HM1,HM2の底面におけるニッケル・シリサイド層14とバリア・メタル膜21との接触抵抗のばらつきを低減することができ、またコンタクト・ホールC1、ならびに第1及び第2配線溝HM1,HM2の側面におけるバリア・メタル膜21の剥がれを防ぐことができる。
(1)図20の「長時間ポスト・プラズマ」のデータより、長時間ポスト・プラズマ窒化処理は、ケルビン抵抗を上昇させる。界面の窒化による電気抵抗の上昇と考えられる。このことは、程度は小さいが、図21からも読み取れる。
(2)「短時間ポスト・プラズマ」のデータで、1.5σ以上で非導通となっている。これは、ニッケル。シリサイド膜の上面近傍における酸化シリコン膜の除去が十分に行われていないことを示す。
(3)従って、コンタクト部分の抵抗低減のためには、プリ・ソーク処理が最も有効であり、これに加えて、ポスト・ソーク処理およびポスト・プラズマ窒化処理が有効である。
以上本発明者によってなされた発明を実施形態に基づいて具体的に説明したが、本願発明はそれに限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは言うまでもない。
1a 基板(またはウエハの基板部)
1b エピタキシャル層
1d 半導体基板(またはウエハ)のデバイス面
1h 半導体基板(またはウエハ)の裏面
2 素子分離
4 p型ウェル
5 n型ウェル
6 ゲート絶縁膜
7 n−型半導体領域
8 p−型半導体領域
9 酸化シリコン膜
10 サイド・ウォール
12 n+型半導体領域
13 p+型半導体領域
14 ニッケル・シリサイド層
15 窒化シリコン膜
16 PSG膜
17 酸化シリコン膜
21 バリア・メタル膜
21a チタン膜(熱反応Ti膜)
21b チタン膜(プラズマ反応Ti膜)
21c 窒化チタン膜(窒素リッチTiN膜)
22 タングステン膜(プラグ・メタル層)
22a タングステン核膜
22b ブランケット・タングステン膜
23a,23b 局所配線
24 酸化シリコン膜
25 バリア・メタル膜
26 酸化シリコン膜
50 成膜装置
51 搬送室
52 ゲートバルブ
53 ロードロック室
54 ドライ洗浄チャンバ
55 洗浄後熱処理チャンバ
56 チタンCVDチャンバ
57 タングステンCVDチャンバ
58 ウエハ搬入出室
59 フープ
60 ポート
61,62 搬送用ロボット
63 高周波電源
64 マス・フロー・コントローラ
65 ガス排気口
66 下部電極
67 上部電極
68 ガス導入口
100 コンタクト・ホール埋め込み工程
101 チタン成膜前還元熱処理
102 下地チタン膜形成
103 主チタンCVD膜形成
104 ハロゲン除去プラズマ処理
105 チタン成膜後還元熱処理
106 チタン・プラズマ窒化処理
107 チタン窒化後還元熱処理
108 下地タングステン膜形成
109 主タングステンCVD膜形成
A 記憶ノード
An1,An2,Ap1,Ap2 活性領域
B 記憶ノード
C1 コンタクト・ホール
C2,C3 ビア・ホール
DL,/DL データ線
Dr1,Dr2 駆動用MISFET
G ゲート電極
GM1,GM2 引き出し部
HM1,HM2 配線溝
INV1,INV2 CMOSインバータ
Ld1,Ld2 負荷用MISFET
M0 第0層配線
M1 第1層配線
M2 第2層配線
MC メモリセル
QnL nMISFET
QpL pMISFET
P1,P2 プラグ
SW 半導体ウエハ
Tr1,Tr2 転送用MISFET
Vcc 電源電圧
Vss 基準電圧
WL ワード線
Claims (1)
- 以下の工程を含む半導体集積回路装置の製造方法:
(a)半導体ウエハのデバイス面上にエッチ・ストップ絶縁膜を介して、プリ・メタル絶縁膜を形成する工程;
(b)前記プリ・メタル絶縁膜および前記エッチ・ストップ絶縁膜を貫通するコンタクト・ホールを開口する工程;
(c)前記コンタクト・ホールの底のニッケル系メタル・シリサイド膜の上面に対して、窒素水素間結合を有するガスを主要なガス成分の一つとして含む第1の非プラズマ還元性気相雰囲気中で、熱処理を実行する工程;
(d)前記工程(c)の後、前記プリ・メタル絶縁膜の上面および前記コンタクト・ホールの内面に、チタン系バリア・メタル膜を形成する工程;
(e)前記プリ・メタル絶縁膜の上面および前記コンタクト・ホールの前記内面の前記チタン系バリア・メタル膜上に、プラグ・メタル層を形成する工程;
(f)前記コンタクト・ホール外の前記チタン系バリア・メタル膜および前記プラグ・メタル層を除去する工程、
ここで、前記工程(c)は、前記半導体ウエハをウエハ・ステージ上に置いた状態で行われ、その設定温度は、摂氏350度から550度であり、前記第1の非プラズマ還元性気相雰囲気は、酸素ガス、ハロゲン・ガス、および有機ガスのいずれのガスも実質的に含まないものである。
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US9431509B2 (en) * | 2012-12-31 | 2016-08-30 | Texas Instruments Incorporated | High-K metal gate |
US9887160B2 (en) * | 2015-09-24 | 2018-02-06 | International Business Machines Corporation | Multiple pre-clean processes for interconnect fabrication |
US10510851B2 (en) * | 2016-11-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low resistance contact method and structure |
US10304728B2 (en) * | 2017-05-01 | 2019-05-28 | Advanced Micro Devices, Inc. | Double spacer immersion lithography triple patterning flow and method |
US10714334B2 (en) * | 2017-11-28 | 2020-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Conductive feature formation and structure |
US11195923B2 (en) * | 2018-12-21 | 2021-12-07 | Applied Materials, Inc. | Method of fabricating a semiconductor device having reduced contact resistance |
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