JP4653949B2 - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
- Publication number
- JP4653949B2 JP4653949B2 JP2003411509A JP2003411509A JP4653949B2 JP 4653949 B2 JP4653949 B2 JP 4653949B2 JP 2003411509 A JP2003411509 A JP 2003411509A JP 2003411509 A JP2003411509 A JP 2003411509A JP 4653949 B2 JP4653949 B2 JP 4653949B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- gate electrode
- refractory metal
- semiconductor region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 284
- 238000004519 manufacturing process Methods 0.000 title claims description 82
- 238000000034 method Methods 0.000 claims description 170
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 129
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 129
- 238000004140 cleaning Methods 0.000 claims description 67
- 239000003870 refractory metal Substances 0.000 claims description 50
- 239000000758 substrate Substances 0.000 claims description 50
- 229910021332 silicide Inorganic materials 0.000 claims description 42
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 42
- 239000007789 gas Substances 0.000 claims description 35
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 33
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 26
- 239000012535 impurity Substances 0.000 claims description 22
- 229910000077 silane Inorganic materials 0.000 claims description 22
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 18
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 16
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 14
- 238000009832 plasma treatment Methods 0.000 claims description 13
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 238000000992 sputter etching Methods 0.000 claims description 12
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 7
- 229910021529 ammonia Inorganic materials 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 82
- 229910019001 CoSi Inorganic materials 0.000 description 63
- 238000000137 annealing Methods 0.000 description 35
- 239000010941 cobalt Substances 0.000 description 26
- 229910017052 cobalt Inorganic materials 0.000 description 26
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 26
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 21
- 230000002159 abnormal effect Effects 0.000 description 21
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 17
- 239000010703 silicon Substances 0.000 description 17
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 238000005530 etching Methods 0.000 description 12
- 238000006243 chemical reaction Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 239000004020 conductor Substances 0.000 description 6
- 239000007788 liquid Substances 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 238000011109 contamination Methods 0.000 description 5
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 239000012495 reaction gas Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本実施の形態の半導体装置およびその製造工程を図面を参照して説明する。図1は、本発明の一実施の形態である半導体装置、例えばCMISFET(Complementary Metal Insulator Semiconductor Field Effect Transistor)、の製造工程中の要部断面図である。
図22は、本発明の他の実施の形態である半導体装置の製造工程を示す製造プロセスフロー図である。ステップS4の第2のアニール処理(第2の熱処理)工程までは上記実施の形態1とほぼ同様であるので、ここではその説明は省略し、ステップS4の第2のアニール処理工程に続く製造工程について説明する。
図23は、本発明の他の実施の形態である半導体装置の製造工程を示す製造プロセスフロー図である。ステップS4の第2のアニール処理(第2の熱処理)工程までは上記実施の形態1とほぼ同様であるので、ここではその説明は省略し、ステップS4の第2のアニール処理工程に続く製造工程について説明する。
図24は、本発明の他の実施の形態である半導体装置の製造工程を示す製造プロセスフロー図である。図25および図26は、本発明の他の実施の形態である半導体装置の製造工程中の要部断面図である。ステップS4の第2のアニール処理(第2の熱処理)工程までは上記実施の形態1とほぼ同様であるので、ここではその説明は省略し、ステップS4の第2のアニール処理工程に続く製造工程について説明する。
2 素子分離領域
3 p型ウエル
4 n型ウエル
5 ゲート絶縁膜
6 導体膜(多結晶シリコン膜)
6a ゲート電極
6b ゲート電極
7a n-型半導体領域
7b n+型半導体領域
8a p-型半導体領域
8b p+型半導体領域
9 サイドウォール
10 nチャネル型MISFET
11 pチャネル型MISFET
12 コバルト膜
13 窒化チタン膜
14 CoSi層
15 CoSi2層
16 窒化シリコン膜(絶縁膜)
17 絶縁膜
18 コンタクトホール
21 プラグ
21a 窒化チタン膜
22 配線
23 絶縁膜
30 シリコン領域
31 核
41 絶縁膜
Claims (20)
- 半導体装置の製造方法であって、
(a)半導体基板を準備する工程、
(b)前記半導体基板上にゲート絶縁膜を形成する工程、
(c)前記ゲート絶縁膜上にゲート電極を形成する工程、
(d)前記半導体基板に不純物を導入して、ソースまたはドレインとしての半導体領域を形成する工程、
(e)前記ゲート電極および前記半導体領域上を含む前記半導体基板上に高融点金属膜を形成する工程、
(f)第1の熱処理を行って前記高融点金属膜と前記ゲート電極または前記半導体領域とを反応させて高融点金属シリサイド層を形成する工程、
(g)前記(f)工程後に、前記高融点金属膜を除去し、前記ゲート電極または前記半導体領域上に前記高融点金属シリサイド層を残す工程、
(h)前記(g)工程後に、第2の熱処理を行って前記高融点金属シリサイド層と前記ゲート電極または前記半導体領域とを反応させる工程、
(i)前記(h)工程後に、ウェット洗浄処理を行う工程、
(j)前記(i)工程後に、前記高融点金属シリサイド層上を含む前記半導体基板上に窒化シリコン膜を形成する工程、
を有し、
前記(i)工程では、前記ウェット洗浄処理としてHPM洗浄処理を行い、
前記(j)工程では、低圧CVD法を用いて前記窒化シリコン膜を形成することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記HPM洗浄処理は、少なくとも塩酸および過酸化水素水を含む溶液で行われることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(g)工程では、枚葉式の洗浄装置によるウェット洗浄処理を行うことを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記ゲート絶縁膜、前記ゲート電極および前記半導体領域によりnチャネル型MISFETが形成されることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(j)工程では、シラン系のガスが用いられることを特徴とする半導体装置の製造方法。 - 半導体装置の製造方法であって、
(a)半導体基板を準備する工程、
(b)前記半導体基板上にゲート絶縁膜を形成する工程、
(c)前記ゲート絶縁膜上にゲート電極を形成する工程、
(d)前記半導体基板に不純物を導入して、ソースまたはドレインとしての半導体領域を形成する工程、
(e)前記ゲート電極および前記半導体領域上を含む前記半導体基板上に高融点金属膜を形成する工程、
(f)第1の熱処理を行って前記高融点金属膜と前記ゲート電極または前記半導体領域とを反応させて高融点金属シリサイド層を形成する工程、
(g)前記(f)工程後に、前記高融点金属膜を除去し、前記ゲート電極または前記半導体領域上に前記高融点金属シリサイド層を残す工程、
(h)前記(g)工程後に、第2の熱処理を行って前記高融点金属シリサイド層と前記ゲート電極または前記半導体領域とを反応させる工程、
(i)前記(h)工程後に、プラズマ処理を行う工程、
(j)前記(i)工程後に、前記高融点金属シリサイド層上を含む前記半導体基板上に窒化シリコン膜を形成する工程、
を有し、
前記(j)工程では、低圧CVD法を用いて前記窒化シリコン膜を形成することを特徴とする半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記(i)工程では、アンモニアプラズマ処理を行うことを特徴とする半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記ゲート絶縁膜、前記ゲート電極および前記半導体領域によりnチャネル型MISFETが形成されることを特徴とする半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記(j)工程では、シラン系のガスが用いられることを特徴とする半導体装置の製造方法。 - 半導体装置の製造方法であって、
(a)半導体基板を準備する工程、
(b)前記半導体基板上にゲート絶縁膜を形成する工程、
(c)前記ゲート絶縁膜上にゲート電極を形成する工程、
(d)前記半導体基板に不純物を導入して、ソースまたはドレインとしての半導体領域を形成する工程、
(e)前記ゲート電極および前記半導体領域上を含む前記半導体基板上に高融点金属膜を形成する工程、
(f)第1の熱処理を行って前記高融点金属膜と前記ゲート電極または前記半導体領域とを反応させて高融点金属シリサイド層を形成する工程、
(g)前記(f)工程後に、前記高融点金属膜を除去し、前記ゲート電極または前記半導体領域上に前記高融点金属シリサイド層を残す工程、
(h)前記(g)工程後に、第2の熱処理を行って前記高融点金属シリサイド層と前記ゲート電極または前記半導体領域とを反応させる工程、
(i)前記(h)工程後に、スパッタエッチング処理を行う工程、
(j)前記(i)工程後に、前記高融点金属シリサイド層上を含む前記半導体基板上に窒化シリコン膜を形成する工程、
を有し、
前記(j)工程では、低圧CVD法を用いて前記窒化シリコン膜を形成することを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記(i)工程では、アルゴンを用いたスパッタエッチング処理を行うことを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記ゲート絶縁膜、前記ゲート電極および前記半導体領域によりnチャネル型MISFETが形成されることを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、
前記(j)工程では、シラン系のガスが用いられることを特徴とする半導体装置の製造方法。 - (a)半導体基板を準備する工程、
(b)前記半導体基板上にゲート絶縁膜を形成する工程、
(c)前記ゲート絶縁膜上にゲート電極を形成する工程、
(d)前記半導体基板に不純物を導入して、ソースまたはドレインとしての半導体領域を形成する工程、
(e)前記ゲート電極および前記半導体領域上を含む前記半導体基板上に高融点金属膜を形成する工程、
(f)第1の熱処理を行って前記高融点金属膜と前記ゲート電極または前記半導体領域とを反応させて高融点金属シリサイド層を形成する工程、
(g)前記(f)工程後に、前記高融点金属膜を除去し、前記ゲート電極または前記半導体領域上に前記高融点金属シリサイド層を残す工程、
(h)前記(g)工程後に、第2の熱処理を行って前記高融点金属シリサイド層と前記ゲート電極または前記半導体領域とを反応させる工程、
(i)前記(h)工程後に、前記高融点金属シリサイド層上を含む前記半導体基板上に窒化シリコンまたは酸化シリコンからなる第1絶縁膜を形成する工程、
(j)前記(i)工程後に、前記第1絶縁膜上に窒化シリコンからなる第2絶縁膜を形成する工程、
を有し、
前記(i)工程で形成される前記第1絶縁膜は、前記(j)工程で形成される前記第2絶縁膜よりも、シラン系のガスが少ない条件で形成され、
前記(j)工程では、低圧CVD法を用いて前記第2絶縁膜を形成することを特徴とする半導体装置の製造方法。 - 請求項14記載の半導体装置の製造方法において、
前記(i)工程では、プラズマCVD法により窒化シリコン膜を形成すること、プラズマCVD法により酸化シリコン膜を形成することまたはシラン系ガスを用いないCVD法により酸化シリコン膜を形成することによって前記第1絶縁膜を形成し、
前記(j)工程では、シラン系ガスを用いたCVD法により前記第2絶縁膜を形成することを特徴とする半導体装置の製造方法。 - 請求項14記載の半導体装置の製造方法において、
前記ゲート絶縁膜、前記ゲート電極および前記半導体領域によりnチャネル型MISFETが形成されることを特徴とする半導体装置の製造方法。 - 半導体基板と、
前記半導体基板上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、
前記半導体基板に形成され、ソースまたはドレインとして機能する半導体領域と、
前記ゲート電極または前記半導体領域上に形成された高融点金属シリサイド層と、
前記高融点金属シリサイド層上を含む前記半導体基板上に前記ゲート電極を覆うように形成され、かつプラズマCVD法により形成された第1絶縁膜と、
前記第1絶縁膜上に低圧CVD法を用いて形成された窒化シリコンからなる第2絶縁膜と、
を有し、
前記ゲート絶縁膜、前記ゲート電極および前記半導体領域によりnチャネル型MISFETが形成され、
前記第2絶縁膜は、前記第1絶縁膜よりも大きな引張り応力を、前記nチャネル型MISFETのチャネル領域に発生させる膜であることを特徴とする半導体装置。 - 請求項17記載の半導体装置において、
前記第1絶縁膜の膜厚は前記第2絶縁膜の膜厚よりも薄いことを特徴とする半導体装置。 - 請求項17記載の半導体装置において、
前記第1絶縁膜は、プラズマCVD法により形成された窒化シリコン膜またはプラズマCVD法により形成された酸化シリコン膜からなることを特徴とする半導体装置。 - 半導体基板と、
前記半導体基板上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、
前記半導体基板に形成され、ソースまたはドレインとして機能する半導体領域と、
前記ゲート電極または前記半導体領域上に形成された高融点金属シリサイド層と、
前記高融点金属シリサイド層上を含む前記半導体基板上に前記ゲート電極を覆うように形成され、かつシラン系ガスを用いないCVD法により形成された酸化シリコン膜からなる第1絶縁膜と、
前記第1絶縁膜上に低圧CVD法を用いて形成された窒化シリコンからなる第2絶縁膜と、
を有し、
前記ゲート絶縁膜、前記ゲート電極および前記半導体領域によりnチャネル型MISFETが形成され、
前記第2絶縁膜は、前記第1絶縁膜よりも大きな引張り応力を、前記nチャネル型MISFETのチャネル領域に発生させる膜であることを特徴とする半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003411509A JP4653949B2 (ja) | 2003-12-10 | 2003-12-10 | 半導体装置の製造方法および半導体装置 |
US11/008,276 US7348230B2 (en) | 2003-12-10 | 2004-12-10 | Manufacturing method of semiconductor device |
US12/028,593 US7666728B2 (en) | 2003-12-10 | 2008-02-08 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003411509A JP4653949B2 (ja) | 2003-12-10 | 2003-12-10 | 半導体装置の製造方法および半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005175121A JP2005175121A (ja) | 2005-06-30 |
JP4653949B2 true JP4653949B2 (ja) | 2011-03-16 |
Family
ID=34708680
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003411509A Expired - Lifetime JP4653949B2 (ja) | 2003-12-10 | 2003-12-10 | 半導体装置の製造方法および半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (2) | US7348230B2 (ja) |
JP (1) | JP4653949B2 (ja) |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7172792B2 (en) * | 2002-12-20 | 2007-02-06 | Applied Materials, Inc. | Method for forming a high quality low temperature silicon nitride film |
US7972663B2 (en) * | 2002-12-20 | 2011-07-05 | Applied Materials, Inc. | Method and apparatus for forming a high quality low temperature silicon nitride layer |
US7488690B2 (en) * | 2004-07-06 | 2009-02-10 | Applied Materials, Inc. | Silicon nitride film with stress control |
JP2006173479A (ja) * | 2004-12-17 | 2006-06-29 | Sharp Corp | 半導体装置の製造方法 |
JP2007067118A (ja) * | 2005-08-30 | 2007-03-15 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4787593B2 (ja) * | 2005-10-14 | 2011-10-05 | パナソニック株式会社 | 半導体装置 |
JP4829591B2 (ja) * | 2005-10-25 | 2011-12-07 | パナソニック株式会社 | 半導体装置及びその製造方法 |
JP2007141903A (ja) * | 2005-11-15 | 2007-06-07 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US7332447B2 (en) * | 2005-11-24 | 2008-02-19 | United Microelectronics Corp. | Method of forming a contact |
US20100224941A1 (en) * | 2006-06-08 | 2010-09-09 | Nec Corporation | Semiconductor device |
US20080009134A1 (en) * | 2006-07-06 | 2008-01-10 | Tsung-Yu Hung | Method for fabricating metal silicide |
JP2008053532A (ja) * | 2006-08-25 | 2008-03-06 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2008192686A (ja) * | 2007-02-01 | 2008-08-21 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US7482282B2 (en) * | 2007-03-26 | 2009-01-27 | International Business Machines Corporation | Use of dilute hydrochloric acid in advanced interconnect contact clean in nickel semiconductor technologies |
US7700480B2 (en) * | 2007-04-27 | 2010-04-20 | Micron Technology, Inc. | Methods of titanium deposition |
JP5411456B2 (ja) * | 2007-06-07 | 2014-02-12 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2009038103A (ja) * | 2007-07-31 | 2009-02-19 | Fujitsu Microelectronics Ltd | 半導体装置の製造方法と半導体装置 |
US7974505B2 (en) | 2007-10-17 | 2011-07-05 | Bae Systems Information And Electronic Systems Integration Inc. | Method for fabricating selectively coupled optical waveguides on a substrate |
WO2009051903A1 (en) | 2007-10-18 | 2009-04-23 | Bae Systems Information And Electronic Systems Integration Inc. | Method for manufacturing multiple layers of waveguides |
US7736934B2 (en) | 2007-10-19 | 2010-06-15 | Bae Systems Information And Electronic Systems Integration Inc. | Method for manufacturing vertical germanium detectors |
WO2009055145A1 (en) * | 2007-10-24 | 2009-04-30 | Bae Systems Information And Electronic Systems Integration Inc. | Method for fabricating a heater capable of adjusting refractive index of an optical waveguide |
WO2009055778A1 (en) | 2007-10-25 | 2009-04-30 | Bae Systems Information And Electronic Systems Integration Inc. | Method for manufacturing lateral germanium detectors |
US7811844B2 (en) | 2007-10-26 | 2010-10-12 | Bae Systems Information And Electronic Systems Integration Inc. | Method for fabricating electronic and photonic devices on a semiconductor substrate |
US8031343B2 (en) * | 2007-10-29 | 2011-10-04 | Bae Systems Information And Electronic Systems Integration Inc. | High-index contrast waveguide optical gyroscope having segmented paths |
WO2009058470A1 (en) * | 2007-10-30 | 2009-05-07 | Bae Systems Information And Electronic Systems Integration Inc. | Method for fabricating butt-coupled electro-absorptive modulators |
WO2009058580A1 (en) * | 2007-10-31 | 2009-05-07 | Bae Systems Information And Electronic Systems Integration Inc. | High-injection heterojunction bipolar transistor |
JP2009147199A (ja) * | 2007-12-17 | 2009-07-02 | Renesas Technology Corp | 半導体装置および半導体装置の製造方法 |
US7987066B2 (en) * | 2008-08-29 | 2011-07-26 | Bae Systems Information And Electronic Systems Integration Inc. | Components and configurations for test and valuation of integrated optical busses |
US7853101B2 (en) * | 2008-08-29 | 2010-12-14 | Bae Systems Information And Electronic Systems Integration Inc. | Bi-rate adaptive optical transfer engine |
US8148265B2 (en) * | 2008-08-29 | 2012-04-03 | Bae Systems Information And Electronic Systems Integration Inc. | Two-step hardmask fabrication methodology for silicon waveguides |
US7693354B2 (en) * | 2008-08-29 | 2010-04-06 | Bae Systems Information And Electronic Systems Integration Inc. | Salicide structures for heat-influenced semiconductor applications |
US8288290B2 (en) * | 2008-08-29 | 2012-10-16 | Bae Systems Information And Electronic Systems Integration Inc. | Integration CMOS compatible of micro/nano optical gain materials |
US7715663B2 (en) * | 2008-08-29 | 2010-05-11 | Bae Systems Information And Electronic Systems Integration Inc. | Integrated optical latch |
JP2010080798A (ja) * | 2008-09-29 | 2010-04-08 | Renesas Technology Corp | 半導体集積回路装置および半導体集積回路装置の製造方法 |
JP5358165B2 (ja) * | 2008-11-26 | 2013-12-04 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
US7847353B2 (en) * | 2008-12-05 | 2010-12-07 | Bae Systems Information And Electronic Systems Integration Inc. | Multi-thickness semiconductor with fully depleted devices and photonic integration |
WO2010140244A1 (ja) * | 2009-06-05 | 2010-12-09 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US9305779B2 (en) * | 2009-08-11 | 2016-04-05 | Bae Systems Information And Electronic Systems Integration Inc. | Method for growing germanium epitaxial films |
US8232607B2 (en) | 2010-11-23 | 2012-07-31 | International Business Machines Corporation | Borderless contact for replacement gate employing selective deposition |
US8797303B2 (en) * | 2011-03-21 | 2014-08-05 | Qualcomm Mems Technologies, Inc. | Amorphous oxide semiconductor thin film transistor fabrication method |
US9379254B2 (en) | 2011-11-18 | 2016-06-28 | Qualcomm Mems Technologies, Inc. | Amorphous oxide semiconductor thin film transistor fabrication method |
JP2013077828A (ja) * | 2012-12-05 | 2013-04-25 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP6081228B2 (ja) * | 2013-02-28 | 2017-02-15 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
CN103489825B (zh) * | 2013-09-22 | 2016-01-20 | 上海华力微电子有限公司 | 解决氮化硅和镍硅化物界面剥落问题的工艺方法 |
CN110391299B (zh) * | 2018-04-23 | 2023-07-14 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002198368A (ja) * | 2000-12-26 | 2002-07-12 | Nec Corp | 半導体装置の製造方法 |
JP2003273240A (ja) * | 2002-03-19 | 2003-09-26 | Hitachi Ltd | 半導体装置及びその製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06333943A (ja) * | 1993-05-18 | 1994-12-02 | Oki Electric Ind Co Ltd | Mos半導体装置の製造方法 |
JPH07153939A (ja) * | 1993-11-29 | 1995-06-16 | Oki Electric Ind Co Ltd | 半導体素子およびその製造方法 |
EP0724287A3 (en) * | 1995-01-30 | 1999-04-07 | Nec Corporation | Method for fabricating semiconductor device having titanium silicide film |
JP2785734B2 (ja) * | 1995-02-28 | 1998-08-13 | 日本電気株式会社 | 半導体装置の製造方法 |
JPH10312975A (ja) * | 1997-05-14 | 1998-11-24 | Toshiba Corp | 半導体装置及びその製造方法 |
US6074960A (en) * | 1997-08-20 | 2000-06-13 | Micron Technology, Inc. | Method and composition for selectively etching against cobalt silicide |
JP3209164B2 (ja) * | 1997-10-07 | 2001-09-17 | 日本電気株式会社 | 半導体装置の製造方法 |
US6235630B1 (en) | 1998-08-19 | 2001-05-22 | Micron Technology, Inc. | Silicide pattern structures and methods of fabricating the same |
US6335294B1 (en) * | 1999-04-22 | 2002-01-01 | International Business Machines Corporation | Wet cleans for cobalt disilicide processing |
JP2002075905A (ja) * | 2000-08-29 | 2002-03-15 | Nec Corp | 半導体装置の製造方法 |
US20050116360A1 (en) * | 2003-12-01 | 2005-06-02 | Chien-Chao Huang | Complementary field-effect transistors and methods of manufacture |
US7332447B2 (en) * | 2005-11-24 | 2008-02-19 | United Microelectronics Corp. | Method of forming a contact |
-
2003
- 2003-12-10 JP JP2003411509A patent/JP4653949B2/ja not_active Expired - Lifetime
-
2004
- 2004-12-10 US US11/008,276 patent/US7348230B2/en active Active
-
2008
- 2008-02-08 US US12/028,593 patent/US7666728B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002198368A (ja) * | 2000-12-26 | 2002-07-12 | Nec Corp | 半導体装置の製造方法 |
JP2003273240A (ja) * | 2002-03-19 | 2003-09-26 | Hitachi Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US7348230B2 (en) | 2008-03-25 |
US20050145897A1 (en) | 2005-07-07 |
US20080142901A1 (en) | 2008-06-19 |
US7666728B2 (en) | 2010-02-23 |
JP2005175121A (ja) | 2005-06-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4653949B2 (ja) | 半導体装置の製造方法および半導体装置 | |
US7598171B2 (en) | Method of manufacturing a semiconductor device | |
JP4738178B2 (ja) | 半導体装置の製造方法 | |
US8222133B2 (en) | Manufacturing method of semiconductor device | |
JP2007207837A (ja) | 半導体装置および半導体装置の製造方法 | |
US6190976B1 (en) | Fabrication method of semiconductor device using selective epitaxial growth | |
TWI798328B (zh) | 半導體結構與其製作方法 | |
JP2009088069A (ja) | 半導体装置及びその製造方法 | |
US20090289285A1 (en) | Semiconductor device and method of fabricating the same | |
US7777266B2 (en) | Conductive line comprising a capping layer | |
KR100603588B1 (ko) | 낮은 콘택 저항을 갖는 반도체 소자 및 그 제조 방법 | |
JP2004134687A (ja) | 半導体装置及びその製造方法 | |
US20090075477A1 (en) | Method of manufacturing semiconductor device | |
JP2007027348A (ja) | 半導体装置及びその製造方法 | |
JP3492973B2 (ja) | 半導体装置の製造方法 | |
JPWO2008117430A1 (ja) | 半導体装置の製造方法、半導体装置 | |
JP2007234667A (ja) | 半導体装置の製造方法 | |
US7670952B2 (en) | Method of manufacturing metal silicide contacts | |
US20010045606A1 (en) | Semiconductor device and method for fabricating the same | |
KR100638422B1 (ko) | 에피택셜 공정을 이용한 반도체 소자의 콘택홀 충진 방법 | |
KR100432789B1 (ko) | 반도체 소자의 제조 방법 | |
KR100853459B1 (ko) | 반도체소자의 콘택저항 감소 방법 | |
CN113284798A (zh) | 半导体器件的制备方法 | |
JP2005203647A (ja) | 半導体装置の製造方法および半導体装置 | |
KR20060000585A (ko) | 반도체 소자의 콘택플러그 형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20061208 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080630 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20100528 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100831 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101027 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20101124 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20101220 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4653949 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131224 Year of fee payment: 3 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
EXPY | Cancellation because of completion of term |