CN108122980B - 半导体装置与半导体装置形成方法 - Google Patents

半导体装置与半导体装置形成方法 Download PDF

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CN108122980B
CN108122980B CN201710600507.4A CN201710600507A CN108122980B CN 108122980 B CN108122980 B CN 108122980B CN 201710600507 A CN201710600507 A CN 201710600507A CN 108122980 B CN108122980 B CN 108122980B
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gate
metal silicide
metal
opening
region
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CN108122980A (zh
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王喻生
林钰庭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体装置，包括：金属硅化物区域，形成于半导体材料中，金属硅化物区域包括第一材料及第二材料，第一材料包括金属，第二材料包括氯、氟或其组合，金属硅化物区域的最上部有具有第一浓度的第二材料；盖层，于金属硅化物区域及接触栓塞开口的侧壁上；以及接触栓塞，形成于盖层之上，填充接触栓塞开口。

Description

半导体装置与半导体装置形成方法
技术领域
本公开涉及一种半导体装置，且特别涉及可降低鳍式场效晶体管的源极/漏极区上形成的接点电阻的一种半导体装置。
背景技术
随着对集成电路的微缩化以及集成电路速度的要求越来越高，晶体管需要有较高的驱动电流以及越来越小的尺寸，因而发展了鳍式场效晶体管(Fin Field-EffectTransistors，FinFET)。鳍式场效晶体管包括基板上方垂直的半导体鳍片。半导体鳍片用于形成源极和漏极区域，并且在源极和漏极区域之间形成沟道区。形成浅沟槽隔离(ShallowTrench Isolation，STI)区域以定义半导体鳍片。鳍式场效晶体管还包括形成于半导体鳍片的侧壁及顶表面上的栅极堆叠。虽然现有的鳍式场效晶体管装置及其制造方法通常已经足以满足其预期目的，但还没有在所有方面都完全令人满意。
由于随着技术和制造使半导体的其他方面微缩化，使得可用于产生接点(contact)的总面积也跟着微缩化，所以低电阻接点越来越重要。
发明内容
在一些实施例中，本公开公开了一种半导体装置，包括：金属硅化物区域，形成于半导体材料中，金属硅化物区域包括第一材料及第二材料，第一材料包括金属，第二材料包括氯、氟或其组合，金属硅化物区域的最上部有具有第一浓度的第二材料；盖层，于金属硅化物区域及接触栓塞开口的侧壁上；以及接触栓塞，形成于盖层之上，填充接触栓塞开口。
在另一些实施例中，本公开公开了一种半导体装置，包括：鳍式场效晶体管，具有第一栅极结构及第二栅极结构，每个第一栅极结构及第二栅极结构各自包括第一栅极间隔物及第二栅极间隔物，每个第一栅极间隔物与每个第二栅极间隔物分离；源极/漏极区，介于第一栅极结构及第二栅极结构间；接点，包括：侧壁，包括第一金属材料，第一金属材料与第一栅极的第一栅极间隔物及第二栅极的第二栅极间隔物重合；底部，包括于源极/漏极区的顶表面上的金属硅化物；栓塞，介于接点的侧壁间及接点的底部上，栓塞包括导电材料；盖层，介于栓塞及金属硅化物间；其中金属硅化物延伸至第一栅极结构的第一栅极间隔物及第二栅极结构的第二栅极间隔物下。
在又一些实施例中，本公开公开了一种半导体装置形成方法，包括：于第一栅极及第二栅极间形成开口；清洗开口；以第一材料轰击开口的底部，从而于第一材料及接触区域的顶表面间引发化学反应；于开口中沉积金属层；于金属层上沉积盖层；于接触区域的顶表面生成金属硅化物；以及于生成金属硅化物后，于开口中沉积金属栓塞。
附图说明
以下将配合所附附图详述本公开的实施例。应注意的是，依据在业界的标准做法，各种特征并未按照比例绘示且仅用以说明例示。事实上，可能任意地放大或缩小元件的尺寸，以清楚地表现出本公开的特征。
图1是鳍式场效晶体管范例的三维视图。
图2-图9是根据一些实施例绘示在不同显影阶段的鳍式场效晶体管的范例。
图10是根据一些实施例绘示的流程图。
图11是根据一些实施例绘示的源极/漏极接点的金属硅化物区域的化学指数图。
附图标记说明：
30～鳍式场效晶体管
32～基板
34～隔离区
36～鳍片
38～栅极介电质
40～栅极电极
42、43、44～源极/漏极区
100～半导体装置
102～鳍片
103a、103b～半导体鳍片材料
105a、105b、105c～源极/漏极材料
110a、110b～栅极堆叠
111a、111b～栅极介电层
115a、115b～栅极电极
119a、119b～硬掩模
119-1、123-1、127-1、131-1、229-1～顶表面
123a、123b～第一栅极间隔物
127a、127b～第二栅极间隔物
127c、127d～栅极间隔物
131～介电层
135～光致抗蚀剂
136、201、211～开口
205～预清洗工艺
207～物理轰击
215’～金属层
225～金属硅化物层
229～导电栓塞
305、310、315、320、325、330、335、340～步骤
A-A～剖面
h1～深度
w1、w2、w3～宽度
具体实施方式
以下公开许多不同的实施方法或是范例来实行所提供的标的的不同特征，以下描述具体的元件及其排列的实施例以阐述本公开。当然这些实施例仅用以例示，且不该以此限定本公开的范围。例如，在说明书中提到第一特征形成于第二特征之上，其包括第一特征与第二特征是直接接触的实施例，另外也包括于第一特征与第二特征之间另外有其他特征的实施例，亦即，第一特征与第二特征并非直接接触。此外，在不同实施例中可能使用重复的标号或标示，这些重复仅为了简单清楚地叙述本公开，不代表所讨论的不同实施例及/或结构之间有特定的关系。
此外，其中可能用到与空间相关用词，例如“在…下方”、“下方”、“较低的”、“上方”、“较高的”及类似的用词，这些空间相关用词是为了便于描述图示中一个(些)元件或特征与另一个(些)元件或特征之间的关系，这些空间相关用词包括使用中或操作中的装置的不同方位，以及附图中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位)，则其中所使用的空间相关形容词也将依转向后的方位来解释。
本公开实施例提供降低接点电阻的能力。通常可以通过增加接点的接触面积，或降低接点材料的电阻，以提高接点的电导率进而降低接点的电阻。例如，一些内连线可使用种子层(seed layer)，以改善于两种分离材料界面处的电导率。根据本公开一些实施例，可在两种材料的界面形成金属硅化物，以增加接点的电导率(或降低其电阻)。此外，于一些实施例中，可于接触界面施加预清洗和化学反应，从而增加金属硅化物的宽度和深度。可以在接触界面上形成接点。虽然接点的形成解释为与鳍式场效晶体管相关，本领域具有通常知识者应理解，于此讨论的接点的应用、结构和其形成方法并不限于在鳍式场效晶体管结构中使用。
图1是鳍式场效晶体管30范例的三维视图。鳍式场效晶体管30包括基板32上的鳍片36。基板32包括隔离区34，和突出于相邻的隔离区34且位于其之间的鳍片36。于此范例中，鳍式场效晶体管30包括两个栅极电极38/40，然而，鳍式场效晶体管可以包含一个栅极或两个以上的栅极。栅极介电质38沿着鳍片36的侧壁和位于鳍片36的顶表面上，栅极电极40位于栅极介电质38上。源极/漏极区42和43以及43和44设置在栅极电极38/40相反侧的鳍片中。图1更绘示于随后的附图中所使用的参考剖面。剖面A-A沿着鳍片36的长平分鳍片36。后续附图参照本参考剖面。
图2至图9是根据一示例性实施例，绘示形成接点的中间步骤的剖面图。附图中使用的标号可包括用于区分一种特定结构与另一种特定结构的字母，否则它们是相同的、可互换的或功能上不可区分的。在使用这种字母的情况下，没有相应字母的标号表示两个/所有特定结构。举例来说，标号103本身包括对应于103a、103b、103c等的广义结构。
图2包括具有半导体基板115以及形成于其上的鳍片102的半导体装置100。半导体装置100可以是主动装置，如晶体管，虽然其它实施例可以包括各种主动和被动装置，如电阻、电容、电感、二极管、可变电容等或其组合。鳍片(如图1的鳍片36或图3的鳍片102)由半导体鳍片材料103a/103b和源极/漏极材料105a/105b/105c所形成。可从半导体基板115形成半导体鳍片材料103a/103b。半导体基板115可以是半导体晶片或半导体装置的一部分。根据本公开一些实施例，半导体基板115包括结晶硅。可以用于半导体基板115中的其它材料包括碳、锗、镓、硼、砷、氮、铟及/或磷等。半导体基板115也可以包括其他半导体材料，例如III-V族化合物半导体材料。半导体基板115可为块体(bulk)基板或绝缘体上半导体(Semiconductor-on-Insulator，SOI)基板。此外，半导体基板115可以包括其他特征。举例来说，上述基板可以根据设计要求包括各种掺杂区(例如p型基板或n型基板)。举例来说，掺杂区可掺杂有p型掺质(如硼或BF2)、n型掺质(如磷或砷)及/或其组合。可配置用于n型鳍式场效晶体管的掺杂区，或者可替换地配置用于p型鳍式场效晶体管的掺杂区。
根据一些实施例，可于半导体鳍片102上形成一或多个栅极堆叠110。半导体鳍片102包括源极/漏极材料105a/105b/105c和半导体鳍片材料103a/103b。栅极堆叠110可包括金属栅极电极115a/115b、栅极绝缘体或介电质111a/111b、可选的(optional)第一栅极间隔物123a/123b、第二栅极间隔物127a/127b和形成在金属栅极电极115a/115b上的自我对准(self-aligned)接点/硬掩模119a/119b。
于一些实施例中，可使用先栅极方法(gate-first approach)形成栅极堆叠110，然而于其他实施例中，可使用后栅极方法(gate-last approach)形成栅极堆叠110。栅极堆叠110a和110b形成在基板103a/103b上。
于一些实施例中，可先形成虚置栅极堆叠。虚置栅极堆叠可以包括虚置栅极介电质、硬掩模和虚置栅极。栅极堆叠110a/110b可替代虚置栅极堆叠。可蚀刻并去除虚置栅极电极和虚置栅极介电质。可于去除虚置栅极电极和虚置栅极介电质后所留下的凹槽中共形地(conformally)沉积栅极介电质111a/111b。栅极介电层111a/111b可以包括氧化硅、氮化硅或其多层。于一些实施例中，栅极介电层111a/111b包括高介电常数(high-k)介电材料，并且可以包括如Hf、Al、Zr、La、Mg、Ba、Ti、Pb及其组合的金属氧化物或金属硅化物。形成栅极介电层111a/111b的方法可包括分子束沉积(molecular-beam deposition，MBD)、原子层沉积(atomic layer deposition，ALD)、等离子体辅助化学气相沉积(plasma-enhancedchemical vapor deposition，PECVD)等。
栅极电极115a/115b分别沉积于栅极介电层111a/111b上，且填充凹槽的剩余部分。可以由含金属材料(如TiN、TaN、TaC、Co、Ru、Al、其组合或其多层)形成栅极115a/115b。于填充栅极电极40之后，可以实行平坦化工艺，如化学机械抛光(chemical mechanicalpolishing，CMP)工艺，以去除栅极介电层111a/111b的多余部分和栅极电极115a/115b的材料。于一或多个蚀刻步骤凹蚀栅极电极115a/115b和栅极介电质111a/111b，以使凹槽形成于栅极间隔物123/127之中。可使用可接受的蚀刻工艺，如对栅极电极115a/115b及栅极介电质111a/111b的材料有选择性的蚀刻工艺。上述凹槽允许随后于凹槽内形成硬掩模119a/119b以保护取代栅极电极115a/115b。
在栅极电极115a/115b和栅极介电质111a/111b上的凹槽内形成硬掩模119a/119b。可由SiN、SiON、SiO2等或其组合制成硬掩模119a/119b。可以由化学气相沉积(chemical vapor deposition，CVD)、物理气相沉积(physical vapor deposition，PVD)、ALD、介电材料旋转涂布(spin-on-dielectric)工艺等或其组合形成硬掩模119a/119b。
可于半导体基板115中形成源极/漏极区105a/105b/105c。可于形成虚置栅极堆叠或形成栅极堆叠110a/110b之后形成源极/漏极区105a/105b/105c。于一些实施例中，可通过实行注入工艺掺杂源极/漏极区105a/105b/105c以注入适当掺质，进而补充半导体基板115中的掺质。在其它实施例中，可以通过在半导体基板115中形成凹槽(未示出)及于上述凹槽中外延生长材料，以形成源极/漏极区105a/105b/105c。可以通过使用任何可接受的蚀刻工艺来蚀刻以形成凹槽，如反应离子蚀刻(reaction ion etching，RIE)、中性束蚀刻(neutral beam etching，NBE)、四甲基氢氧化铵(tetramethyalammonium hydroxide，TMAH)、氢氧化铵(NH4OH)、对硅及隔离区的材料(未示出)有良好蚀刻选择性的能够蚀刻硅的湿蚀刻剂等或其组合。蚀刻可以是各向异性的。可实行单一蚀刻工艺或多重蚀刻工艺来蚀刻半导体鳍片102。可在凹槽中外延地生长材料105a/105b/105c以形成源极/漏极区105a/105b/105c于凹槽中，例如通过金属有机化学气相沉积(metal-organic CVD，MOCVD)、分子束外延(molecular beam epitaxy，MBE)、液相外延(liquid phase epitaxy，LPE)、气相外延(vapor phase epitaxy，VPE)、选择性外延生长(selective epitaxial growth，SEG)等或其组合。
可以通过如上所述的注入方法或于材料生长时同时掺杂源极/漏极区105a/105b/105c。外延源极/漏极区105a/105b/105c可包括任何可接受的材料，如适合n型场效晶体管及/或p型场效晶体管的材料。举例来说，在n型构造中，若半导体基板115为硅，外延源极/漏极区105a/105b/105c可包括Si、SiC、SiCP、SiP等。举例来说，在p型构造中，若半导体基板115为硅，外延源极/漏极区105a/105b/105c可以包括SiGe、SiGeB、Ge、GeSn等。外延源极/漏极区105a/105b/105c可以具有比半导体基板115的顶表面高的表面，并且可以具有晶面(facets)。
于形成鳍式场效晶体管之后，于一些实施例中，可在上述结构上形成介电层131。可以在介电层中形成接点，以电性耦接栅极和源极/漏极区至其它装置或结构。于一些实施例中，介电层131可包括多层。
图2的元件135显示额外的光致抗蚀剂层或氧化硅光致抗蚀剂层135，其沉积在半导体基板115上然后被图案化，从而在光致抗蚀剂层135中形成开口136。一般来说，光刻技术利用沉积的光致抗蚀剂材料(如光致抗蚀剂135)、照射(曝光)和显影以去除部分光致抗蚀剂材料。剩余的光致抗蚀剂材料于后续的工艺步骤如蚀刻中保护其下的材料，例如本范例中的介电材料131。在这个范例中，图案化光致抗蚀剂材料以定义将被蚀刻的区域，以及相反地，定义将被保护以免被蚀刻剂蚀刻的区域。在未使用介电材料131的实施例中，不使用光致抗蚀剂135。
值得注意的是，开口136可以比栅极结构110a/110b之间的宽度更宽。或者换句话说，开口136不必精确地位于栅极结构110a/110b上方。于一些实施例中，开口136可以跨越多个栅极堆叠。
图3是绘示在蚀刻由光致抗蚀剂掩模135曝光所留下的介电质后的鳍式场效晶体管的剖面图。可由任何适合的技术蚀刻介电质，如使用对介电材料131具有选择性的干蚀刻剂或湿蚀刻剂。于蚀刻之后可去除光致抗蚀剂135。蚀刻在栅极结构110a/110b之间形成开口201并露出源极/漏极105b的顶部。
当露出源极/漏极105b时，可形成氧化物。例如，如果源极/漏极105b是基于硅的(silicon-based)，源极/漏极105b的顶部可在鳍片顶部具有氧化硅(SiO)。氧化物可通过引起增加的电阻以干扰源极/漏极105b上的接点的形成。因此，可以在形成接点之前清洗/去除氧化物。
图4绘示预清洗工艺205和物理轰击207。使用氩(Ar)气作为清洗蚀刻剂来实行预清洗工艺205。可以使用其它清洗蚀刻剂如NF3、NH3、H2、N2、混合气Ar/H2和Ar/N2。可于实行预清洗工艺205之后、交替或同时实行物理轰击207。
于一些实施例中，可于蚀刻腔室(未示出)或沉积腔室(未示出)中使用射频(radio-frequency,RF)信号产生器(未示出)，以产生使用功率高达约1.5kW的等离子体，如约200W。在其它实施例中，可提高功率至高达约1.5kW，如至约400W。在预清洗工艺205中，在腔室中填充氩气，且露出开口201于蚀刻腔室中所产生的等离子体。在物理轰击207工艺中，可加入轰击材料至蚀刻腔室中。轰击材料可以是氯气、氟气、氨气或其组合。开口201露出于等离子体。当露出开口201于预清洗工艺和轰击材料时，开口201将变宽而成为开口211。开口211具有包括栅极间隔物127c/127d的侧壁，其在清洗蚀刻/物理轰击工艺中被薄化。
根据一些实施例，使用如上所述的工艺气体作为轰击材料实行物理轰击。也可存在其它工艺气体，包括氩、氦、氮(N2)、氢(H2)、氙、砷、锗、磷等。从轰击材料产生离子并用于轰击开口201。在真空环境(如蚀刻腔室)中实行轰击。工艺气体的流速可介于约1sccm至约20000sccm。工艺气体的压力可介于约0.1mTorr至约1Torr。偏压可介于约20eV至约5keV。轰击的持续时间可介于约1秒至约90秒。
被轰击的表面区包括源极/漏极105b的顶表面和栅极间隔物表面127c/127d。栅极间隔物和源极/漏极105b可包括原生氧化物。作为轰击的结果，表面区变得更粗糙且栅极间隔物127c/127d变薄。此外，经轰击的表面区的材料(如氧化物)之间的键结可能被破坏或松动。因此，经轰击的表面区可在随后的化学反应步骤中吸附更多工艺气体。
可于轰击中将离子注入源极/漏极区105b中。注入的离子可以具有减少随后形成的金属硅化物区域之间以及接触栓塞和源极/漏极区105b之间的电阻的功能。这可降低接触栓塞的接触电阻。可通过调整轰击离子种类和轰击能量以进一步调整接触电阻。
在物理轰击工艺207中，化学反应将发生于轰击材料与源极/漏极区105b之间源极/漏极区105b的露的表面处，且轰击材料将被并入源极/漏极区105b的顶部中。举例来说，当使用氟化铵(ammonium fluoride)气体作为轰击材料时，氟化铵可与氧化硅反应，以产生氟硅酸铵(ammonium fluorosilicate)化合物。物理轰击工艺207可包括多个循环，以提供多个气体反应。可根据等离子体工艺来调节气体注入，以由跨越开口211底部的特定区域将气体注入。
可通过将气体清洗蚀刻剂(如氩气)和物理轰击材料(如氯、氟、氨或其组合)同时填充至蚀刻腔室以同时实行预清洗工艺205和物理轰击207。可存在额外的气体，包括氢气和氮气。
参照图5，可于开口211露出的表面上形成金属层215。于一些实施例中，随后形成图7的金属硅化物层225的工艺将大抵消耗金属层215。可由钛、镍、钴、钨、铂、钼、钽等或其组合形成金属层215。如图5所示，金属层215包括与源极/漏极区105b的顶部接触的开口的底部的一部分、沿着开口211的侧壁延伸的部分及延伸于栅极堆叠110a/110b上方的部分。于一些实施例中，金属层215也可延伸至介电材料131上方。于一些实施例中，可通过如PVD、CLD、ALD、溅镀沉积等或其组合以形成厚度为约
Figure GDA0002286368760000091
至约
Figure GDA0002286368760000092
的金属层215。于一些实施例中，可于由RF信号产生器施加偏压的同时通过PVD、CLD、ALD或溅镀实行沉积。可共形地沉积金属层32，以使其在沿着开口211的底部和侧壁及于栅极堆叠110a/110b上方具有大致均匀的厚度。
参照图6，在金属层215上及开口211中形成盖层219。盖层219改善图7中随后形成的导电栓塞229之间的粘着力，且亦预防金属层225的氧化。盖层219也可作为帮助形成金属硅化物的阻挡层。盖层219有助于稳定金属层215且预防金属层225穿透至导电栓塞229。可由多层形成盖层219。可由氮化钛、氮化钽等或其组合形成盖层219。如图6所示，盖层219包括在开口211的底部的一部分、沿开口211的侧壁延伸的部分和延伸至栅极堆叠110a/110b上方的部分。于一些实施例中，部分的盖层219可以延伸至介电质131上方。于一些实施例中，通过CVD、PVD、ALD等或其组合的单一或多次循环以形成厚度约
Figure GDA0002286368760000101
至约
Figure GDA0002286368760000102
的盖层219。可以共形地沉积盖层219，以使其在沿开口211的底部和侧壁及于栅极堆叠110a/110b上方具有大抵均匀的厚度。
参照图7，硅化工艺从金属层215形成金属硅化物层225。金属硅化物层225的形成包括于半导体装置100上实行退火工艺。退火工艺使轰击材料和轰击源极/漏极区105b与金属层215反应以形成金属硅化物层225。于一些实施例中，使用快速热退火(rapid thermalanneal)、热浸泡(thermal soaking)、尖波退火(spike annealing)、快速加热退火(flashannealing)、激光退火(laser annealing)、微波退火(microwave annealing)等或其组合实行退火工艺。于一些实施例中，在介于约100℃至约900℃的温度下，于包括如N2、NH3、H2、混合气体等或其组合的工艺气体的环境中，及介于1Torr至约760Torr的压力下实行退火工艺。
于一些实施例中，退火腔室可包括加热载台(heater stage)(未绘示)以支撑晶片使其可被加热到约30℃至约120℃。退火腔室可以是等离子体蚀刻腔室(plasma etchingchamber)，其具有用于输送工艺气体至等离子体蚀刻腔室的莲蓬头式腔室盖(shower headchamber lid)(未绘示)，其中所述腔室盖还具有退火功能，例如上述的退火功能。
于一些实施例中，在形成金属硅化物层225后，可以留下部分未转化为金属硅化物层225的金属层215'。
如图7所示，金属硅化物层225包括深度h1和宽度w3。相较于无化学反应而能够形成金属硅化物层225的情况，轰击材料与鳍片105b顶部的化学反应有助于形成具有更大宽度和深度的金属硅化物层225。于一些实施例中，宽度w1可以介于约10nm至约20nm。宽度w2可以介于约15nm至约25nm。宽度w3可以介于约15nm至约30nm。于一些实施例中，w3与w1的比例增加了约6％或以上。于一些实施例中，金属硅化物的深度h1大于约6nm或7nm。轰击材料与开口211底部的轰击可以增加接点开口211侧壁的节距(pitch)，使得它们比轰击之前更加垂直。在侧壁是相邻栅极结构的栅极间隔物处，相较于栅极堆叠的栅极间隔物127a和127b，相应的开口211侧壁的栅极间隔物(如栅极间隔物127c及127d)，可更加垂直及更薄。于一些实施例中，开口211的宽度w1与开口211的底部宽度w2的尺寸比值大于约90％。
于形成金属硅化物层225后，轰击材料(如氟或氯)的元素浓度可以在金属层215’和金属硅化物层225的界面处的化学指数(chemical index)中找到。于图11中，如下所述，使用氟作为代表显示这些元素之间的关系。在靠近金属硅化物层225的顶部的金属层215'和金属硅化物层225的界面处，可以找到轰击材料的第一浓度。轰击材料的第一浓度可为金属硅化物层225中轰击材料的峰值浓度。形成金属硅化物层225的硅化工艺也可以导致轰击材料浸入回到(leech back)金属层215'中。因此，于一些实施例中，可以在金属层215'的化学指数中找到轰击材料。进一步往金属硅化物层225中移动，轰击材料的化学指数会下降直到其为微量(trace amount)。于一些实施例中，于金属硅化物深度的大约一半处将存在微量的轰击材料。轰击材料的第二浓度可以开始于金属硅化物深度的大约一半处，且以大约相同的浓度持续遍及至剩余的金属硅化物层225。
参照图8，可以导电材料229填充图7的开口211。于一些实施例中，导电材料229填充开口211，且亦延伸至介电层131上方。于一些实施例中，导电材料229可填充开口211，且不延伸至介电层131上方。导电材料229包括图9的随后将形成的导电栓塞229'。导电材料229包括任何合适的金属或合金，例如钨、铝、铜、氮化钛、氮化钽等或其组合。可实行CVD、ALD、PVD、溅镀等或其组合以形成导电材料。可通过沉积多层的多重步骤形成导电材料229。
参照图9，可于导电材料229上实行平坦化工艺以形成导电栓塞229'。于一些实施例中，平坦化工艺是化学机械抛光工艺、蚀刻工艺等或其组合。于平坦化工艺后，导电栓塞229’的顶表面229-1与介电层131的顶表面131-1、栅极硬掩模119a/119b的顶表面119a-1/119b-1、栅极间隔物123/127的顶表面123-1/127-1、金属层215'的最顶表面及盖层219的最顶表面大抵共面。金属硅化物层225、未反应的金属层215’(若存在)、盖层219和导电栓塞229’形成接触结构233。
于一些实施例中，可于硅化源极/漏极区105b的同时或之后硅化源极/漏极区105a/105c，且于其中形成相应的接触结构。可使用上述与硅化源极/漏极区105b相同的工艺以硅化源极/漏极区105a/105c。细节不于此处重复。
于一些实施例中，可在栅极堆叠110a/110b上形成栅极接点。于一些实施例中，可使用上述的硅化工艺以形成用于栅极接点的栅极金属硅化物。于一些实施例中，上述硅化工艺可以用于形成接点或其它类型的半导体装置，例如其它类型的晶体管、纳米线(nano-wire)晶体管和中介层(interposer)。
图10是根据一些实施例绘示的流程图。在步骤305中，于形成源极/漏极区(如图2的源极/漏极区105a/105b/105c)和栅极堆叠(如栅极堆叠110a/110b)后，于源极/漏极区上形成开口。
在步骤310中，使用清洗剂清洗开口。于一些实施例中，清洗剂可以是氩气或等离子体，用于蚀刻开口以除去任何残留的氧化物或介电材料(如图3的来自介电材料131的残留物)。
在步骤315中，通过轰击材料轰击开口。轰击材料可为氯、氟或其组合。如上所述，可通过RF产生器产生等离子体。于一些实施例中，可以同时进行步骤310和315。于一些实施例中，可交替重复步骤310和315。于一些实施例中，可重复约1至5次清洗和物理轰击。于一些实施例中，可重复更多次清洗和物理轰击，例如10或20次。通过清洗和物理轰击，可薄化形成开口的侧壁的栅极间隔物。
在步骤320中，于开口中形成金属层。金属层的形成已在上述关于图5中详细讨论，在此不再重复。
在步骤325中，在金属层上形成盖层。金属层的形成已在上述关于图6中详细讨论，在此不再重复。
在步骤330中，在源极/漏极区中形成金属硅化物。由于轰击材料在源极/漏极区表面的反应，金属硅化物的形成可以比原本更宽广和更深。举例来说，金属硅化物可以包括栅极间隔物下方的区域。硅化物的形成已在上述关于图7中详细讨论，在此不再重复。
在步骤335中，以导电材料填充开口。在步骤340中，将导电材料平坦化以使其与栅极堆叠大抵共面。
图11是根据一些实施例绘示的金属硅化物区域225的化学指数图表。垂直虚线位于图表上的大概区域中，其被定义为金属硅化物区域。每个虚线都是约略的，并且可理解为在由每个虚线上方的箭头所示的范围内。化学指数显示形成金属硅化物区域的钛和硅。于金属硅化物区域也存在氟，其于本范例中用作轰击材料。用于形成金属硅化物的退火工艺可引起轰击材料浸入或扩散回到金属层215'和盖层219中。因此，可以在金属层215'和盖层219中找到轰击材料的浓度。轰击材料在金属硅化物层的最上部分或表面处具有其峰值浓度。轰击材料的浓度在金属硅化物层深度约一半时显著下降到第二浓度。对于金属硅化物层的剩余深度，轰击材料的浓度在第二浓度处保持大约相同。
接触结构233电性耦接源极/漏极区105a/105b/105c至其上的结构(未示出)，如导电线/通孔及/或其它主动和被动装置。举例来说，可在接触结构233和介电层131上形成包括交替的介电材料层和导电材料层的内连线结构。接触结构233可电性耦接源极/漏极区105b至这种内连线结构。
本公开实施例可提供降低形成于鳍式场效晶体管的源极/漏极区上的接点的电阻的能力。通过以预清洗工艺和诸如氯或氟的材料的物理轰击来预处理接点开口，随后形成的金属硅化物相较于未经由预清洗工艺和物理轰击所形成的金属硅化物可具有较低的电阻。金属硅化物可更宽且更深入源极/漏极区。接触孔本身的底部也可以比以前更宽。
在一些实施例中，本公开公开了一种半导体装置，包括：金属硅化物区域，形成于半导体材料中，金属硅化物区域包括第一材料及第二材料，第一材料包括金属，第二材料包括氯、氟或其组合，金属硅化物区域的最上部有具有第一浓度的第二材料；盖层，于金属硅化物区域及接触栓塞开口的侧壁上；以及接触栓塞，形成于盖层之上，填充接触栓塞开口。
在另一些实施例中，本公开公开了一种半导体装置，包括：鳍式场效晶体管，具有第一栅极结构及第二栅极结构，每个第一栅极结构及第二栅极结构各自包括第一栅极间隔物及第二栅极间隔物，每个第一栅极间隔物与每个第二栅极间隔物分离；源极/漏极区，介于第一栅极结构及第二栅极结构间；接点，包括：侧壁，包括第一金属材料，第一金属材料与第一栅极的第一栅极间隔物及第二栅极的第二栅极间隔物重合；底部，包括于源极/漏极区的顶表面上的金属硅化物；栓塞，介于接点的侧壁间及接点的底部上，栓塞包括导电材料；盖层，介于栓塞及金属硅化物间；其中金属硅化物延伸至第一栅极结构的第一栅极间隔物及第二栅极结构的第二栅极间隔物下。
在又一些实施例中，本公开公开了一种半导体装置形成方法，包括：于第一栅极及第二栅极间形成开口；清洗开口；以第一材料轰击开口的底部，从而于第一材料及接触区域的顶表面间引发化学反应；于开口中沉积金属层；于金属层上沉积盖层；于接触区域的顶表面生成金属硅化物；以及于生成金属硅化物后，于开口中沉积金属栓塞。
如本公开一实施例所述的半导体装置，还包括一金属层，介于该金属硅化物及该盖层间，该金属层包括该第一金属。
如本公开一实施例所述的半导体装置，其中该金属层包括具有一第二浓度的该第二材料。
如本公开一实施例所述的半导体装置，其中该金属硅化物区域形成于一鳍式场效晶体管的一源极/漏极区中。
如本公开一实施例所述的半导体装置，其中该接触栓塞开口的一侧壁与一栅极堆叠的一第一栅极间隔物接触。
如本公开一实施例所述的半导体装置，其中该第一栅极间隔物比该栅极堆叠的一第二栅极间隔物薄，该第二栅极间隔物与该栅极堆叠的栅极相对。
如本公开一实施例所述的半导体装置，其中该金属硅化物区域比该接触栓塞开口的一底部宽。
如本公开一实施例所述的半导体装置，其中该接触栓塞的一最顶表面与一相邻栅极堆叠的一最顶表面大抵共面。
如本公开另一实施例所述的半导体装置，还包括一金属层，介于该盖层及该金属硅化物之间，该金属层包括该第一金属材料。
如本公开另一实施例所述的半导体装置，其中该第一栅极结构的该第一栅极间隔物比该第二栅极结构的该第二栅极间隔物更垂直。
如本公开另一实施例所述的半导体装置，其中于该金属层及该金属硅化物层的一界面有氯或氟。
如本公开另一实施例所述的半导体装置，其中该第一栅极结构的该第一栅极间隔物较该第二栅极结构的该第二栅极间隔物薄。
如本公开又一实施例所述的半导体装置形成方法，还包括平坦化该金属栓塞，以使该金属栓塞的一最顶表面与该第一栅极的一最顶表面及该第二栅极的一最顶表面大抵共面。
如本公开又一实施例所述的半导体装置形成方法，其中该金属硅化物比该开口的一底部宽度宽。
如本公开又一实施例所述的半导体装置形成方法，其中该清洗及该轰击同时进行。
如本公开又一实施例所述的半导体装置形成方法，其中该第一材料包括氟、氯或其组合。
如本公开又一实施例所述的半导体装置形成方法，其中生成该金属硅化物由一快速热退火进行。
如本公开又一实施例所述的半导体装置形成方法，其中该金属硅化物的深度大于约6nm。
上述内容概述许多实施例的特征，因此任何本领域技术人员，可更加理解本公开的各面向。任何本领域技术人员，可能无困难地以本公开为基础，设计或修改其他工艺及结构，以达到与本公开实施例相同的目的及/或得到相同的优点。任何本领域技术人员也应了解，在不脱离本公开的精神和范围内做不同改变、代替及修改，如此等效的创造并没有超出本公开的精神及范围。

Claims (32)

1.一种半导体装置，包括：
一金属硅化物区域，形成于一半导体材料中，该金属硅化物区域包括一第一材料及一第二材料，该第一材料包括一金属，该第二材料包括氯、氟或其组合，该金属硅化物区域的一最上部有具有一第一浓度的该第二材料，其中该第二材料在该金属硅化物区域中的该第一浓度以一梯度从该金属硅化物区域的该最上部进一步降低到该金属硅化物区域的一中间位置，其中在该金属硅化物区域中的该第二材料的一第二浓度从该金属硅化物区域的该中间位置到该金属硅化物区域的一深度大抵均匀；
一盖层，于该金属硅化物区域及一接触栓塞开口的一侧壁上；以及
一接触栓塞，形成于该盖层之上，填充该接触栓塞开口。
2.如权利要求1所述的半导体装置，还包括一金属层，介于该金属硅化物及该盖层间，该金属层包括该第一材料。
3.如权利要求1所述的半导体装置，其中该金属硅化物区域形成于一鳍式场效晶体管的一源极/漏极区中。
4.如权利要求1所述的半导体装置，其中该接触栓塞开口的一侧壁与一栅极堆叠的一第一栅极间隔物接触。
5.如权利要求4所述的半导体装置，其中该第一栅极间隔物比该栅极堆叠的一第二栅极间隔物薄。
6.如权利要求1所述的半导体装置，其中该金属硅化物区域比该接触栓塞开口的一底部宽。
7.如权利要求1所述的半导体装置，其中该接触栓塞的一最顶表面与一相邻栅极堆叠的一最顶表面大抵共面。
8.一种半导体装置，包括：
一鳍式场效晶体管，具有一第一栅极结构及一第二栅极结构，每个该第一栅极结构及该第二栅极结构各自包括一第一栅极间隔物及一第二栅极间隔物，每个该第一栅极间隔物与每个该第二栅极间隔物分离；
一源极/漏极区，介于该第一栅极结构及该第二栅极结构间；
一接点，包括：
多个侧壁，包括一第一金属材料，该第一金属材料与该第一栅极的该第一栅极间隔物及该第二栅极的该第二栅极间隔物重合；
一底部，包括于该源极/漏极区的顶表面上的一金属硅化物，其中该金属硅化物具有一第一深度，该金属硅化物的一上表面包括具有一第一浓度的第一材料，该第一材料的该第一浓度在该金属硅化物的一第二深度以一第一梯度降低到该第一材料的一第二浓度，其中该第一材料从该金属硅化物的该第二深度到该金属硅化物的该第一深度持续具有该第二浓度，该第二深度位于该金属硅化物的该顶表面以及该金属硅化物的该第一深度之间；
一栓塞，介于该接点的该等侧壁间及该接点的该底部上，该栓塞包括一导电材料；
一盖层，介于该栓塞及该金属硅化物间；
其中该金属硅化物延伸至该第一栅极结构的该第一栅极间隔物及该第二栅极结构的该第二栅极间隔物下。
9.如权利要求8所述的半导体装置，还包括一金属层，介于该盖层及该金属硅化物之间，该金属层包括该第一金属材料。
10.如权利要求8所述的半导体装置，其中该第一栅极结构的该第一栅极间隔物比该第二栅极结构的该第二栅极间隔物更垂直。
11.如权利要求9所述的半导体装置，其中于该金属层及该金属硅化物层的一界面有氯或氟。
12.如权利要求8所述的半导体装置，其中该第一栅极结构的该第一栅极间隔物较该第二栅极结构的该第二栅极间隔物薄。
13.一种半导体装置形成方法，包括：
于一第一栅极及一第二栅极间的一绝缘层中形成一开口，该开口露出一源极/漏极区的一接触区域；
清洗该开口；
以一第一材料轰击该开口的一底部，从而于该第一材料及该接触区域的一顶表面间引发一化学反应；
于该开口中沉积一金属层；
于该金属层上沉积一盖层；
于该接触区域的该顶表面生成一金属硅化物，其中该金属硅化物具有一第一深度，该金属硅化物的一上表面包括具有一第一浓度的该第一材料，该第一材料的该第一浓度在该金属硅化物的一第二深度以一第一梯度降低到该第一材料的一第二浓度，其中该第一材料从该金属硅化物的该第二深度到该金属硅化物的该第一深度持续具有该第二浓度，该第二深度位于该金属硅化物的该顶表面以及该金属硅化物的该第一深度之间；以及
于生成该金属硅化物后，于该开口中沉积一金属栓塞。
14.如权利要求13所述的半导体装置形成方法，还包括：
平坦化该金属栓塞，以使该金属栓塞的一最顶表面与该第一栅极的一最顶表面及该第二栅极的一最顶表面大抵共面。
15.如权利要求13所述的半导体装置形成方法，其中该金属硅化物比该开口的一底部宽度宽，该底部宽度在该第一栅极的一第一间隔物下以及该第二栅极的一第二间隔物下延伸。
16.如权利要求13所述的半导体装置形成方法，其中该清洗操作及该轰击操作同时完成。
17.如权利要求13所述的半导体装置形成方法，其中该金属硅化物的该第一深度介于6nm以及该源极/漏极区的一厚度之间。
18.如权利要求13所述的半导体装置形成方法，其中该第一材料包括氨。
19.如权利要求13所述的半导体装置形成方法，其中该绝缘层包括一连续层，横向围绕该第一栅极以及该第二栅极，并在该第一栅极的一顶部以及该第二栅极的一顶部的上方延伸，其中该绝缘层的厚度大于该第一栅极的高度，该开口露出在第一栅极的一第一栅极电极上方的一第一掩模层以及该第二栅极的一第二栅极电极上方的一第二掩模层，且该轰击操作包括轰击该第一掩模层以及该第二掩模层。
20.如权利要求13所述的半导体装置形成方法，其中该轰击操作造成该开口在该开口的该底部变宽，从而在该开口的该底部的一第一宽度与该开口在该第一栅极的一垂直中点的一第二宽度的比值大于90％。
21.一种半导体装置形成方法，包括：
在垂直一半导体鳍片的方向上，在该半导体鳍片上方形成一第一栅极结构以及一第二栅极结构，该第一栅极结构包括一第一栅极堆叠以及设置在该第一栅极堆叠旁的一第一栅极间隔物，该第二栅极结构包括一第二栅极堆叠以及设置在该第二栅极堆叠旁的一第二栅极间隔物，该第一栅极以及该第二栅极分别具有一非垂直侧壁；
在该第一栅极堆叠以及该第二栅极堆叠之间沉积一第一层，该第一层包括一介电材料；
在该第一层中蚀刻出一开口，以露出一晶体管的一源极/漏极区，其中该蚀刻操作使用该第一栅极结构的该第一栅极间隔物以及该第二栅极结构的该第二栅极间隔物作为一蚀刻掩模；
藉由一清洗工艺扩大该开口；
使用一第一材料轰击露出的该源极/漏极区，该第一材料与该源极/漏极区的一材料反应，其中该轰击操作造成该第一栅极间隔物的该非垂直侧壁以及该第二栅极间隔物的该非垂直侧壁更加地垂直，在轰击露出的该源极/漏极区之后，该开口的一底部的第一宽度与该开口在该第一栅极结构的一垂直中点的一第二宽度的一比值大于90％；
在该开口中沉积一金属膜；以及
硅化该源极/漏极区，以在该源极/漏极区中形成一金属硅化物区域，其中该金属硅化物区域中的该第一材料的一第一浓度从该金属硅化物区域的上表面以一梯度降低到该金属硅化物区域的一中间位置，其中该第一材料在该金属硅化物区域中的一第二浓度从该金属硅化物区域的该中间位置到该金属硅化物区域的一深度大抵均匀。
22.如权利要求21所述的半导体装置形成方法，还包括：
在硅化该源极/漏极区的操作的前，在该金属膜上方形成一盖层。
23.如权利要求22所述的半导体装置形成方法，还包括：
在该开口中形成一金属栓塞，其中在形成该金属栓塞的操作之后，该盖层残留在该金属栓塞以及该金属硅化物区域之间，且该第一材料在该金属栓塞中具有一第三浓度。
24.如权利要求21所述的半导体装置形成方法，其中该清洗工艺以及该轰击操作在一相同的工艺步骤进行。
25.如权利要求21所述的半导体装置形成方法，其中该第一材料包括氟、氯、或其组合。
26.如权利要求21所述的半导体装置形成方法，还包括：
在该第一栅极间隔物以及该第一栅极堆叠之间形成一第三栅极间隔物；
在该第二栅极间隔物以及该第二栅极堆叠之间形成一第四栅极间隔物，其中该金属硅化物区域水平地延伸超出该开口的横向范围，且该金属硅化物区域在该第一栅极间隔物下方延伸到该第三栅极间隔物，以及在该第二栅极间隔物下方延伸到该第四栅极间隔物。
27.如权利要求21所述的半导体装置形成方法，其中该第一材料包括氨。
28.一种半导体装置形成方法，包括：
在一第一栅极堆叠以及一第二栅极堆叠之间形成一源极/漏极区；
在该源极/漏极区上方形成一绝缘层，该绝缘层在该第一栅极堆叠以及该第二栅极堆叠上方延伸；
在该绝缘层中蚀刻出一开口，该开口露出该源极/漏极区、该第一栅极堆叠的一上部、以及该第二栅极堆叠的一上部；
使用一第一材料轰击该源极/漏极区，该第一材料包括氯；以及
在该源极/漏极区的一上部形成一金属硅化物区域，该金属硅化物区域横向延伸超出该开口，该金属硅化物区域的一上表面包括一第一浓度的该第一材料，其中该第一材料在该金属硅化物区域中的该第一浓度以一梯度从该金属硅化物区域的该上表面进一步降低到该金属硅化物区域的一中间位置，其中在该金属硅化物区域中的该第一材料的一第二浓度从该金属硅化物区域的该中间位置到该金属硅化物区域的一深度大抵均匀。
29.如权利要求28所述的半导体装置形成方法，其中形成该金属硅化物区域的操作包括：
在该开口中沉积一第一金属膜，该第一金属膜接触该源极/漏极区；
在该开口中于该第一金属膜上方沉积一盖层；以及
退火该源极/漏极区。
30.如权利要求28所述的半导体装置形成方法，还包括：
在该开口中沉积一金属栓塞，其中具有一第三浓度的该第一材料沉积在该金属栓塞中；以及
平坦化该金属栓塞以及该绝缘层，以使该金属栓塞的一最上表面与该第一栅极堆叠的一最上表面齐平。
31.如权利要求28所述的半导体装置形成方法，还包括：
在轰击该源极/漏极区的操作时，经由一清洗蚀刻工艺扩大该开口。
32.如权利要求28所述的半导体装置形成方法，其中该轰击操作造成该开口的一第一非垂直侧壁变得更加垂直，该开口的该第一非垂直侧壁包括该第一栅极堆叠的一间隔物。
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