TW201318129A - 嵌埋穿孔中介層之封裝基板及其製法 - Google Patents

嵌埋穿孔中介層之封裝基板及其製法 Download PDF

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TW201318129A
TW201318129A TW100139667A TW100139667A TW201318129A TW 201318129 A TW201318129 A TW 201318129A TW 100139667 A TW100139667 A TW 100139667A TW 100139667 A TW100139667 A TW 100139667A TW 201318129 A TW201318129 A TW 201318129A
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layer
interposer
conductive
package substrate
end surface
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TW100139667A
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TWI476888B (zh
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Dyi-Chung Hu
Tzyy-Jang Tseng
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Unimicron Technology Corp
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Priority to TW100139667A priority Critical patent/TWI476888B/zh
Priority to CN201110427233.6A priority patent/CN103094244B/zh
Priority to JP2012011761A priority patent/JP2013098526A/ja
Priority to US13/604,968 priority patent/US8946564B2/en
Priority to KR1020120098720A priority patent/KR101414057B1/ko
Publication of TW201318129A publication Critical patent/TW201318129A/zh
Priority to US14/602,656 priority patent/US9781843B2/en
Priority to US14/602,645 priority patent/US9357659B2/en
Application granted granted Critical
Publication of TWI476888B publication Critical patent/TWI476888B/zh
Priority to US15/391,861 priority patent/US11127664B2/en
Priority to US15/701,435 priority patent/US20170374748A1/en
Priority to US16/379,816 priority patent/US11445617B2/en
Priority to US16/672,512 priority patent/US20200068721A1/en
Priority to US17/194,323 priority patent/US11895780B2/en
Priority to US17/818,006 priority patent/US20220375919A1/en

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Abstract

一種嵌埋穿孔中介層之封裝基板，係包括：模封層、嵌埋於該模封層中且具有複數導電穿孔的穿孔中介層、嵌埋於該模封層中且設於該穿孔中介層上並電性連接該導電穿孔之其中一端面的線路重佈層、以及設於該模封層與穿孔中介層上並電性連接該導電穿孔之另一端面的增層結構。藉由嵌埋該穿孔中介層，使該線路重佈層以電性結合間距較小的半導體晶片之電極墊，而另一端電性連接間距較大之增層結構之導電盲孔，令該封裝基板可結合具有高佈線密度之半導體晶片。本發明復提供該嵌埋穿孔中介層之封裝基板之製法。

Description

嵌埋穿孔中介層之封裝基板及其製法
　　本發明係有關於一種封裝基板及其製法，尤指一種承載半導體晶片用之嵌埋穿孔中介層之封裝基板及其製法。
　　如第1圖所示，係為習知覆晶式封裝結構之剖視示意圖，該封裝結構之製程係先提供一具有核心板102、第一表面10a及第二表面10b之雙馬來醯亞胺-三氮雜苯（Bismaleimide-Triazine, BT）封裝基板10，且於該封裝基板10之第一表面10a形成有覆晶焊墊100；再藉由焊錫凸塊11電性連接半導體晶片12之電性連接墊120；接著，於該封裝基板10之第一表面10a與該半導體晶片12之間形成底膠17，以包覆該焊錫凸塊11；又於該封裝基板10之第二表面10b具有植球墊101，以藉由焊球13電性連接例如為印刷電路板之另一電子裝置（未表示於圖中）。
　　然，為了增進該半導體晶片12的電性效能，故於該半導體晶片12的後端製程（Back-End Of Line, BEOL）中通常將採用超低介電係數(Extreme low-k dielectric, ELK) 或超低介電常數(Ultra low-k, ULK)之介電材料，但該low-k之介電材料為多孔且易脆之特性，以致於當進行覆晶封裝後，在信賴度熱循環測試時，將因該封裝基板10與該半導體晶片12之間的熱膨脹係數（thermal expansion coefficient, CTE）差異過大，導致該焊錫凸塊11易因熱應力不均而產生破裂，使該半導體晶片12產生破裂，造成產品可靠度不佳。
　　再者，隨著電子產品更趨於輕薄短小及功能不斷提昇之需求，該半導體晶片12之佈線密度愈來愈高，以奈米尺寸作單位，因而各該電性連接墊120之間的間距更小；然，習知封裝基板10之覆晶焊墊100之間距係以微米尺寸作單位，而無法有效縮小至對應該電性連接墊120之間距的大小，導致雖有高線路密度之半導體晶片12，卻未有可配合之封裝基板，以致於無法有效生產電子產品。
　　因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。
　　鑑於上述習知技術之種種缺失，本發明遂提供一種嵌埋穿孔中介層之封裝基板，係包括：模封層；嵌埋於該模封層中之穿孔中介層，係具有複數導電穿孔，該導電穿孔之相對兩端面均外露於該穿孔中介層；嵌埋於該模封層中且設於該穿孔中介層上之線路重佈層，係電性連接該導電穿孔之其中一端面；以及設於該模封層與穿孔中介層上之增層結構，係電性連接該導電穿孔之另一端面。
　　本發明復提供一種嵌埋穿孔中介層之封裝基板之製法，係包括：提供一具有複數導電穿孔之穿孔中介層，該導電穿孔之相對兩端面均外露於該穿孔中介層，又於該穿孔中介層上形成電性連接該導電穿孔一端面之線路重佈層；將一模封層包覆該穿孔中介層，使該穿孔中介層與線路重佈層嵌埋於該模封層中；以及於該模封層、該穿孔中介層上形成電性連接該導電穿孔另一端面之增層結構。
　　前述之嵌埋穿孔中介層之封裝基板及其製法中，該導電穿孔之另一端面可凸出該穿孔中介層，以作為導電凸塊，俾供電性連接該增層結構。
　　由上可知，本發明嵌埋穿孔中介層之封裝基板及其製法中，係藉由嵌埋該穿孔中介層，使該導電穿孔之其中一端電性連接該線路重佈層以電性結合間距較小的半導體晶片之電性連接墊，而另一端電性連接間距較大之增層結構之導電盲孔，使該封裝基板可結合具有高佈線密度之半導體晶片，而達到整合高佈線密度之半導體晶片之目的。故藉由該中介層，不僅可解決缺乏可配合之封裝基板的問題，且不會改變IC產業原本之供應鏈（supply chain）及基礎設備（infrastructure）。
　　再者，若將半導體晶片設於該穿孔中介層上，因該穿孔中介層之熱膨脹係數與半導體晶片之熱膨脹係數相近，故可避免該半導體晶片與該穿孔中介層之間的焊錫凸塊破裂，有效使產品之可靠度提升。
　　又，藉由將該穿孔中介層嵌埋於該模封層中，可降低整體結構之厚度，且藉由於該模封層之第二表面上形成增層結構，故無需使用習知技術之核心板，亦可降低整體結構之厚度。
　　以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
　　須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
　　請參閱第2A至2J圖，係為本發明嵌埋穿孔中介層之封裝基板之製法之第一實施例之剖視示意圖。
　　如第2A圖所示，提供一中介層20’，該中介層20’具有相對之第一側20a與第二側20b’，再於該中介層20’之第一側20a形成複數穿孔200’。
　　於本實施例中，該中介層20’之材質為矽。
　　如第2B圖所示，於該穿孔200’之側壁與底部上形成絕緣層201，再於該穿孔200’中形成銅材，以形成導電穿孔200，該導電穿孔200具有對應該中介層20’之第一側20a與第二側20b’之第一端面200a與第二端面200b。
　　於本實施例中，形成該導電穿孔200之材質亦可為鎳、金、鎢、鋁或導電膏，而該絕緣層201之材質可為SiO2、Si3N4或Polymer，又該導電穿孔200之第一端面200a係與該中介層20’之第一側20a齊平。
　　另外，要補充說明的是，本發明之中介層20’除了如前述第2B圖的態樣之外，亦可為不具有該絕緣層201之態樣，亦即該中介層20’之材質可為玻璃、或例如為Al2O3或AlN之陶瓷等絕緣材料，並在該中介層20’中直接形成貫穿之導電穿孔200，由於此態樣係所屬技術領域之通常知識者所能瞭解，故不在此加以贅述與圖示。
　　如第2C圖所示，於該中介層20’之第一側20a與該導電穿孔200之第一端面200a上形成線路重佈層（Redistribution layer, RDL）21，該線路重佈層21電性連接該導電穿孔200之第一端面200a，且該線路重佈層21之最外層具有複數電極墊210。
　　如第2D圖所示，將該中介層20’之第一側20a與該線路重佈層21結合至一載板（圖未示）上，再經研磨該中介層20’之第二側20b’，使該導電穿孔200之第二端面200b外露於該穿孔中介層20之第二側20b，再移除該載板，以完成該穿孔中介層20之製作。
　　於本實施例中，該導電穿孔200之第二端面200b係與該穿孔中介層20之第二側20b齊平，且該導電穿孔200連通該穿孔中介層20之第一側20a與第二側20b，又該導電穿孔200僅於側壁上具有絕緣層201。
　　再者，所述之載板的材質係選用與該中介層20’相同或相近的材質，以利於結合該中介層20’，故該載板之材質可例如為矽、玻璃、或Al2O3、AlN之陶瓷等絕緣材料，而於本實施例中，該載板之材質選用玻璃。
　　又，該載板與該中介層20’之結合方式可為黏貼式。
　　如第2E圖所示，於如第2D圖所示之切割假想線K處進行切單後，得到複數穿孔中介層20。
　　如第2F圖所示，於一玻璃載板（圖未示）上重新排列該些穿孔中介層20，使該些穿孔中介層20之第二側20b與該導電穿孔200之第二端面200b結合至該玻璃載板上，再將一模封層22包覆該些穿孔中介層20，使該些穿孔中介層20嵌埋於該模封層22中，再移除該玻璃載板。
　　於本實施例中，該模封層22具有相對之第一表面22a及第二表面22b，以令該穿孔中介層20之第二側20b與該導電穿孔200之第二端面200b係與該模封層22之第二表面22b齊平，且該模封層22覆蓋該線路重佈層21與該些電極墊210。
　　如第2G至2I圖所示，於該模封層22之第二表面22b、該穿孔中介層20之第二側20b與該導電穿孔200之第二端面200b上形成增層結構23。
　　如第2G圖所示，係先形成一如ABF（Ajinomoto Build-up Film）之介電層230，再於該介電層230上以雷射方式形成複數線路槽（包含盲孔）230a，以外露出該導電穿孔200之第二端面200b。於本實施例中，形成該介電層230之方式可為塗佈或壓合製程，而形成該介電層230之材料亦可為PI(Polyimide)、PP(prepreg)或苯環丁烯（Benzocyclobutene, BCB）。
　　如第2H圖所示，於該線路槽230a中電鍍形成線路層231與複數導電盲孔232’，使該線路層231嵌埋於該介電層230中，且該些導電盲孔232’對應電性連接該導電穿孔200之第二端面200b。於本實施例中，係先於該線路槽230a中與介電層230上形成銅材以作為導電層（圖未示），再於該線路槽230a中與介電層230上電鍍金屬材，以形成該線路層231與該些導電盲孔232’，最後移除該介電層230底面上之金屬材與導電層。
　　因此，本發明之嵌埋式線路層231之製程，係免用蝕刻方式，因而可克服線路因蝕刻液之側蝕而損壞線路尺寸，進而導致線路需作成較大之尺寸的缺失。故當使用體積較小之穿孔中介層20時，仍可製作出更精密的線路，以對應連接較微小之導電穿孔200。
　　如第2I圖所示，依實際層數需求，可製作多層線路結構。於本實施例中，該增層結構23具有至少一介電層230、嵌埋於該介電層230中之線路層231、及設於該介電層230中並電性連接該線路層231之複數導電盲孔232，而部分之導電盲孔232’係對應電性連接該導電穿孔200之第二端面200b。
　　接著，於該增層結構23上形成絕緣保護層24，且該絕緣保護層24形成有複數開孔240，以外露部份之線路層231，俾供作為電性接觸墊233。
　　於其他實施例中，亦可移除該模封層22之第一表面22a之部分材質，令該電極墊210外露於該模封層22之第一表面22a’,22a”，俾供接置半導體晶片（圖未示）。如第2I’圖所示，係於該模封層22之第一表面22a’形成複數開孔220，令該電極墊210對應外露於該開孔220。或者，如第2I”圖所示，使該模封層22之第一表面22a”的高度齊平或低於該電極墊210之高度，令該電極墊210外露於該模封層22之第一表面22a”。
　　如第2J、2J’、2J”圖所示，於如第2I圖所示之切割假想線L處將第2I、2I’、2I”圖之結構進行切單後，可取得複數個嵌埋穿孔中介層20之封裝基板2,2’,2”。
　　於切單製程前或於後續製程中，可於該些電性接觸墊233上結合焊球25，以接置其他電子裝置，如電路板或封裝件。
　　另外，如第2K圖所示，於其他實施例之封裝基板5中，該增層結構23之線路層231’亦可形成於該介電層230之表面上，而非嵌埋型式。
　　本發明復提供一種嵌埋穿孔中介層20之封裝基板2,2’,2”，係包括：具有相對之第一表面22a,22a’,22a”及第二表面22b之模封層22、嵌埋於該模封層22中之穿孔中介層20、嵌埋於該模封層22中且設於該穿孔中介層20上之線路重佈層21、設於該模封層22之第二表面22b上之增層結構23、以及設於該增層結構23上之絕緣保護層24。
　　所述之穿孔中介層20係具有相對之第一側20a與第二側20b、及連通該第一側20a與第二側20b之複數導電穿孔200，該導電穿孔200於該第一側20a與第二側20b上分別具有第一端面200a與第二端面200b，且該導電穿孔200之側壁上可具有絕緣層201，又該穿孔中介層20之第二側20b與該導電穿孔200之第二端面200b係與該模封層22之第二表面22b齊平。
　　所述之線路重佈層21係設於該穿孔中介層20之第一側20a與該導電穿孔200之第一端面200a上，並電性連接該導電穿孔200之第一端面200a，而該線路重佈層21之最外層具有複數電極墊210。
　　所述之模封層22可覆蓋該些電極墊210，如第2J圖所示；亦可令該些電極墊210外露於該模封層22之第一表面22a’,22a”，如第2J’、2J”圖所示。
　　所述之增層結構23復設於該穿孔中介層20之第二側20b與該導電穿孔200之第二端面200b上，且具有至少一介電層230、嵌埋於該介電層230中之線路層231、及設於該介電層230中並電性連接該線路層231之複數導電盲孔232，而部分之導電盲孔232’係對應電性連接該導電穿孔200之第二端面200b。
　　所述之絕緣保護層24係形成有複數開孔240，以外露部分之線路層231，俾供作為電性接觸墊233。
　　本發明之嵌埋穿孔中介層20之封裝基板2,2’,2”及其製法，主要藉由嵌埋該穿孔中介層20，使該導電穿孔200之第一端面200a電性連接該線路重佈層21以電性結合間距較小的半導體晶片（圖未示）之電性連接墊（如第2J’、2J”圖所示），而第二端面200b電性連接間距較大之增層結構23之導電盲孔232’，使該封裝基板2,2’,2”可結合具有高佈線密度之半導體晶片，而達到整合高佈線密度之半導體晶片之目的。
　　再者，若將半導體晶片設於該穿孔中介層20上，且該穿孔中介層20之熱膨脹係數與半導體晶片之熱膨脹係數相近（CET均約為2.6ppm），故可避免該半導體晶片與該穿孔中介層20之間的焊錫凸塊破裂，因而有效使產品之可靠度提升。
　　又，將該穿孔中介層20嵌埋於該模封層22中，可降低整體結構之厚度，且於該模封層22之第二表面22b上形成增層結構23，故無需使用習知技術之核心板，亦可降低整體結構之厚度。
　　請參閱第3A至3E圖，係為本發明嵌埋穿孔中介層30之封裝基板3之製法之第二實施例之剖視示意圖。本實施例與第一實施例之差異僅在於該穿孔中介層30具有導電凸塊301，其他相關製程大致相同。
　　如第3A圖所示，提供一第2D圖所示之穿孔中介層20。
　　如第3B圖所示，蝕刻移除該穿孔中介層20之第二側20b之部分材質，使該導電穿孔300之第二端面300b係凸出該穿孔中介層30之第二側30b，令該導電穿孔300之凸出部分作為導電凸塊301（可包含該絕緣層201）。
　　如第3C圖所示，於如第3B圖所示之切割假想線K處切單後，取得複數穿孔中介層30。
　　接著，將一具有相對之第一表面22a及第二表面22b的模封層22包覆該些穿孔中介層30，使該穿孔中介層30嵌埋於該模封層22中，且該穿孔中介層30之第二側30b外露於該模封層22之第二表面22b，而該導電凸塊301凸出該模封層22之第二表面22b，又該模封層22覆蓋該線路重佈層21與該些電極墊210。
　　如第3D圖所示，於該模封層22之第二表面22b、該穿孔中介層30之第二側30b與該導電凸塊301上形成增層結構23，該增層結構23具有至少一介電層230、嵌埋於該介電層230中之線路層231、及設於該介電層230中並電性連接該線路層231之複數導電盲孔232，而部分之導電盲孔232’係對應電性連接該導電凸塊301。
　　接著，於該增層結構23上形成絕緣保護層24，且該絕緣保護層24形成有複數開孔240，以外露部份之線路層231，俾供作為電性接觸墊233。
　　於其他實施例中，亦可移除該模封層22之第一表面22a之部分材質，令該電極墊210外露於該模封層22之第一表面22a’,22a”。如第3D’圖所示，係於該模封層22之第一表面22a’形成複數開孔220，令該電極墊210對應外露於該開孔220。或者，如第3D”圖所示，使該模封層22之第一表面22a”的高度齊平或低於該電極墊210之高度，令該電極墊210外露於該模封層22之第一表面22a”。
　　如第3E、3E’、3E”圖所示，於如第3D圖所示之切割假想線L處將第3D、3D’、3D”圖之結構進行切單後，可取得複數個嵌埋穿孔中介層30之封裝基板3,3’,3”。
　　於切單製程前或於後續製程中，可於該些電性接觸墊233上結合焊球25，以接置其他電子裝置，如電路板或封裝件。
　　本發明之製法中，藉由該導電穿孔300之第二端面300b凸出該穿孔中介層30之第二側30b以作為導電凸塊301，當製作該增層結構23以雷射形成該線路槽230a時，雷射產生的高溫及壓力將被硬質材之該導電凸塊301吸收，以避免破壞由脆弱材質所製成之穿孔中介層30。
　　再者，雖可直接於該導電穿孔300之第二端面300b上結合凸塊，以代替蝕刻移除該穿孔中介層20之第二側20b之部分材質，但此方式所形成之凸塊的高度至少需30μm，因而不利於微小化之穿孔中介層30，又於該凸塊上還需先進行化鎳金製程，導致成本提高，且製程溫度高，藥水攻擊性強，因而還需考量凸塊材料之承受度。
　　請參閱第4A、4A’及4A”圖，係為本發明嵌埋穿孔中介層30之封裝基板4,4’,4”之第三實施例之剖視示意圖。本實施例與第二實施例之差異僅在於線路層係形成於該介電層上，其他相關製程均相同。
　　如第4A、4A’及4A”圖所示，該增層結構23之線路層231’係設於該介電層230之表面上。
　　本發明復提供一種嵌埋穿孔中介層30之封裝基板3,3’,3”,4,4’,4”，係包括：具有相對之第一表面22a,22a’,22a”及第二表面22b之模封層22、嵌埋於該模封層22中之穿孔中介層30、嵌埋於該模封層22中且設於該穿孔中介層30上之線路重佈層21、設於該模封層22之第二表面22b上之增層結構23、以及設於該增層結構23上之絕緣保護層24。
　　所述之穿孔中介層30係具有相對之第一側30a與第二側30b、及連通該第一側30a與第二側30b之複數導電穿孔300，該導電穿孔300於該第一側30a與第二側30b上分別具有第一端面300a與第二端面300b，且該導電穿孔300之側壁上可具有絕緣層201，而該第二側30b係外露於該模封層22之第二表面22b，又該導電穿孔300之第二端面300b凸出該穿孔中介層30之第二側30b與該模封層22之第二表面22b，以作為導電凸塊301。
　　所述之線路重佈層21係設於該穿孔中介層30之第一側30a與該導電穿孔300之第一端面300a上，並電性連接該導電穿孔300之第一端面300a，而該線路重佈層21之最外層具有複數電極墊210。
　　所述之模封層22可覆蓋該些電極墊210，如第3E圖所示；亦可令該些電極墊210外露於該模封層22之第一表面22a’,22a”，如第3E’、3E”圖所示。
　　所述之增層結構23復設於該穿孔中介層30之第二側30b與該導電穿孔300之第二端面300b上，且具有至少一介電層230、嵌埋於該介電層230中之線路層231（如第3E、3E’、3E”圖所示）、及設於該介電層230中並電性連接該線路層231之複數導電盲孔232，而部分之導電盲孔232’係對應電性連接該導電凸塊301。再者，該線路層231’亦可設於該介電層230上，如第4A、4A’及4A”圖所示。
　　所述之絕緣保護層24係形成有複數開孔240，以外露部分之線路層231，俾供作為電性接觸墊233。
　　綜上所述，本發明之嵌埋穿孔中介層之封裝基板及其製法，藉由將中介層嵌埋於模封層中，不僅可解決缺乏可配合之封裝基板的問題，且不會改變IC產業原本之供應鏈（supply chain）及基礎設備（infrastructure），以符合微小化與低成本之需求。
　　上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10,3,3’,3”,4,4’,4”．．．封裝基板
10a,22a,22a’,22a”．．．第一表面
10b,22b．．．第二表面
100．．．覆晶焊墊
101．．．植球墊
102．．．核心板
11．．．焊錫凸塊
12．．．半導體晶片
120．．．電性連接墊
13,25．．．焊球
17．．．底膠
2,2’,2”,5．．．封裝基板
20,30．．．穿孔中介層
20’．．．中介層
20a,30a．．．第一側
20b,20b’,30b．．．第二側
200,300．．．導電穿孔
200’．．．穿孔
200a,300a．．．第一端面
200b,300b．．．第二端面
201．．．絕緣層
21．．．線路重佈層
210．．．電極墊
22．．．模封層
220,240．．．開孔
23．．．增層結構
230．．．介電層
230a．．．線路槽
231,231’．．．線路層
232,232’．．．導電盲孔
233．．．電性接觸墊
24．．．絕緣保護層
301．．．導電凸塊
K,L．．．假想線
　　第1圖係為習知覆晶封裝結構的剖視示意圖；
　　第2A至2J圖係為本發明嵌埋穿孔中介層之封裝基板的製法之第一實施例之剖視示意圖；第2I’、2I”圖係為第2I圖之其他實施例，第2J’、2J”、2K圖係為第2J圖之其他實施態樣；
　　第3A至3E圖係為本發明嵌埋穿孔中介層之封裝基板的製法之第二實施例之剖視示意圖；第3D’、3D”圖係為第3D圖之其他實施例，第3E’、3E”圖係為第3E圖之其他實施態樣；以及
　　第4A、4A'及4A”圖係為本發明嵌埋穿孔中介層之封裝基板之第三實施例之剖視示意圖。
2．．．封裝基板
20．．．穿孔中介層
20a．．．第一側
20b．．．第二側
200．．．導電穿孔
200a．．．第一端面
200b．．．第二端面
21．．．線路重佈層
210．．．電極墊
22．．．模封層
22a．．．第一表面
22b．．．第二表面
23．．．增層結構
233．．．電性接觸墊
24．．．絕緣保護層
25．．．焊球

Claims (21)

  1. 一種嵌埋穿孔中介層之封裝基板，係包括：
    　　模封層，係具有相對之第一表面及第二表面；
    　　穿孔中介層，係嵌埋於該模封層中，且具有相對之第一側與第二側、及連通該第一側與第二側之複數導電穿孔，該導電穿孔於該第一側與第二側上分別具有第一端面與第二端面，且該穿孔中介層之第二側與該導電穿孔之第二端面係與該模封層之第二表面齊平；
    　　線路重佈層，係嵌埋於該模封層中且設於該穿孔中介層之第一側與該導電穿孔之第一端面上，並電性連接該導電穿孔之第一端面，而該線路重佈層之最外層具有電極墊；以及
    　　增層結構，係設於該模封層之第二表面、該穿孔中介層之第二側與該導電穿孔之第二端面上，且具有至少一介電層、嵌埋於該介電層中之線路層、及設於該介電層中並電性連接該線路層之複數導電盲孔，而部分之導電盲孔係對應電性連接該導電穿孔之第二端面。
  2. 如申請專利範圍第1項所述之嵌埋穿孔中介層之封裝基板，其中，該導電穿孔之側壁上具有絕緣層。
  3. 如申請專利範圍第1項所述之嵌埋穿孔中介層之封裝基板，復包括絕緣保護層，係設於該增層結構上，且具有複數開孔，以外露部分之線路層，俾供作為電性接觸墊。
  4. 如申請專利範圍第1項所述之嵌埋穿孔中介層之封裝基板，其中，該模封層覆蓋該電極墊。
  5. 如申請專利範圍第1項所述之嵌埋穿孔中介層之封裝基板，其中，該電極墊外露於該模封層之第一表面。
  6. 一種嵌埋穿孔中介層之封裝基板，係包括：
    　　模封層，係具有相對之第一表面及第二表面；
    　　穿孔中介層，係嵌埋於該模封層中，且具有相對之第一側與第二側、及連通該第一側與第二側之複數導電穿孔，該導電穿孔於該第一側與第二側上分別具有第一端面與第二端面，且該第二側係外露於該模封層之第二表面，又該導電穿孔之第二端面凸出該穿孔中介層之第二側與該模封層之第二表面，以作為導電凸塊；
    　　線路重佈層，係嵌埋於該模封層中且設於該穿孔中介層之第一側與該導電穿孔之第一端面上，並電性連接該導電穿孔之第一端面，而該線路重佈層之最外層具有電極墊；以及
    　　增層結構，係設於該模封層之第二表面、該穿孔中介層之第二側與該導電凸塊上，且具有至少一介電層、設於該介電層上之線路層、及設於該介電層中並電性連接該線路層之複數導電盲孔，而部分之導電盲孔係對應電性連接該導電凸塊。
  7. 如申請專利範圍第6項所述之嵌埋穿孔中介層之封裝基板，其中，該導電穿孔之側壁上具有絕緣層。
  8. 如申請專利範圍第6項所述之嵌埋穿孔中介層之封裝基板，復包括絕緣保護層，係設於該增層結構上，且具有複數開孔，以外露部分之線路層，俾供作為電性接觸墊。
  9. 如申請專利範圍第6項所述之嵌埋穿孔中介層之封裝基板，其中，該線路層嵌埋於該介電層中。
  10. 如申請專利範圍第6項所述之嵌埋穿孔中介層之封裝基板，其中，該模封層覆蓋該電極墊。
  11. 如申請專利範圍第6項所述之嵌埋穿孔中介層之封裝基板，其中，該電極墊外露於該模封層之第一表面。
  12. 一種嵌埋穿孔中介層之封裝基板之製法，係包括：
    　　提供一穿孔中介層，該穿孔中介層具有相對之第一側與第二側、及連通該第一側與第二側之複數導電穿孔，該導電穿孔於該第一側與第二側上分別具有第一端面與第二端面，而該導電穿孔之第二端面係與該穿孔中介層之第二側齊平，又於該穿孔中介層之第一側與該導電穿孔之第一端面上形成線路重佈層，該線路重佈層電性連接該導電穿孔之第一端面，且該線路重佈層之最外層具有電極墊；
    　　將一模封層包覆該穿孔中介層，使該穿孔中介層嵌埋於該模封層中，且該模封層具有相對之第一表面及第二表面，以令該穿孔中介層之第二側與該導電穿孔之第二端面係與該模封層之第二表面齊平，且該模封層覆蓋該線路重佈層與該電極墊；以及
    　　於該模封層之第二表面、該穿孔中介層之第二側與該導電穿孔之第二端面上形成增層結構，該增層結構具有至少一介電層、嵌埋於該介電層中之線路層、及設於該介電層中並電性連接該線路層之複數導電盲孔，而部分之導電盲孔係對應電性連接該導電穿孔之第二端面。
  13. 如申請專利範圍第12項所述之嵌埋穿孔中介層之封裝基板之製法，其中，該導電穿孔之側壁上具有絕緣層。
  14. 如申請專利範圍第12項所述之嵌埋穿孔中介層之封裝基板之製法，其中，該線路層之製程係包括：
    　　形成該介電層；
    　　於該介電層上形成線路槽；以及
    　　於該線路槽中形成該線路層。
  15. 如申請專利範圍第12項所述之嵌埋穿孔中介層之封裝基板之製法，復包括於該增層結構上形成絕緣保護層，且該絕緣保護層具有複數開孔，以外露部份之線路層，俾供作為電性接觸墊。
  16. 如申請專利範圍第12項所述之嵌埋穿孔中介層之封裝基板之製法，復包括移除該模封層之第一表面之部分材質，令該電極墊外露於該模封層之第一表面。
  17. 一種嵌埋穿孔中介層之封裝基板之製法，係包括：
    　　提供一穿孔中介層，該穿孔中介層具有相對之第一側與第二側、及連通該第一側與第二側之複數導電穿孔，該導電穿孔於該第一側與第二側上分別具有第一端面與第二端面，而該導電穿孔之第二端面係凸出該穿孔中介層之第二側，以作為導電凸塊，又於該穿孔中介層之第一側與該導電穿孔之第一端面上形成線路重佈層，該線路重佈層電性連接該導電穿孔之第一端面，且該線路重佈層之最外層具有電極墊；
    　　將一模封層包覆該穿孔中介層，使該穿孔中介層嵌埋於該模封層中，且該模封層具有相對之第一表面及第二表面，令該穿孔中介層之第二側外露於該模封層之第二表面，且該導電凸塊凸出該模封層之第二表面，而該模封層覆蓋該線路重佈層與該電極墊；以及
    　　於該模封層之第二表面、該穿孔中介層之第二側與該導電凸塊上形成增層結構，該增層結構具有至少一介電層、設於該介電層上之線路層、及設於該介電層中並電性連接該線路層之複數導電盲孔，而部分之導電盲孔係對應電性連接該導電凸塊。
  18. 如申請專利範圍第17項所述之嵌埋穿孔中介層之封裝基板之製法，其中，該導電穿孔之側壁上具有絕緣層。
  19. 如申請專利範圍第17項所述之嵌埋穿孔中介層之封裝基板之製法，復包括於該增層結構上形成絕緣保護層，且該絕緣保護層具有複數開孔，以外露部份之線路層，俾供作為電性接觸墊。
  20. 如申請專利範圍第17項所述之嵌埋穿孔中介層之封裝基板之製法，該線路層嵌埋於該介電層中。
  21. 如申請專利範圍第17項所述之嵌埋穿孔中介層之封裝基板之製法，復包括移除該模封層之第一表面之部分材質，令該電極墊外露於該模封層之第一表面。
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JP2012011761A JP2013098526A (ja) 2011-10-31 2012-01-24 ビアホール中間層が埋め込まれたパッケージ基板及びその製造方法
US13/604,968 US8946564B2 (en) 2011-10-31 2012-09-06 Packaging substrate having embedded through-via interposer and method of fabricating the same
KR1020120098720A KR101414057B1 (ko) 2011-10-31 2012-09-06 매입 관통-비아 인터포저를 갖는 패키지 기판 및 그 제조 방법
US14/602,645 US9357659B2 (en) 2011-10-31 2015-01-22 Packaging substrate having embedded through-via interposer
US14/602,656 US9781843B2 (en) 2011-10-31 2015-01-22 Method of fabricating packaging substrate having embedded through-via interposer
US15/391,861 US11127664B2 (en) 2011-10-31 2016-12-28 Circuit board and manufacturing method thereof
US15/701,435 US20170374748A1 (en) 2011-10-31 2017-09-11 Package structure and manufacturing method thereof
US16/379,816 US11445617B2 (en) 2011-10-31 2019-04-10 Package structure and manufacturing method thereof
US16/672,512 US20200068721A1 (en) 2011-10-31 2019-11-03 Package structure and manufacturing method thereof
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US9781843B2 (en) 2017-10-03
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