TWI578458B - 封裝基材 - Google Patents

封裝基材 Download PDF

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TWI578458B
TWI578458B TW105104857A TW105104857A TWI578458B TW I578458 B TWI578458 B TW I578458B TW 105104857 A TW105104857 A TW 105104857A TW 105104857 A TW105104857 A TW 105104857A TW I578458 B TWI578458 B TW I578458B
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circuit
trench
redistribution structure
package substrate
disposed
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TW201620092A (zh
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胡迪群
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胡迪群
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    • H—ELECTRICITY
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Description

封裝基材
本發明係有關於晶片的電路高密度封裝基材，尤其是封裝基材具有「溝槽」，環繞在「中介層」(interposer)周圍，提供電路與絕緣層材料的膨脹與收縮的空間，使得封裝不會因為CTE不匹配而變形的問題。
圖1是先前技藝，美國專利US8,269,337的截面圖，包含：中介層212、電路重新分佈層213、電路增層24、封裝材料22、晶片27。中介層212具有導通金屬210穿過中介層212。電路重新分佈層213具有電路與絕緣材料，設置於中介層212上方，且電性耦合於導通金屬210的上端。電路重新分佈層213與中介層212，統稱為電路重新分佈結構21。封裝材料22包圍著電路重新分佈結構21周邊，電路重新分佈層213具有複數個上層銲墊211。電路增層24設置於封裝材料22與中介層212的下方，電路增層24具有金屬導線與絕緣材料，金屬導線中的縱向金屬242電性耦合至導通金屬210的下端，電路增層24具有複數個下層銲墊243，錫鉛球26安置在下層銲墊243下方。晶片27具有底部銲墊272，經由錫鉛球271電性耦合於上層銲墊211。下方填充(underfill)材料270填充於晶片27與下方的絕緣材料之間。複數個錫鉛球26，分別安置於下層銲墊243下方。中介層212具有CTE約為3ppm/K；封裝材料22與下層電路分布層的絕緣材料層具有CTE約為5~15ppm/K；因 此，習知技藝的晶片封裝，因為CTE不匹配，會造成封裝內部應力，產生裂痕而損壞整體封裝產品。一個可以解決不同材料結合之間的CTE不匹配問題，亟需被開發。
基於先前技藝中，晶片封裝因為矽基材中介層的CTE與絕緣材料的CTE不匹配，容易因為冷縮熱脹引起破裂而導致封裝產品的故障。
本發明的目的是要提供一種封裝基材，可以改善中介層與絕緣材料、封裝材料之間不同材料間的CTE不匹配，導致晶片封裝破裂問題。
本發明設立溝槽，環繞著上層電路重新分佈結構周邊，溝槽可以吸收兩邊不同材料的冷縮熱脹，致使整個封裝產品不會因為不同才見間的CTE不匹配所導致的破裂問題。
本發明實施例之一的溝槽，具有一個深度，大於封裝材料厚度。
本發明實施例之一的溝槽，具有一個寬度，在10um~200um。
本發明實施例之一的溝槽，具有一個寬度，在50um~100um。
本發明實施例之一的封裝材料，有一部分封裝材料，設置於溝槽與電路重新分佈結構之間。
本發明實施例之一的溝槽，更填入CTE較低於溝槽兩邊材料的CTE的材料；也可以填入彈性材料。
本發明實施例之一的溝槽，更填入CTE較低於溝槽兩邊材料的CTE的材料；例如矽氧樹脂。
本發明實施例之一的封裝材料，有一部分封裝材料約有10~200um寬，設置於溝槽與電路重新分佈結構之間。
本發明實施例之一的封裝材料，有一部分封裝材料約有20~70um寬，設置於溝槽與電路重新分佈結構之間。
本發明實施例之一的上層銲墊具有一個密度高於下層銲墊，致使本發明的封裝基材，上方為晶片方(chip side)，下方為電路板方(PCB side)。
本發明實施例之一的上層銲墊具有一個面積，小於下層銲墊的面積。
100‧‧‧重新分佈結構
104b‧‧‧底部
106‧‧‧上方銲墊
200‧‧‧增層電路
201‧‧‧電路
202‧‧‧絕緣材料
204b‧‧‧抗銲漆
206‧‧‧銲墊
207‧‧‧絕緣材料
21‧‧‧電路重新分佈結構
21b‧‧‧底部
210b‧‧‧縱向金屬
211‧‧‧上層金屬墊
212‧‧‧中介層
213‧‧‧電路重新分佈層
220‧‧‧溝槽
221‧‧‧封裝材料的一部分
22‧‧‧封裝材料
24‧‧‧電路增層
243‧‧‧底面金屬墊
22b‧‧‧底部
24b‧‧‧抗銲漆
300‧‧‧封裝材料
304b‧‧‧底部
320‧‧‧溝槽
321‧‧‧封裝材料的一部分
圖1 顯示先前技藝
圖2顯示本發明實施例一
圖3是本發明實施例一的溝槽一
圖4是本發明實施例二
圖5是本發明實施例二的溝槽二
圖6是本發明實施例三
圖7是本發明實施例三的溝槽三
圖8是本發明的溝槽四
圖9是本發明的溝槽五
圖10是本發明的溝槽六
圖2顯示本發明實施例一
圖2顯示一種封裝基材，包含： 電路重新分佈層213具有複數個上層金屬墊211，上層金屬墊211具有第一密度，適合晶片安置其上；電路增層24，設置於中介層212與封裝材料22的下方，中介層212具有底部21b與封裝材料22的底部22b共平面。電路增層24具有複數個底面金屬墊243，底面金屬墊243具有第二密度，適合封裝安置於印刷電路板者；所述之第二密度低於第一密度。本封裝上方為晶片方(chip side)適合晶片安置其上；本封裝下方為電路板方(PCB side)適合本封裝安置於外部的印刷電路板上。封裝材料22包裹電路重新分佈結構21；以及溝槽220，延伸包圍在電路重新分佈結構21的周圍。所述之溝槽220，具有一個深度，大於封裝材料22的厚度。封裝材料22具有上表面22a與下表面22b。上表面22a與電路重新分佈層213上表面共平面、下表面22b與中介層212下表面共平面。抗銲漆24b設置於下層銲墊243下方裸露下層銲墊243中央區域提供後續錫鉛球設置用。圖中也顯示封裝材料的一部分221，設置於溝槽220與電路重新分佈結構21的中間。其中封裝材料的一部分221，其寬度W2小於溝槽220的寬度W1。封裝材料的一部分221，其高度H小於溝槽220的深度D。
圖3是本發明實施例一的溝槽一
圖3顯示其中的溝槽220，係連續圍繞在電路重新分佈結構21的周圍。
圖中也顯示封裝材料的一部分221，設置於溝槽220與電路重新分佈結構21的中間。其中封裝材料的一部分221，其寬度小於溝槽220的寬度。封裝材料22包圍溝槽220周邊。
圖4是本發明實施例二
圖4顯示一種封裝基材，其中溝槽220，毗鄰於電路重新分佈結構21周圍。
圖5是本發明實施例二的溝槽二
圖5顯示溝槽220，係連續圍繞於電路重新分佈結構21的一個邊緣。
包含四條獨立的溝槽，分別設置於電路重新分佈結構的一個邊緣。
圖6是本發明實施例三
圖6顯示一個電路重新分佈結構100，與前面實施例不同的是，此一實施例的電路重新分佈結構100，不具有中介層(interposer)。
重新分佈結構100是一個單純的電路重新分佈層，具有絕緣材料102，以及電路101；電路101具有上方銲墊106，適合於晶片安置其上。增層電路200設置於電路重新分佈結構100的下方，增層電路200具有絕緣材料202,207以及電路201,206，電性耦合於電路重新分佈結構100的電路。此一封裝基材，其中的封裝材料300的底部304b，低於電路重新分佈結構100的底部104b。此一封裝基材的溝槽320，具有一個深度，小於封裝材料300的厚度。抗銲漆204b設置於底層銲墊206下方裸露底層銲墊206部分區域，提供後續錫鉛球安置用。
圖7是本發明實施例三的溝槽三
圖7顯示其中的溝槽320，係連續圍繞在電路重新分佈結構100的周圍。
圖中也顯示封裝材料的一部分321，設置於溝槽320與電路重新分佈結構100的中間。其中封裝材料的一部分321，其寬度小於溝槽320的寬度。
圖8是本發明的溝槽四
圖8顯示，以頂視圖觀之，本發明的「溝槽」，包含四條獨立的溝槽220/320，分別設置於電路重新分佈結構的一個邊緣。
圖9是本發明的溝槽五
圖9顯示：以頂視圖觀之，本發明的「溝槽」，可以是複數個孔220/320，設置於電路重新分佈結構的四邊外圍。
圖10是本發明的溝槽六
圖10顯示：以頂視圖觀之，本發明的「溝槽」，可以是複數個矩形溝槽220/320，設置於電路重新分佈結構的四邊外圍。
本發明的溝槽，可以使用具有較低CTE的材料如矽氧樹脂等填入其中；或是以彈性材料等，填充於溝槽中。
前述描述揭示了本發明之較佳實施例以及設計圖式，惟，較佳實施例以及設計圖式僅是舉例說明，並非用於限制本發明之權利範圍於此，凡是以均等之技藝手段實施本發明者、或是以下述之「申請專利範圍」所涵蓋之權利範圍而實施者，均不脫離本發明之精神而為申請人之權利範圍。
100‧‧‧電路重新分佈結構
101‧‧‧電路
102‧‧‧絕緣材料
104b‧‧‧下表面
106‧‧‧銲墊
200‧‧‧增層電路
201‧‧‧電路
202‧‧‧絕緣材料
204b‧‧‧抗銲漆
206‧‧‧銲墊
207‧‧‧絕緣材料
300,321‧‧‧封裝材料
304a‧‧‧上表面
304b‧‧‧下表面
304b‧‧‧底部
320‧‧‧溝槽

Claims (20)

  1. 一種封裝基材，包含：電路重新分佈結構，具有複數個上層金屬墊，所述之複數個上層金屬墊具有第一密度；晶片，安置於所述之上層金屬墊上；電路增層，設置於所述之電路重新分佈結構的下方，所述之電路增層具有複數個底面金屬墊，所述之底面金屬墊具有第二密度，適合所述之封裝安置於印刷電路板者；所述之第二密度低於所述之第一密度；封裝材料，包裹所述之電路重新分佈結構；以及溝槽，延伸包圍所述之電路重新分佈結構；其中該溝槽不包含導電材料，所述之電路重新分佈結構與所述之溝槽，整個設置於所述之晶片下方，並且所述之溝槽，從所述之封裝材料的頂面向下延伸，穿過所述之封裝材料的整個厚度，並且延伸到所述之電路增層的一部分中。
  2. 如申請專利範圍第1項所述之一種封裝基材，其中，所述之電路增層，具有最頂層介電層；最頂層電路埋設於所述之電路增層最頂層介電層中；封裝材料的底表面，與電路增層的最頂層介電層的頂表面直接接觸。
  3. 如申請專利範圍第2項所述之一種封裝基材，其中，所述之溝槽，與所述之電路重新分佈結構的整個厚度，設置於共同的高度區間；以及所述之溝槽，具有一個深度，大於所述之電路重新分佈結構的整個厚度。
  4. 如申請專利範圍第2項所述之一種封裝基材，其中所述之溝槽，連續圍繞所述之電路重新分佈結構。
  5. 一種封裝基材，包含：電路重新分佈結構，具有複數個上層金屬墊，所述之上層金屬墊，具有第一密度，適於晶片設置於其上；電路增層，設置於所述之電路重新分佈結構的底部，所述之電路增層具有複數個底面金屬墊，所述之底面金屬墊具有第二密度，適於將所述之一種封裝基材安裝到印刷電路板上，所述之第二密度低於所述之第一密度；封裝材料，包裹所述之電路重新分佈結構；晶片，設置於所述之上層金屬墊上；溝槽，圍繞所述之電路重新分佈結構；以及介電材料，填充在所述之溝槽中，其中該溝槽不包含導電材料，所述之封裝材料的一部分，設置於所述之溝槽和所述之電路重新分佈結構之間，填充在溝槽中的介電材料的材料，不同於封裝材料的材料， 所述之電路重新分佈結構與所述之溝槽，整個設置於所述之晶片下方，所述之電路增層，具有最頂層介電層；最頂層電路埋設於所述之電路增層最頂層介電層中；所述之溝槽，從所述之封裝材料的頂面向下延伸，穿過所述之封裝材料的整個厚度，並且進入所述之電路增層的最頂層的介電層，所述之封裝材料，具有底表面，與所述之電路增層的最頂層的介電層的頂表面直接接觸，所述之溝槽，與所述之電路重新分佈結構的整個厚度，設置於共同的高度區間；所述之溝槽，具有一個深度，大於所述之電路重新分佈結構的整個厚度。
  6. 如申請專利範圍第5項所述之一種封裝基材，其中，所述之溝槽和所述之電路重新分佈結構之間的封裝材料的寬度小於所述之溝槽的寬度。
  7. 如申請專利範圍第2項所述之一種封裝基材，其中所述之溝槽，毗鄰於所述之電路重新分佈結構。
  8. 如申請專利範圍第2項所述之一種封裝基材，其中，以頂視圖觀之，所述之溝槽包含分別沿著所述之電路重新分佈結構的四個側面佈置的四個獨立的分段溝槽。
  9. 如申請專利範圍第2項所述之一種封裝基材，其中，以頂 視圖觀之，所述之溝槽，包含複數個孔，設置於所述之電路重新分佈結構的四個側面。
  10. 如申請專利範圍第2項所述之一種封裝基材，其中，以頂視圖觀之，所述之溝槽，包含複數個矩形溝槽，設置於所述之電路重新分佈結構的四個側面。
  11. 如申請專利範圍第5項所述之一種封裝基材，其中，填充在所述之溝槽中的介電材料是矽氧樹脂。
  12. 如申請專利範圍第2項所述之一種封裝基材，更包含：中介層，埋設於所述之電路重新分佈結構中。
  13. 如申請專利範圍第5項所述之一種封裝基材，更包含：中介層，埋設於所述之電路重新分佈結構中。
  14. 如申請專利範圍第13項所述之一種封裝基材，其中，填充在溝槽中的介電材料是矽氧樹脂。
  15. 如申請專利範圍第1項所述之一種封裝基材，其中所述之溝槽的底部在所述之電路重新分佈結構的最底部電路下方。
  16. 如申請專利範圍第15項所述之一種封裝基材，其中，所述之溝槽，與所述之電路重新分佈結構的整個厚度，設置於共同的高度區間； 所述之溝槽，具有一個深度，大於所述之電路重新分佈結構的整個厚度。
  17. 如申請專利範圍第16項所述之一種封裝基材，其中，在所述之溝槽的底部上方的所述之溝槽的一部分，與所述之電路增層的最上層電路，設置於共同的高度區間。
  18. 如申請專利範圍第17項所述之一種封裝基材，其中，所述之電路增層，具有最頂層介電層；最頂層電路埋設於所述之電路增層最頂層介電層中；封裝材料的底表面，與電路增層的最頂層介電層的頂表面直接接觸。
  19. 如申請專利範圍第1項所述之一種封裝基材，更包含：中介層，埋設於所述之電路重新分佈結構中的。
  20. 一種封裝基材，包含：電路重新分佈結構，具有複數個上層金屬墊，所述之複數個上層金屬墊具有第一密度；電路增層，設置於所述之電路重新分佈結構的下方，所述之電路增層具有複數個底面金屬墊；所述之底面金屬墊具有第二密度，適合所述之封裝安置於印刷電路板者；所述之第二密度低於所述之第一密度；封裝材料，包裹所述之電路重新分佈結構；以及溝槽，延伸包圍所述之電路重新分佈結構； 其中該溝槽不包含導電材料，其中，當晶片安置於所述之上層金屬墊上時，所述之電路重新分佈結構與所述之溝槽，整個設置於所述之晶片下方，並且所述之溝槽，從所述之封裝材料的頂面向下延伸，所述之溝槽的底部，部分溝槽與所述之電路增層的最上層金屬電路，設置於共同的高度區間。
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US9627285B2 (en) 2017-04-18
EP2978020B1 (en) 2020-10-14
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JP2016032102A (ja) 2016-03-07
US20170162523A1 (en) 2017-06-08

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